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STM32F103XC/D/E

ARM-based 32-bit MCU

The STM32F103XC/D/E is a arm-based 32-bit mcu from STMicroelectronics. View the full STM32F103XC/D/E datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Key Specifications

ParameterValue
ConnectivityCANbus, I2C, IrDA, LINbus, SPI, UART/USART, USB
Core ProcessorARM® Cortex®-M3
Core Size32-Bit
Data ConvertersA/D 16x12b; D/A 2x12b
DigiKey ProgrammableNot Verified
DigiKey ProgrammableNot Verified
DigiKey ProgrammableNot Verified
Mounting TypeSurface Mount
Number of I/O51
Operating Temperature-40°C ~ 85°C (TA)
Oscillator TypeInternal
Oscillator TypeInternal
Oscillator TypeInternal
Package / Case64-LQFP
PeripheralsDMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Flash Memory Size256KB (256K x 8)
Program Memory TypeFLASH
RAM Size48K x 8 B
Clock Speed72MHz
Supply Voltage2V ~ 3.6V

Overview

Part: STM32F103xC, STM32F103xD, STM32F103xE

Type: ARM Cortex-M3 MCU

Description: ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces, and up to 72 MHz maximum frequency.

Operating Conditions:

  • Supply voltage: 2.0 to 3.6 V
  • Operating temperature: -40 to +125 °C (Junction temperature)
  • Max CPU frequency: 72 MHz
  • ADC conversion range: 0 to 3.6 V

Absolute Maximum Ratings:

  • Max supply voltage: 4.0 V
  • Max continuous current: 200 mA (VDD)
  • Max junction/storage temperature: -65 to +150 °C (Storage temperature)

Key Specs:

  • CPU: ARM 32-bit Cortex-M3
  • Max CPU frequency: 72 MHz
  • Flash memory: 256 to 512 Kbytes
  • SRAM: up to 64 Kbytes
  • ADC resolution: 12-bit
  • DAC resolution: 12-bit
  • SPI speed: 18 Mbit/s
  • DMIPS/MHz: 1.25 DMIPS/MHz (Dhrystone 2.1)

Features:

  • Single-cycle multiplication and hardware division
  • Flexible static memory controller (FSMC)
  • LCD parallel interface (8080/6800 modes)
  • Power-on reset (POR), Power-down reset (PDR), Programmable voltage detector (PVD)
  • Low-power modes: Sleep, Stop, Standby
  • 12-channel DMA controller
  • Serial wire debug (SWD) & JTAG interfaces
  • CRC calculation unit, 96-bit unique ID
  • ECOPACK® packages

Package:

  • LFBGA144 (144-ball)
  • LFBGA100 (100-ball)
  • WLCSP64 (64-ball)
  • LQFP144 (144-pin)
  • LQFP64 (64-pin)

Features

  • Core: ARM ® 32-bit Cortex ® -M3 CPU
  • -72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
  • -Single-cycle multiplication and hardware division
  • Memories
  • -256 to 512 Kbytes of Flash memory
  • -up to 64 Kbytes of SRAM
  • -Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
  • -LCD parallel interface, 8080/6800 modes
  • Clock, reset and supply management
  • -2.0 to 3.6 V application supply and I/Os
  • -POR, PDR, and programmable voltage detector (PVD)
  • -4-to-16 MHz crystal oscillator
  • -Internal 8 MHz factory-trimmed RC
  • -Internal 40 kHz RC with calibration
  • -32 kHz oscillator for RTC with calibration
  • Low power
  • -Sleep, Stop and Standby modes
  • -VBAT supply for RTC and backup registers
  • 3 × 12-bit, 1 μs A/D converters (up to 21 channels)
  • -Conversion range: 0 to 3.6 V
  • -Triple-sample and hold capability
  • -Temperature sensor
  • 2 × 12-bit D/A converters
  • DMA: 12-channel DMA controller
  • -Supported peripherals: timers, ADCs, DAC, SDIO, I 2 Ss, SPIs, I 2 Cs and USARTs
  • Debug mode
  • -Serial wire debug (SWD) & JTAG interfaces
  • -Cortex ® -M3 Embedded Trace Macrocell™
  • Up to 112 fast I/O ports
  • -51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

Pin Configuration

STM32F103XC/D/E Pinout

LQFP144 Package

PinNameTypeMain FunctionAlternate Functions (Default)Alternate Functions (Remap)
1PE2I/OFT PE2TRACECK/FSMC_A23
2PE3I/OFT PE3TRACED0/FSMC_A19
3PE4I/OFT PE4TRACED1/FSMC_A20
4PE5I/OFT PE5TRACED2/FSMC_A21
5PE6I/OFT PE6TRACED3/FSMC_A22
6VBATSVBAT
7PC13-TAMPER-RTCI/OPC13TAMPER-RTC
8PC14-OSC32_INI/OPC14OSC32_IN
9PC15-OSC32_OUTI/OPC15OSC32_OUT
10PF0I/OFT PF0FSMC_A0
11PF1I/OFT PF1FSMC_A1
12PF2I/OFT PF2FSMC_A2
13PF3I/OFT PF3FSMC_A3
14PF4I/OFT PF4FSMC_A4
15PF5I/OFT PF5FSMC_A5
16VSS_5SVSS_5
17VDD_5SVDD_5
18PF6I/OPF6ADC3_IN4/FSMC_NIORD
19PF7I/OPF7ADC3_IN5/FSMC_NREG
20PF8I/OPF8ADC3_IN6/FSMC_NIOWR
21PF9I/OPF9ADC3_IN7/FSMC_CD
22PF10I/OPF10ADC3_IN8/FSMC_INTR
23OSC_INIOSC_IN
24OSC_OUTOOSC_OUT
25NRSTI/ONRST
26PC0I/OPC0ADC123_IN10
27PC1I/OPC1ADC123_IN11
28PC2I/OPC2ADC123_IN12
29PC3I/OPC3ADC123_IN13
30VSSASVSSA
31VREF-SVREF-
32VREF+SVREF+
33VDDASVDDA
34PA0-WKUPI/OPA0 WKUPADC123_IN0/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR/USART2_CTS
35PA1I/OPA1ADC123_IN1/TIM2_CH2/TIM5_CH2/USART2_RTS
36PA2I/OPA2ADC123_IN2/TIM2_CH3/TIM5_CH3/USART2_TX
37PA3I/OPA3ADC123_IN3/TIM2_CH4/TIM5_CH4/USART2_RX
38VSS_4SVSS_4
39VDD_4SVDD_4
40PA4I/OPA4ADC12_IN4/DAC_OUT1/SPI1_NSS/USART2_CK
41PA5I/OPA5ADC12_IN5/DAC_OUT2/SPI1_SCK
42PA6I/OPA6ADC12_IN6/TIM3_CH1/SPI1_MISO/TIM8_BKINTIM1_BKIN
43PA7I/OPA7ADC12_IN7/TIM3_CH2/SPI1_MOSI/TIM8_CH1NTIM1_CH1N
44PC4I/OPC4ADC12_IN14
45PC5I/OPC5ADC12_IN15
46PB0I/OPB0ADC12_IN8/TIM3_CH3/TIM8_CH2NTIM1_CH2N
47PB1I/OPB1ADC12_IN9/TIM3_CH4/TIM8_CH3NTIM1_CH3N
48PB2I/OFT PB2/BOOT1
49PF11I/OFT PF11FSMC_NIOS16
50PF12I/OFT PF12FSMC_A6
51VSS_6SVSS_6
52VDD_6SVDD_6
53PF13I/OFT PF13FSMC_A7
54PF14I/OFT PF14FSMC_A8
55PF15I/OFT PF15FSMC_A9
56PG0I/OFT PG0FSMC_A10
57PG1I/OFT PG1FSMC_A11
58PE7I/OFT PE7FSMC_D4TIM1_ETR
59PE8I/OFT PE8FSMC_D5TIM1_CH1N
60PE9I/OFT PE9FSMC_D6TIM1_CH1
61VSS_7SVSS_7
62VDD_7SVDD_7
63PE10I/OFT PE10FSMC_D7TIM1_CH2N
64PE11I/OFT PE11FSMC_D8TIM1_CH2
65PE12I/OFT PE12FSMC_D9TIM1_CH3N
66PE13I/OFT PE13FSMC_D10TIM1_CH3
67PE14I/OFT PE14FSMC_D11TIM1_CH4
68PE15I/OFT PE15FSMC_D12TIM1_BKIN
69PB10I/OFT PB10I2C2_SCL/USART3_TXTIM2_CH3
70PB11I/OFT PB11I2C2_SDA/USART3_RXTIM2_CH4
71VSS_1SVSS_1
72VDD_1SVDD_1
73PB12I/OFT PB12SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN
74PB13I/OFT PB13SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N
75PB14I/OFT PB14SPI2_MISO/TIM1_CH2N/USART3_RTS
76PB15I/OFT PB15SPI2_MOSI/I2S2_SD/TIM1_CH3N
77PD8I/OFT PD8FSMC_D13USART3_TX
78PD9I/OFT PD9FSMC_D14USART3_RX
79PD10I/OFT PD10FSMC_D15USART3_CK
80PD11I/OFT PD11FSMC_A16USART3_CTS
81PD12I/OFT PD12FSMC_A17/TIM4_CH1USART3_RTS
82PD13I/OFT PD13FSMC_A18/TIM4_CH2
83VSS_8SVSS_8
84VDD_8SVDD_8
85PD14I/OFT PD14FSMC_D0/TIM4_CH3
86PD15I/OFT PD15FSMC_D1/TIM4_CH4
87PG2I/OFT PG2FSMC_A12
88PG3I/OFT PG3FSMC_A13
89PG4I/OFT PG4FSMC_A14
90PG5I/OFT PG5FSMC_A15
91PG6I/OFT PG6FSMC_INT2
92PG7I/OFT PG7FSMC_INT3
93PG8I/OFT PG8
94VSS_9SVSS_9
95VDD_9SVDD_9
96PC6I/OFT PC6I2S2_MCK/TIM8_CH1/SDIO_D6TIM3_CH1
97PC7I/OFT PC7I2S3_MCK/TIM8_CH2/SDIO_D7TIM3_CH2
98PC8I/OFT PC8TIM8_CH3/SDIO_D0TIM3_CH3
99PC9I/OFT PC9TIM8_CH4/SDIO_D1TIM3_CH4
100PA8I/OFT PA8USART1_CK/TIM1_CH1/MCO
101PA9I/OFT PA9USART1_TX/TIM1_CH2
102PA10I/OFT PA10USART1_RX/TIM1_CH3
103PA11I/OFT PA11USART1_CTS/USBDM/CAN_RX/TIM1_CH4
104PA12I/OFT PA12USART1_RTS/USBDP/CAN_TX/TIM1_ETR
105PA13I/OFTJTMS-SWDIOPA13
106NCNot connected
107VSS_2SVSS_2
108VDD_2SVDD_2
109PA14I/OFTJTCK-SWCLKPA14
110PA15I/OFTJTDISPI3_NSS/I2S3_WS/TIM2_CH1_ETR/SPI1_NSS
111PC10I/OFTPC10UART4_TX/SDIO_D2/USART3_TX
112PC11I/OFTPC11UART4_RX/SDIO_D3/USART3_RX
113PC12I/OFTPC12UART5_TX/SDIO_CK/USART3_CK
114PD0I/OFTOSC_INFSMC_D2/CAN_RX
115PD1I/OFTOSC_OUTFSMC_D3/CAN_TX
116PD2I/OFTPD2TIM3_ETR/UART5_RX/SDIO_CMD
117PD3I/OFTPD3FSMC_CLK/USART2_CTS
118PD4I/OFTPD4FSMC_NOE/USART2_RTS
119PD5I/OFTPD5FSMC_NWE/USART2_TX
120VSS_10SVSS_10
121VDD_10SVDD_10
122PD6I/OFTPD6FSMC_NWAIT/USART2_RX
123PD7I/OFTPD7FSMC_NE1/FSMC_NCE2/USART2_CK
124PG9I/OFTPG9FSMC_NE2/FSMC_NCE3
125PG10I/OFTPG10FSMC_NCE4_1/FSMC_NE3
126PG11I/OFTPG11FSMC_NCE4_2
127PG12I/OFTPG12FSMC_NE4
128PG13I/OFTPG13FSMC_A24
129PG14I/OFTPG14FSMC_A25
130VSS_11SVSS_11
131VDD_11SVDD_11
132PG15I/OFTPG15
133PB3I/OFTJTDOSPI3_SCK/I2S3_CK/TIM2_CH2/SPI1_SCK/PB3/TRACESWO
134PB4I/OFTNJTRSTSPI3_MISO/PB4/TIM3_CH1/SPI1_MISO
135PB5I/OPB5I2C1_SMBA/SPI3_MOSI/I2S3_SD/TIM3_CH2/SPI1_MOSI
136PB6I/OFTPB6I2C1_SCL/TIM4_CH1/USART1_TX
137PB7I/OFTPB7I2C1_SDA/FSMC_NADV/TIM4_CH2/USART1_RX
138BOOT0IBOOT0
139PB8I/OFTPB8TIM4_CH3/SDIO_D4/I2C1_SCL/CAN_RX
140PB9I/OFTPB9TIM4_CH4/SDIO_D5/I2C1_SDA/CAN_TX
141PE0I/OFTPE0TIM4_ETR/FSMC_NBL0
142PE1I/OFTPE1FSMC_NBL1
143VSS_3SVSS_3
144VDD_3SVDD_3

Notes

  • FT designation: Pins marked "FT" are 5V-tolerant.
  • PC13, PC14, PC15: Limited output capability (3 mA max sink current, 2 MHz max speed, 30 pF max load). Not suitable as current sources.
  • Pins 114–115 (PD0/PD1): In LQFP144 package, these pins are available by default as GPIO. In LQFP64 package, they are configured as OSC_IN/OSC_OUT after reset but can be remapped via software.
  • Alternate functions: Many pins support remapping via software configuration. Refer to the STM32F10xxx reference manual for detailed remapping options.
  • FSMC availability: FSMC functions (Flexible Static Memory Controller) are not available in LQFP64 package devices.

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 46 and Table 48 , respectively.

Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 10 .

Table 48. I/O AC characteristics (1)

MODEx[1:0] bit value (1)SymbolParameterConditionsMinMaxUnit
10f max(IO)outMaximum frequency (2)C L = 50 pF, V DD = 2 V to 3.6 V-2MHz
10t f(IO)outOutput high to low level fall timeC L = 50 pF, V DD = 2 V to 3.6 V-125 (3)ns
10t r(IO)outOutput low to high level rise timeC L = 50 pF, V DD = 2 V to 3.6 V-125 (3)ns
01f max(IO)outMaximum frequency (2)C L = 50 pF, V DD = 2 V to 3.6 V-10MHz
01t f(IO)outOutput high to low level fall timeC L = 50 pF, V DD = 2 V to 3.6 V-25 (3)ns
01t r(IO)outOutput low to high level rise timeC L = 50 pF, V DD = 2 V to 3.6 V-25 (3)ns
11F max(IO)outMaximum frequency (2)C L = 30 pF, V DD = 2.7 V to 3.6 V-50MHz
11F max(IO)outMaximum frequency (2)C L = 50 pF, V DD = 2.7 V to 3.6 V-30MHz
11F max(IO)outMaximum frequency (2)C L = 50 pF, V DD = 2 V to 2.7 V-20MHz
11t f(IO)outOutput high to low level fall timeC L = 30 pF, V DD = 2.7 V to 3.6 V-5 (3)ns
11t f(IO)outOutput high to low level fall timeC L = 50 pF, V DD = 2.7 V to 3.6 V-8 (3)ns
11t f(IO)outOutput high to low level fall timeC L = 50 pF, V DD = 2 V to 2.7 V-12 (3)ns
11t r(IO)outOutput low to high level rise timeC L = 30 pF, V DD = 2.7 V to 3.6 V-5 (3)ns
11t r(IO)outOutput low to high level rise timeC L = 50 pF, V DD = 2.7 V to 3.6 V-8 (3)ns
11t r(IO)outOutput low to high level rise timeC L = 50 pF, V DD = 2 V to 2.7 V-12 (3)ns
-t EXTIpwPulse width of external signals detected by the EXTI controller-10-ns
  1. The maximum frequency is defined in Figure 46 .
  2. Guaranteed by design.

Figure 46. I/O AC characteristics definition

Figure 46. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics , Table 8: Current characteristics , and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 7. Voltage characteristics

SymbolRatingsMinMaxUnit
V DD -V SSExternal main supply voltage (including V DDA and V DD ) (1)-0.34.0V
V IN (2)Input voltage on five volt tolerant pinV SS - 0.3V DD + 4.0V
V IN (2)Input voltage on any other pinV SS - 0.34.0V
\∆ V DDx \Variations between different V DD power pins-
\V SSX - V SS \Variations between all the different ground pins (3)-
V ESD(HBM)Electrostatic discharge voltage (human body model)see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)-

Table 8. Current characteristics

Table 8. Current characteristics

SymbolRatingsMax.Unit
I VDDTotal current into V DD /V DDA power lines (source) (1)150mA
I VSSTotal current out of V SS ground lines (sink) (1)150mA
I IOOutput current sunk by any I/O and control pin25mA
I IOOutput current source by any I/Os and control pin- 25mA
I INJ(PIN) (2)Injected current on five volt tolerant pins (3)-5/+0mA
I INJ(PIN) (2)Injected current on any other pin (4)± 5mA
Σ I INJ(PIN)Total injected current (sum of all I/O and control pins) (5)± 25mA
  1. Positive injection is not possible on these I/Os. A negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.
  2. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.
  3. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

136

Table 9. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature150°C

Thermal Information

The maximum chip junction temperature (T J max) must never exceed the values given in Table 10: General operating conditions on page 44 .

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.

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