STM32F103XGSTM32F103XF

Part: STM32F103xC, STM32F103xD, STM32F103xE

Type: ARM®-based 32-bit MCU

Key Specs:

• Core: ARM® 32-bit Cortex®-M3 CPU
• Maximum CPU Frequency: 72 MHz
• Flash Memory: 256 to 512 Kbytes
• SRAM: Up to 64 Kbytes
• Application Supply Voltage: 2.0 to 3.6 V
• ADC: 3 × 12-bit, 1 μs
• DAC: 2 × 12-bit
• I/O Ports: Up to 112

Features:

• 1.25 DMIPS/MHz (Dhrystone 2.1) performance
• Single-cycle multiplication and hardware division
• Flexible static memory controller (Compact Flash, SRAM, PSRAM, NOR, NAND support)
• LCD parallel interface (8080/6800 modes)
• POR, PDR, and programmable voltage detector (PVD)
• Low power modes: Sleep, Stop, Standby
• VBAT supply for RTC and backup registers
• Triple-sample and hold capability for ADC
• Temperature sensor
• 12-channel DMA controller
• Serial wire debug (SWD) & JTAG interfaces
• Cortex®-M3 Embedded Trace Macrocell™
• Almost all I/Os 5 V-tolerant
• Up to 11 timers (16-bit, motor control PWM, watchdog, SysTick, basic)
• Up to 13 communication interfaces (I2C, USART, SPI, CAN, USB, SDIO)
• CRC calculation unit
• 96-bit unique ID
• ECOPACK® packages

Applications:

• null

Package:

• LFBGA100: 10 × 10 mm
• LFBGA144: 10 × 10 mm
• WLCSP64
• LQFP144
• LQFP100
• LQFP64

{
  "manufacturer": null,
  "part_family": "STM32F103xx",
  "component_type": "Microcontroller",

• Core: ARM® 32-bit Cortex®-M3 CPU
  • 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
  • Single-cycle multiplication and hardware division
• Memories
  • 256 to 512 Kbytes of Flash memory
  • up to 64 Kbytes of SRAM
  • Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
  • LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
  • 2.0 to 3.6 V application supply and I/Os
  • POR, PDR, and programmable voltage detector (PVD)
  • 4-to-16 MHz crystal oscillator
  • Internal 8 MHz factory-trimmed RC
  • Internal 40 kHz RC with calibration
  • 32 kHz oscillator for RTC with calibration
• Low power
  • Sleep, Stop and Standby modes
  • VBAT supply for RTC and backup registers
• 3 × 12-bit, 1 μs A/D converters (up to 21 channels)
  • Conversion range: 0 to 3.6 V
  • Triple-sample and hold capability
  • Temperature sensor
• 2 × 12-bit D/A converters
• DMA: 12-channel DMA controller
• Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Debug mode
  • Serial wire debug (SWD) & JTAG interfaces
  • Cortex®-M3 Embedded Trace Macrocell™
• Up to 112 fast I/O ports
  • 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

LFBGA100 10 × 10 mm LFBGA144 10 × 10 mm

• Up to 11 timers
  • Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
  • 2 × 16-bit motor control PWM timers with deadtime generation and emergency stop
  • 2 × watchdog timers (Independent and Window)
  • SysTick timer: a 24-bit downcounter
  • 2 × 16-bit basic timers to drive the DAC
• Up to 13 communication interfaces
  • Up to 2 × I2C interfaces (SMBus/PMBus)
  • Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
  • Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed
  • CAN interface (2.0B Active)
  • USB 2.0 full speed interface
  • SDIO interface
• CRC calculation unit, 96-bit unique ID
• ECOPACK® packages

Table 1.Device summary

Reference	Part number
STM32F103xC	STM32F103RC STM32F103VC STM32F103ZC
STM32F103xD	STM32F103RD STM32F103VD STM32F103ZD
STM32F103xE	STM32F103RE STM32F103ZE STM32F103VE

November 2015 DocID14611 Rev 12 1/144

This is information on a product in full production.

	1	2	3	4	5	6	7	8	9	10	11	12
A	PC13- TAMPER-RTC	PE3	PE2	PE1	PE0	PB4 JTRST	PB3 JTDO	PD6	PD7	PA15 JTDI	PA14 JTCK	PA13 JTMS
B	PC14- OSC32_IN	PE4	PE5	PE6	PB9	PB5	PG15	PG12	PD5	PC11	PC10	PA12
C	PC15- OSC32_OUT	VBAT	PF0	PF1	PB8	PB6	PG14	PG11	PD4	PC12	NC	PA11
D	OSC_IN	VSS_5	VDD_5	PF2	BOOT0	PB7	PG13	PG10	PD3	PD1	PA10	PA9
E	OSC_OUT	PF3	PF4	PF5	VSS_3	VSS_11	VSS_10	PG9	PD2	PD0	PC9	PA8
F	NRST	PF7	PF6	VDD_4	VDD_3	VDD_11	VDD_10	VDD_8	VDD_2	VDD_9	PC8	PC7
G	PF10	PF9	PF8	VSS_4	VDD_6	VDD_7	VDD_1	VSS_8	VSS_2	VSS_9	PG8	PC6
H	PC0	PC1	PC2	PC3	VSS_6	VSS_7	VSS_1	PE11	PD11	PG7	PG6	PG5
J	VSSA	PA0-WKUP	PA4	PC4	PB2/ BOOT1	PG1	PE10	PE12	PD10	PG4	PG3	PG2
K	VREF-	PA1	PA5	PC5	PF13	PG0	PE9	PE13	PD9	PD13	PD14	PD15
L	VREF+	PA2	PA6	PB0	PF12	PF15	PE8	PE14	PD8	PD12	PB14	PB15
M	VDDA	PA3	PA7	PB1	PF11	PF14	PE7	PE15	PB10	PB11	PB12	PB13

Figure 3. STM32F103xC/D/E BGA144 ballout

1. The above figure shows the package top view.

	1	2	3	4	5	6	7	8	9	10
A	PC14- OSC32_IN	PC13- TAMPER RTC	PE2	PB9	PB7	PB4	PB3	PA15	PA14	PA13
B	PC15- OSC32_OUT	VBAT	PE3	PB8	PB6	PD5	PD2	PC11	PC10	PA12
C	OSC_IN	V SS_5	PE4	PE1	PB5	PD6	PD3	PC12	PA9	PA11
D	OSC_OUT	VDD_5	PE5	PE0	BOOT0	PD7	PD4	PD0	PA8	PA10
E	NRST	PC2	PE6	VSS_4	V SS_3	VSS_2	VSS_1	PD1	PC9	PC7
F	PC0	PC1	PC3	VDD_4	V DD_3	VDD_2	VDD_1	NC	PC8	PC6
G	VSSA	PA0-WKUP	PA4	PC4	PB2	PE10	PE14	PB15	PD11	PD15
H	VREF–	PA1	PA5	PC5	PE7	PE11	PE15	PB14	PD10	PD14
J	V REF+	PA2	PA6	PB0	PE8	PE12	PB10	PB13	PD9	PD13
K	V DDA	PA3	PA7	PB1	PE9	PE13	PB11	PB12	PD8	PD12

Figure 4. STM32F103xC/D/E performance line BGA100 ballout

Figure 5. STM32F103xC/D/E performance line LQFP144 pinout

Figure 6. STM32F103xC/D/E performance line LQFP100 pinout

Figure 7. STM32F103xC/D/E performance line LQFP64 pinout

Figure 8. STM32F103xC/D/E performance line WLCSP64 ballout, ball side

Pins										Alternate functions(4)
LFBGA144	LFBGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	Type(1)	I / O Level(2)	Main function(3) (after reset)	Default
A3	A3	-	-	1	1	PE2		I/O FT	PE2	TRACECK/ FSMC_A23
A2	B3	-	-	2	2	PE3		I/O FT	PE3	TRACED0/FSMC_A19
B2	C3	-	-	3	3	PE4		I/O FT	PE4	TRACED1/FSMC_A20
B3	D3	-	-	4	4	PE5		I/O FT	PE5	TRACED2/FSMC_A21
B4	E3	-	-	5	5	PE6		I/O FT	PE6	TRACED3/FSMC_A22
C2	B2	C6	1	6	6	VBAT	S	-	VBAT	-
A1	A2	C8	2	7	7	PC13-TAMPER RTC(5)	I/O	-	PC13(6)	TAMPER-RTC
B1	A1	B8	3	8	8	PC14- OSC32_IN(5)	I/O	-	PC14(6)	OSC32_IN
C1	B1	B7	4	9	9	PC15- OSC32_OUT(5)	I/O	-	PC15(6)	OSC32_OUT
C3	-	-	-	-	10	PF0		I/O FT	PF0	FSMC_A0
C4	-	-	-	-	11	PF1		I/O FT	PF1	FSMC_A1
D4	-	-	-	-	12	PF2		I/O FT	PF2	FSMC_A2
E2	-	-	-	-	13	PF3		I/O FT	PF3	FSMC_A3
E3	-	-	-	-	14	PF4		I/O FT	PF4	FSMC_A4
E4	-	-	-	-	15	PF5		I/O FT	PF5	FSMC_A5
D2	C2	-	-	10	16	VSS_5	S	-	VSS_5	-
D3	D2	-	-	11	17	VDD_5	S	-	VDD_5	-
F3	-	-	-	-	18	PF6	I/O	-	PF6	ADC3_IN4/FSMC_NIORD
F2	-	-	-	-	19	PF7	I/O	-	PF7	ADC3_IN5/FSMC_NREG
G3	-	-	-	-	20	PF8	I/O	-	PF8	ADC3_IN6/FSMC_NIOWR
G2	-	-	-	-	21	PF9	I/O	-	PF9	ADC3_IN7/FSMC_CD
G1	-	-	-	-	22	PF10	I/O	-	PF10	ADC3_IN8/FSMC_INTR
D1	C1	D8	5	12	23	OSC_IN	I	-	OSC_IN	-
E1	D1	D7	6	13	24	OSC_OUT	O	-	OSC_OUT	-
F1	E1	C7	7	14	25	NRST	I/O	-	NRST	-
H1	F1	E8	8	15	26	PC0	I/O	-	PC0	ADC123_IN10
H2	F2	F8	9	16	27	PC1	I/O	-	PC1	ADC123_IN11

Table 5. High-density STM32F103xC/D/E pin definitions

Pins										Alternate functions(4)
LFBGA144	LFBGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	Type(1)	I / O Level(2)	Main function(3) (after reset)	Default
H3	E2	D6	10	17	28	PC2	I/O	-	PC2	ADC123_IN12
H4	F3	-	11	18	29	PC3(7)	I/O	-	PC3	ADC123_IN13
J1	G1	E7	12	19	30	VSSA	S	-	VSSA	-
K1	H1	-	-	20	31	VREF-	S	-	VREF-	-
L1	J1	F7 (8)	-	21	32	VREF+	S	-	VREF+	-
M1	K1	G8	13	22	33	VDDA	S	-	VDDA	-
J2	G2	F6	14	23	34	PA0-WKUP	I/O	-	PA0	WKUP/USART2_CTS(9) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR
K2	H2	E6	15	24	35	PA1	I/O	-	PA1	USART2_RTS(9) ADC123_IN1/ TIM5_CH2/TIM2_CH2(9)
L2	J2	H8	16	25	36	PA2	I/O	-	PA2	USART2_TX(9)/TIM5_CH3 ADC123_IN2/ TIM2_CH3 (9)
M2	K2	G7	17	26	37	PA3	I/O	-	PA3	USART2_RX(9)/TIM5_CH4 ADC123_IN3/TIM2_CH4(9)
G4	E4	F5	18	27	38	VSS_4	S	-	VSS_4	-
F4	F4	G6	19	28	39	VDD_4	S	-	VDD_4	-
J3	G3	H7	20	29	40	PA4	I/O	-	PA4	SPI1_NSS(9)/ USART2_CK(9) DAC_OUT1/ADC12_IN4
K3	H3	E5	21	30	41	PA5	I/O	-	PA5	SPI1_SCK(9) DAC_OUT2 ADC12_IN5
L3	J3	G5	22	31	42	PA6	I/O	-	PA6	SPI1_MISO(9) TIM8_BKIN/ADC12_IN6 TIM3_CH1(9)
M3	K3	G4	23	32	43	PA7	I/O	-	PA7	SPI1_MOSI(9)/ TIM8_CH1N/ADC12_IN7 TIM3_CH2(9)
J4	G4	H6	24	33	44	PC4	I/O	-	PC4	ADC12_IN14
K4	H4	H5	25	34	45	PC5	I/O	-	PC5	ADC12_IN15

Table 5. High-density STM32F103xC/D/E pin definitions (continued)

Pins										Alternate functions(4)
LFBGA144	LFBGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	Type(1)	I / O Level(2)	Main function(3) (after reset)	Default
L4	J4	H4	26	35	46	PB0	I/O	-	PB0	ADC12_IN8/TIM3_CH3 TIM8_CH2N
M4	K4	F4	27	36	47	PB1	I/O	-	PB1	ADC12_IN9/TIM3_CH4(9) TIM8_CH3N
J5	G5	H3	28	37	48	PB2		I/O FT	PB2/BOOT1	-
M5	-	-	-	-	49	PF11		I/O FT	PF11	FSMC_NIOS16
L5	-	-	-	-	50	PF12		I/O FT	PF12	FSMC_A6
H5	-	-	-	-	51	VSS_6	S	-	VSS_6	-
G5	-	-	-	-	52	VDD_6	S	-	VDD_6	-
K5	-	-	-	-	53	PF13		I/O FT	PF13	FSMC_A7
M6	-	-	-	-	54	PF14		I/O FT	PF14	FSMC_A8
L6	-	-	-	-	55	PF15		I/O FT	PF15	FSMC_A9
K6	-	-	-	-	56	PG0		I/O FT	PG0	FSMC_A10
J6	-	-	-	-	57	PG1		I/O FT	PG1	FSMC_A11
M7	H5	-	-	38	58	PE7		I/O FT	PE7	FSMC_D4
L7	J5	-	-	39	59	PE8		I/O FT	PE8	FSMC_D5
K7	K5	-	-	40	60	PE9		I/O FT	PE9	FSMC_D6
H6	-	-	-	-	61	VSS_7	S	-	VSS_7	-
G6	-	-	-	-	62	VDD_7	S	-	VDD_7	-
J7	G6	-	-	41	63	PE10		I/O FT	PE10	FSMC_D7
H8	H6	-	-	42	64	PE11		I/O FT	PE11	FSMC_D8
J8	J6	-	-	43	65	PE12		I/O FT	PE12	FSMC_D9
K8	K6	-	-	44	66	PE13		I/O FT	PE13	FSMC_D10
L8	G7	-	-	45	67	PE14		I/O FT	PE14	FSMC_D11
M8	H7	-	-	46	68	PE15		I/O FT	PE15	FSMC_D12
M9	J7	G3	29	47	69	PB10		I/O FT	PB10	I2C2_SCL/USART3_TX(9)
M10 K7		F3	30	48	70	PB11		I/O FT	PB11	I2C2_SDA/USART3_RX(9)
H7	E7	H2	31	49	71	VSS_1	S	-	VSS_1	-
G7	F7	H1	32	50	72	VDD_1	S	-	VDD_1	-

Table 5. High-density STM32F103xC/D/E pin definitions (continued)

Pins										Alternate functions(4)
LFBGA144	LFBGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	Type(1)	I / O Level(2)	Main function(3) (after reset)	Default
M11	K8	G2	33	51	73	PB12		I/O FT	PB12	SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK(9)/ TIM1_BKIN(9)
M12	J8	G1	34	52	74	PB13		I/O FT	PB13	SPI2_SCK/I2S2_CK USART3_CTS(9)/ TIM1_CH1N
L11	H8	F2	35	53	75	PB14		I/O FT	PB14	SPI2_MISO/TIM1_CH2N USART3_RTS(9)/
L12	G8	F1	36	54	76	PB15		I/O FT	PB15	SPI2_MOSI/I2S2_SD TIM1_CH3N(9)/
L9	K9	-	-	55	77	PD8	I/O FT		PD8	FSMC_D13
K9	J9	-	-	56	78	PD9		I/O FT	PD9	FSMC_D14
J9	H9	-	-	57	79	PD10		I/O FT	PD10	FSMC_D15
H9	G9	-	-	58	80	PD11		I/O FT	PD11	FSMC_A16
	L10 K10	-	-	59	81	PD12		I/O FT	PD12	FSMC_A17
K10 J10		-	-	60	82	PD13		I/O FT	PD13	FSMC_A18
G8	-	-	-	-	83	VSS_8	S	-	VSS_8	-
F8	-	-	-	-	84	VDD_8	S	-	VDD_8	-
	K11 H10	-	-	61	85	PD14	I/O FT		PD14	FSMC_D0
	K12 G10	-	-	62	86	PD15	I/O FT		PD15	FSMC_D1
J12	-	-	-	-	87	PG2		I/O FT	PG2	FSMC_A12
J11	-	-	-	-	88	PG3		I/O FT	PG3	FSMC_A13
J10	-	-	-	-	89	PG4		I/O FT	PG4	FSMC_A14
H12	-	-	-	-	90	PG5		I/O FT	PG5	FSMC_A15
H11	-	-	-	-	91	PG6		I/O FT	PG6	FSMC_INT2
H10	-	-	-	-	92	PG7		I/O FT	PG7	FSMC_INT3
G11	-	-	-	-	93	PG8		I/O FT	PG8	-
G10	-	-	-	-	94	VSS_9	S	-	VSS_9	-
F10	-	-	-	-	95	VDD_9	S	-	VDD_9	-

		Pins								Alternate functions(4)
LFBGA144	LFBGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	Type(1)	I / O Level(2)	Main function(3) (after reset)	Default
	G12 F10 E1		37	63	96	PC6		I/O FT	PC6	I2S2_MCK/ TIM8_CH1/SDIO_D6
	F12 E10 E2		38	64	97	PC7		I/O FT	PC7	I2S3_MCK/ TIM8_CH2/SDIO_D7
F11	F9	E3	39	65	98	PC8		I/O FT	PC8	TIM8_CH3/SDIO_D0
E11	E9	D1	40	66	99	PC9		I/O FT	PC9	TIM8_CH4/SDIO_D1
E12	D9	E4	41		67 100	PA8		I/O FT	PA8	USART1_CK/ TIM1_CH1(9)/MCO
D12 C9		D2	42		68 101	PA9		I/O FT	PA9	USART1_TX(9)/ TIM1_CH2(9)
	D11 D10 D3		43		69 102	PA10		I/O FT	PA10	USART1_RX(9)/ TIM1_CH3(9)
	C12 C10 C1		44		70 103	PA11		I/O FT	PA11	USART1_CTS/USBDM CAN_RX(9)/TIM1_CH4(9)
	B12 B10 C2		45		71 104	PA12		I/O FT	PA12	USART1_RTS/USBDP/ CAN_TX(9)/TIM1_ETR(9)
	A12 A10 D4		46		72 105	PA13		I/O FT	JTMS SWDIO	-
C11	F8	-	-		73 106		Not connected			-
G9	E6	B1	47		74 107	VSS_2	S	-	VSS_2	-
F9	F6	A1	48		75 108	VDD_2	S	-	VDD_2	-
A11	A9	B2	49		76 109	PA14		I/O FT	JTCK SWCLK	-
A10	A8	C3	50		77 110	PA15		I/O FT	JTDI	SPI3_NSS/ I2S3_WS
B11	B9	A2	51	78	111	PC10		I/O FT	PC10	UART4_TX/SDIO_D2
B10	B8	B3	52		79 112	PC11		I/O FT	PC11	UART4_RX/SDIO_D3
C10 C8		C4	53		80 113	PC12		I/O FT	PC12	UART5_TX/SDIO_CK
E10	D8	D8	5		81 114	PD0		I/O FT	OSC_IN(10)	FSMC_D2(11)
D10	E8	D7	6		82 115	PD1			I/O FT OSC_OUT(10)	FSMC_D3(11)
E9	B7	A3	54		83 116	PD2		I/O FT	PD2	TIM3_ETR/UART5_RX SDIO_CMD
D9	C7	-	-		84 117	PD3		I/O FT	PD3	FSMC_CLK

		Pins								Alternate functions(4)
LFBGA144	LFBGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	Type(1)	I / O Level(2)	Main function(3) (after reset)	Default
C9	D7	-	-		85 118	PD4		I/O FT	PD4	FSMC_NOE
B9	B6	-	-		86 119	PD5		I/O FT	PD5	FSMC_NWE
E7	-	-	-	-	120	VSS_10	S	-	VSS_10	-
F7	-	-	-	-	121	VDD_10	S	-	VDD_10	-
A8	C6	-	-		87 122	PD6		I/O FT	PD6	FSMC_NWAIT
A9	D6	-	-		88 123	PD7		I/O FT	PD7	FSMC_NE1/FSMC_NCE2
E8	-	-	-	-	124	PG9		I/O FT	PG9	FSMC_NE2/FSMC_NCE3
D8	-	-	-	-	125	PG10		I/O FT	PG10	FSMC_NCE4_1/ FSMC_NE3
C8	-	-	-	-	126	PG11		I/O FT	PG11	FSMC_NCE4_2
B8	-	-	-	-	127	PG12		I/O FT	PG12	FSMC_NE4
D7	-	-	-	-	128	PG13		I/O FT	PG13	FSMC_A24
C7	-	-	-	-	129	PG14		I/O FT	PG14	FSMC_A25
E6	-	-	-	-	130	VSS_11	S	-	VSS_11	-
F6	-	-	-	-	131	VDD_11	S	-	VDD_11	-
B7	-	-	-	-	132	PG15		I/O FT	PG15	-
A7	A7	A4	55		89 133	PB3		I/O FT	JTDO	SPI3_SCK / I2S3_CK/
A6	A6	B4	56		90 134	PB4		I/O FT	NJTRST	SPI3_MISO
B6	C5	A5	57		91 135	PB5	I/O	-	PB5	I2C1_SMBA/ SPI3_MOSI I2S3_SD
C6	B5	B5	58		92 136	PB6		I/O FT	PB6	I2C1_SCL(9)/ TIM4_CH1(9)
D6	A5	C5	59		93 137	PB7		I/O FT	PB7	I2C1_SDA(9) / FSMC_NADV / TIM4_CH2(9)
D5	D5	A6	60		94 138	BOOT0	I	-	BOOT0	-
C5	B4	D5	61		95 139	PB8		I/O FT	PB8	TIM4_CH3(9)/SDIO_D4
B5	A4	B6	62		96 140	PB9		I/O FT	PB9	TIM4_CH4(9)/SDIO_D5

		Pins								Alternate functions(4)
A3	A3	-	-	1	1	PE2	I/O	FT	PE2	TRACECK
Table 5. High-density STM32F103xC/D/E pin definitions (continued)

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

• 1. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
• 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
• 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
• 7. In the WCLSP64 package, the PC3 I/O pin is not bonded and it must be configured by software to output mode (Push-pull) and writing 0 to the data register in order to avoid an extra consumption during low-power modes.
• 1. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The VREF+ functionality is provided instead.
• 9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
• 10. For the WCLSP64/LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
• 11. For devices delivered in LQFP64 packages, the FSMC function is not available.

Pins	CF	CF/IDE	FSMC NOR/PSRAM/ SRAM	NOR/PSRAM Mux	NAND 16 bit	LQFP100 BGA100(1)
PE2	-	-	A23	A23	-	Yes
PE3	-	-	A19	A19	-	Yes
PE4	-	-	A20	A20	-	Yes
PE5	-	-	A21	A21	-	Yes
PE6	-	-	A22	A22	-	Yes
PF0	A0	A0	A0	-	-	-
PF1	A1	A1	A1	-	-	-
PF2	A2	A2	A2	-	-	-
PF3	A3	-	A3	-	-	-
PF4	A4	-	A4	-	-	-
PF5	A5	-	A5	-	-	-
PF6	NIORD	NIORD	-	-	-	-
PF7	NREG	NREG	-	-	-	-
PF8	NIOWR	NIOWR	-	-	-	-
PF9	CD	CD	-	-	-	-
PF10	INTR	INTR	-	-	-	-
PF11	NIOS16	NIOS16	-	-	-	-
PF12	A6	-	A6	-	-	-
PF13	A7	-	A7	-	-	-
PF14	A8	-	A8	-	-	-
PF15	A9	-	A9	-	-	-
PG0	A10	-	A10	-	-	-
PG1	-	-	A11	-	-	-
PE7	D4	D4	D4	DA4	D4	Yes
PE8	D5	D5	D5	DA5	D5	Yes
PE9	D6	D6	D6	DA6	D6	Yes
PE10	D7	D7	D7	DA7	D7	Yes
PE11	D8	D8	D8	DA8	D8	Yes
PE12	D9	D9	D9	DA9	D9	Yes
PE13	D10	D10	D10	DA10	D10	Yes
PE14	D11	D11	D11	DA11	D11	Yes
PE15	D12	D12	D12	DA12	D12	Yes
PD8	D13	D13	D13	DA13	D13	Yes

Table 6. FSMC pin definition

Pins	CF	CF/IDE	NOR/PSRAM/ SRAM	NOR/PSRAM Mux	NAND 16 bit	LQFP100 BGA100(1)
PD9	D14	D14	D14	DA14	D14	Yes
PD10	D15	D15	D15	DA15	D15	Yes
PD11	-	-	A16	A16	CLE	Yes
PD12	-	-	A17	A17	ALE	Yes
PD13	-	-	A18	A18	-	Yes
PD14	D0	D0	D0	DA0	D0	Yes
PD15	D1	D1	D1	DA1	D1	Yes
PG2	-	-	A12	-	-	-
PG3	-	-	A13	-	-	-
PG4	-	-	A14	-	-	-
PG5	-	-	A15	-	-	-
PG6	-	-	-	-	INT2	-
PG7	-	-	-	-	INT3	-
PD0	D2	D2	D2	DA2	D2	Yes
PD1	D3	D3	D3	DA3	D3	Yes
PD3	-	-	CLK	CLK	-	Yes
PD4	NOE	NOE	NOE	NOE	NOE	Yes
PD5	NWE	NWE	NWE	NWE	NWE	Yes
PD6	NWAIT	NWAIT	NWAIT	NWAIT	NWAIT	Yes
PD7	-	-	NE1	NE1	NCE2	Yes
PG9	-	-	NE2	NE2	NCE3	-
PG10	NCE4_1	NCE4_1	NE3	NE3	-	-
PG11	NCE4_2	NCE4_2	-	-	-	-
PG12	-	-	NE4	NE4	-	-
PG13	-	-	A24	A24	-	-
PG14	-	-	A25	A25	-	-
PB7	-	-	NADV	NADV	-	Yes
PE0	-	-	NBL0	NBL0	-	Yes
PE1	-	-	NBL1	NBL1	-	Yes

1. Ports F and G are not available in devices delivered in 100-pin packages.

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

5.1.6 Power supply scheme

Figure 12. Power supply scheme

Caution: In Figure 12, the 4.7 μF capacitor must be connected to VDD3.

5.1.7 Current consumption measurement

Figure 13. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD–VSS	External main supply voltage (including VDDA (1) and VDD)	–0.3	4.0
VIN(2)	Input voltage on five volt tolerant pin	VSS - 0.3	VDD + 4.0	V
	Input voltage on any other pin	VSS -0.3	4.0
ΔVDDx	Variations between different VDD power pins	-	50
VSSX -VSS	Variations between all the different ground pins(3)		50	mV
VESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)		-

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum allowed injected current values.

3. Include VREF- pin.

Table 8. Current characteristics

Symbol	Ratings	Max.	Unit
IVDD	Total current into VDD/VDDA power lines (source)(1)	150
IVSS	Total current out of VSS ground lines (sink)(1)	150
IIO	Output current sunk by any I/O and control pin	25
	Output current source by any I/Os and control pin	-25	mA
IINJ(PIN)(2)	Injected current on five volt tolerant pins(3)	-5/+0
	Injected current on any other pin(4)	± 5
ΣIINJ(PIN)	Total injected current (sum of all I/O and control pins)(5)	± 25

1. Negative injection disturbs the analog performance of the device. See note 3 below Table 62 on page 109.

2. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.

3. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.

4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	150	°C

Table 9. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Symbol	Parameter	Conditions	Min	Max	Unit
fHCLK	Internal AHB clock frequency	-	0	72	MHz
fPCLK1	Internal APB1 clock frequency	-	0	36	MHz
fPCLK2	Internal APB2 clock frequency	-	0	72	MHz
VDD	Standard operating voltage	-	2	3.6	V
VDDA(1)	Analog operating voltage (ADC not used)	Must be the same potential	2	3.6	V
	Analog operating voltage (ADC used)	as VDD(2)	2.4	3.6	V
VBAT	Backup operating voltage	-	1.8	3.6	V
PD	Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(3)	LQFP144	-	666	mW
		LQFP100	-	434	mW
		LQFP64	-	444	mW
		LFBGA100	-	500	mW
		LFBGA144	-	500	mW
		WLCSP64	-	400	mW
TA	Ambient temperature for 6 suffix version	Maximum power dissipation	–40	85	°C
		Low-power dissipation(4)	–40	105	°C
	Ambient temperature for 7 suffix version	Maximum power dissipation	–40	105	°C
		Low-power dissipation(4)	–40	125	°C
TJ	Junction temperature range	6 suffix version	–40	105	°C
		7 suffix version	–40	125	°C

Table 10. General operating conditions

1. When the ADC is used, refer to Table 59: ADC characteristics.

2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation.

3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.7: Thermal characteristics on page 133).

4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6.7: Thermal characteristics on page 133).

5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10.

Symbol	Parameter	Conditions	Min	Max	Unit
tVDD	VDD rise time rate	-	0	∞	μs/V
	VDD fall time rate	-	20	∞	μs/V

5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
		PLS[2:0]=000 (rising edge)	2.1	2.18	2.26
		PLS[2:0]=000 (falling edge)	2	2.08	2.16
		PLS[2:0]=001 (rising edge)	2.19	2.28	2.37
		PLS[2:0]=001 (falling edge)	2.09	2.18	2.27
		PLS[2:0]=010 (rising edge)	2.28	2.38	2.48
		PLS[2:0]=010 (falling edge)	2.18	2.28	2.38
		PLS[2:0]=011 (rising edge)	2.38	2.48	2.58
	Programmable voltage detector level selection	PLS[2:0]=011 (falling edge)	2.28	2.38	2.48	V
VPVD		PLS[2:0]=100 (rising edge)	2.47	2.58	2.69
		PLS[2:0]=100 (falling edge)	2.37	2.48	2.59
		PLS[2:0]=101 (rising edge)	2.57	2.68	2.79
		PLS[2:0]=101 (falling edge)	2.47	2.58	2.69
		PLS[2:0]=110 (rising edge)	2.66	2.78	2.9
		PLS[2:0]=110 (falling edge)	2.56	2.68	2.8
		PLS[2:0]=111 (rising edge)	2.76	2.88	3
		PLS[2:0]=111 (falling edge)	2.66	2.78	2.9
VPVDhyst(2)	PVD hysteresis	-	-	100	-	mV
VPOR/PDR	Power on/power down	Falling edge	1.8(1)	1.88	1.96
	reset threshold	Rising edge	1.84	1.92	2.0	V
VPDRhyst(2)	PDR hysteresis	-	-	40	-	mV
TRSTTEMPO(2)	Reset temporization	-	1	2.5	4.5	ms

1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.

2. Guaranteed by design.

5.3.4 Embedded reference voltage

The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VREFINT	Internal reference voltage	–40 °C < TA < +105 °C	1.16	1.20	1.26	V
		–40 °C < TA < +85 °C	1.16	1.20	1.24
TS_vrefint(1)	ADC sampling time when reading the internal reference voltage	-	-	5.1	17.1(2)	μs
VRERINT(2)	Internal reference voltage spread over the temperature range	VDD = 3 V ±10 mV	-	-	10	mV
TCoeff(2)	Temperature coefficient	-	-	-	100	ppm/°C

Table 13. Embedded internal reference voltage
-----------------------------------------------

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design.

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 13: Current consumption measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at VDD or VSS (no load)
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
• When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK

The parameters given in Table 14, Table 15 and Table 16 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

Symbol	Parameter	Conditions	fHCLK	Max(1)	Unit
				TA = 85 °C	mA
IDD	Supply current in Run mode	External clock(2), all peripherals enabled	72 MHz	69	mA
			48 MHz	50	mA
			36 MHz	39	mA
			24 MHz	27	mA
			16 MHz	20	mA
			8 MHz	11	mA
		External clock(2), all peripherals disabled	72 MHz	37	mA
			48 MHz	28	mA
			36 MHz	22	mA
			24 MHz	16.5	mA
			16 MHz	12.5	mA
			8 MHz	8	mA

1. Guaranteed by characterization results.

2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

Symbol	Parameter	Conditions	fHCLK	Max(1)		Unit
				TA = 85 °C	TA = 105 °C
IDD	Supply current in Run mode	External clock(2), all peripherals enabled	72 MHz	66	67	mA
			48 MHz	43.5	45.5
			36 MHz	33	35
			24 MHz	23	24.5
			16 MHz	16	18
			8 MHz	9	10.5
		External clock(2), all peripherals disabled	72 MHz	33	33.5
			48 MHz	23	23.5
			36 MHz	18	18.5
			24 MHz	13	13.5
			16 MHz	10	10.5
			8 MHz	6	6.5

CIAO Table 15. Maximum current consumption in Run mode, code with data processing running from RAM

1. Guaranteed by characterization results at VDD max, fHCLK max.

2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled

Symbol	Parameter	Conditions	fHCLK	Max(1)
				TA = 85 °C
IDD	Supply current in Run mode	code with data processing running from RAM, peripherals enabled	72 MHz	61
			48 MHz	43
			36 MHz	33
			24 MHz	24
			16 MHz	18

Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM

1. Guaranteed by characterization results at VDD max, fHCLK max with peripherals enabled.

2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

Symbol	Parameter	Conditions	Typ(1)			Max		Unit
			VDD/VBAT = 2.0 V	VDD/VBAT = 2.4 V	VDD/VBAT = 3.3 V	TA = 85 °C	TA = 105 °C
IDD	Supply current in Stop mode	Regulator in run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)	-	34.5	35	379	1130	µA

1. Typical values are measured at TA = 25 °C.

2. Guaranteed by characterization results.

Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values

Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values

Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values

Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values

Typical current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above).
• Ambient temperature and VDD supply voltage conditions summarized in Table 10.
• Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)

When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4

	Parameter	Conditions	fHCLK	Typ(1)
Symbol				All peripherals enabled(2)
		External clock(3)	72 MHz	51
			48 MHz	34.6
			36 MHz	26.6
			24 MHz	18.5
	Supply current in Run mode		16 MHz	12.8
			8 MHz	7.2
			4 MHz	4.2
			2 MHz	2.7
			1 MHz	2
			500 kHz	1.6
			125 kHz	1.3
IDD		Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency	64 MHz	45
			48 MHz	34
			36 MHz	26
			24 MHz	17.9
			16 MHz	12.2
			8 MHz	6.6
			4 MHz	3.6
			2 MHz	2.1
			1 MHz	1.4
			500 kHz	1
			125 kHz	0.7

Table 18. Typical current consumption in Run mode, code with data processing running from Flash

1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

Symbol	Parameter	Conditions	fHCLK	Typ(1) All peripherals enabled(2)	Typ(1) All peripherals disabled	Unit
IDD	Supply current in Run mode	External clock(3)	72 MHz	51	30.5	mA
			48 MHz	34.6	20.7
			36 MHz	26.6	16.2
			24 MHz	18.5	11.4
			16 MHz	12.8	8.2
			8 MHz	7.2	5
			4 MHz	4.2	3.1
			2 MHz	2.7	2.1
			1 MHz	2	1.7
			500 kHz	1.6	1.4
			125 kHz	1.3	1.2
		Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency	64 MHz	45	27	mA
			48 MHz	34	20.1
			36 MHz	26	15.6
			24 MHz	17.9	10.8
			16 MHz	12.2	7.6
			8 MHz	6.6	4.4
			4 MHz	3.6	2.5
			2 MHz	2.1	1.5
			1 MHz	1.4	1.1
			500 kHz	1	0.8
			125 kHz	0.7	0.6

1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed under the following conditions:

• all I/O pins are in input mode with a static value at VDD or VSS (no load)
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
  • with all peripherals clocked off
  • with only one peripheral clocked on
• ambient operating temperature and VDD supply voltage conditions summarized in Table 7

Peripheral	Current consumption	Unit
DMA1	20,42	μA/MHz
DMA2	19,03
FSMC	52,36
CRC	2,36
SDIO	33,33
BusMatrix(1)	9,72

Table 20. Peripheral current consumption

Table 20. Peripheral current consumption
Peripheral		Current consumption	Unit
---------------------	--------------	------------------------	--------
AHB (up to 72 MHz)	DMA1	20,42	μA/MHz
	DMA2	19,03
	FSMC	52,36
	CRC	2,36
	SDIO	33,33
	BusMatrix(1)	9,72

Peripheral		Current consumption	Unit
AHB (up to 72 MHz)	DMA1	20,42	μA/MHz
	DMA2	19,03
	FSMC	52,36
	CRC	2,36
	SDIO	33,33
	BusMatrix(1)	9,72

1. The BusMatrix is automatically active when at least one master is ON. (CPU, DMA1 or DMA2).

2. When the I2S is enabled, a current consumption equal to 0.02 mA must be added.

1. When DAC_OU1 or DAC_OUT2 is enabled, a current consumption equal to 0.36 mA must be added.

4. Specific conditions for measuring ADC current consumption: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4. When ADON bit in the ADCx_CR2 register is set to 1, a current consumption of analog part equal to 0.54 mA must be added for each ADC.

5.3.6 External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Table 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSE_ext	User external clock source frequency(1)		1	8	25	MHz
VHSEH	OSC_IN input pin high level voltage		0.7VDD	-	VDD	V
VHSEL	OSC_IN input pin low level voltage	-	VSS	-	0.3VDD
tw(HSE) tw(HSE)	OSC_IN high or low time(1)		5	-	-	ns
tr(HSE) tf(HSE)	OSC_IN rise or fall time(1)		-	-	20
Cin(HSE)	OSC_IN input capacitance(1)	-	-	5	-	pF
DuCy(HSE)	Duty cycle	-	45	-	55	%
IL	OSC_IN Input leakage current	VSS ≤VIN ≤VDD	-	-	±1	μA

Table 21. High-speed external user clock characteristics

1. Guaranteed by design.

Low-speed external user clock generated from an external source

The characteristics given in Table 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fLSE_ext	User External clock source frequency(1)		-	32.768	1000	kHz
VLSEH	OSC32_IN input pin high level voltage		0.7VDD	-	VDD
VLSEL	OSC32_IN input pin low level voltage	-	VSS	-	0.3VDD	V
tw(LSE)	OSC32_IN high or low time(1)		450	-	-	ns
tr(LSE) tf(LSE)	OSC32_IN rise or fall time(1)		-	-	50
Cin(LSE)	OSC32_IN input capacitance(1)	-	-	5	-	pF
DuCy(LSE)	Duty cycle	-	30	-	70	%
IL	OSC32_IN Input leakage current	VSS ≤VIN ≤VDD	-	-	±1	μA

1. Guaranteed by design.

Figure 20. High-speed external clock source AC timing diagram

DL

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fOSC_IN	Oscillator frequency	-	4	8	16	MHz
RF	Feedback resistor	-	-	200	-	kΩ
C	Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3)	RS = 30 Ω	-	30	-	pF
i2	HSE driving current	VDD= 3.3 V, VIN = VSS with 30 pF load	-	-	1	mA
gm	Oscillator transconductance	Startup	25	-	-	mA/V
tSU(HSE)(4)	Startup time	VDD is stabilized	-	2	-	ms

Table 23. HSE 4-16 MHz oscillator characteristics(1)(2)
---------------------------------------------------------

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by characterization results.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 22). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com.

1. REXT value depends on the crystal characteristics.

60/144 DocID14611 Rev 12

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
RF	Feedback resistor	-	-	5	-	MΩ
C(2)	Recommended load capacitance versus equivalent serial resistance of the crystal (RS)	RS = 30 kΩ	-	-	15	pF
I2	LSE driving current	VDD = 3.3 V, VIN = VSS	-	-	1.4	μA
gm	Oscillator transconductance	-	5	-	-	μA/V
tSU(LSE)(3

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
R$_F$	Feedback resistor	-	-	5	-	MΩ
C$^{(2)}$	Recommended load capacitance versus equivalent serial resistance of the crystal (R$_S$)	R$_S$ = 30 kΩ	-	-	15	pF
I$_2$	LSE driving current	V${DD}$ = 3.3 V, V${IN}$ = V$_{SS}$	-	-	1.4	µA
g$_m$	Oscillator transconductance	-	5	-	-

1. Guaranteed by characterization results.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers".

1. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer, PCB layout and humidity.

Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF.

Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 23). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF.

Figure 23. Typical application with a 32.768 kHz crystal

5.3.7 Internal clock source characteristics

The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

High-speed internal (HSI) RC oscillator

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI	Frequency	-	-	8	-	MHz
DuCy(HSI)	Duty cycle	-	45	-	55	%
ACCHSI	Accuracy of the HSI oscillator	User-trimmed with the RCC_CR register(2)	-	-	1(3)	%
		Factory calibrated(4)
		TA = –40 to 105 °C	–2

Table 25. HSI oscillator characteristics(1)

1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.

2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com.

3. Guaranteed by design.

4. Guaranteed by characterization results.

Low-speed internal (LSI) RC oscillator

		Table 26. LSI oscillator characteristics (1)
--	--	----------------------------------------------

Symbol	Parameter	Min	Typ	Max	Unit
fLSI(2)	Frequency	30	40	60	kHz
tsu(LSI)(3)	LSI oscillator startup time	-	-	85	μs
IDD(LSI)(3)	LSI oscillator power consumption	-	0.65	1.2	μA

1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.

2. Guaranteed by characterization results.

3. Guaranteed by design.

Wakeup time from low-power mode

The wakeup times given in Table 27 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator
• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

Symbol	Parameter	Typ	Unit
tWUSLEEP(1)	Wakeup from Sleep mode	1.8	μs
tWUSTOP(1)	Wakeup from Stop mode (regulator in run mode)	3.6	μs
	Wakeup from Stop mode (regulator in low-power mode)	5.4	μs
tWUSTDBY(1)	Wakeup from Standby mode	50	μs

Table 27. Low-power mode wakeup timings

1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction.

5.3.8 PLL characteristics

The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

Symbol	Parameter
	PLL input clock(2)
fPLL_IN	PLL input clock duty cycle
fPLL_OUT	PLL multiplier output clock
tLOCK	PLL lock time
Jitter	Cycle-to-cycle jitter

Symbol	Parameter	Min	Typ	Max$^{(1)}$	Unit
f$_{PLL_IN}$	PLL input clock$^{(2)}$	1	8.0	25	MHz
	PLL input clock duty cycle	40	-	60	%
f$_{PLL_OUT}$	PLL multiplier output clock	16	-	72	MHz
t$_{LOCK}$	PLL lock time	-	-	200	µs
Jitter	Cycle-to-cycle jitter	-	-	300	ps

1. Guaranteed by characterization results.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT.

5.3.9 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

Symbol	Parameter	Conditions	Min	Typ	Max(1)	Unit
tprog	16-bit programming time	TA = –40 to +105 °C	40	52.5	70	μs
tERASE	Page (2 KB) erase time	TA = –40 to +105 °C	20	-	40	ms
tME	Mass erase time	TA = –40 to +105 °C	20	-	40	ms
IDD	Supply current	Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V	-	-	28	mA
		Write mode fHCLK = 72 MHz, VDD = 3.3 V	-	-	7	mA
		Erase mode fHCLK = 72 MHz, VDD = 3.3 V	-	-	5	mA
		Power-down mode / Halt, VDD = 3.0 to 3.6 V	-	-	50	μA
Vprog	Programming voltage	-	2	-	3.6	V

Table 29. Flash memory characteristics

1. Guaranteed by design.

Symbol	Parameter	Conditions	Value	Unit
			Min(1)
NEND	Endurance	TA = –40 to +85 °C (6 suffix versions)	10	kcycles
		TA = –40 to +105 °C (7 suffix versions)
		1 kcycle(2) at TA = 85 °C	30
tRET	Data retention	1 kcycle(2) at TA = 105 °C	10	Years
		10 kcycles(2) at TA = 55 °C	20

1. Guaranteed by characterization results.

2. Cycling performed over the whole temperature range.

5.3.10 FSMC characteristics

Asynchronous waveforms and timings

Figure 24 through Figure 27 represent asynchronous waveforms and Table 31 through Table 34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration:

• AddressSetupTime = 0
• AddressHoldTime = 1
• DataSetupTime = 1

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Symbol	Parameter	Min	Max	Unit
tw(NE)	FSMC_NE low time	5tHCLK – 1.5	5tHCLK + 2	ns
tv(NOE_NE)	FSMC_NEx low to FSMC_NOE low	0.5	1.5	ns
tw(NOE)	FSMC_NOE low time	5tHCLK – 1.5	5tHCLK + 1.5	ns
th(NE_NOE)	FSMC_NOE high to FSMC_NE high hold time	–1.5	-	ns
tv(A_NE)	FSMC_NEx low to FSMC_A valid	-	0	ns
th(A_NOE)	Address hold time after FSMC_NOE high	0.1	-	ns
tv(BL_NE)	FSMC_NEx low to FSMC_BL valid	-	0	ns
th(BL_NOE)	FSMC_BL hold time after FSMC_NOE high	0	-	ns
tsu(Data_NE)	Data to FSMC_NEx high setup time	2tHCLK + 25	-	ns
tsu(Data_NOE)	Data to FSMC_NOEx high setup time	2tHCLK + 25	-	ns
th(Data_NOE)	Data hold time after FSMC_NOE high	0	-	ns
th(Data_NE)	Data hold time after FSMC_NEx high	0	-	ns
tv(NADV_NE)	FSMC_NEx low to FSMC_NADV low	-	5	ns
tw(NADV)	FSMC_NADV low time	-	tHCLK + 1.5	ns

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

1. CL = 15 pF.

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Symbol	Parameter	Min	Max	Unit
tw(NE)	FSMC_NE low time	3tHCLK – 1	3tHCLK + 2	ns
tv(NWE_NE)	FSMC_NEx low to FSMC_NWE low	tHCLK – 0.5	tHCLK + 1.5	ns
tw(NWE)	FSMC_NWE low time	tHCLK – 0.5	tHCLK + 1.5	ns
th(NE_NWE)	FSMC_NWE high to FSMC_NE high hold time	tHCLK	-	ns
tv(A_NE)	FSMC_NEx low to FSMC_A valid	-	7.5	ns
th(A_NWE)	Address hold time after FSMC_NWE high	tHCLK	-	ns
tv(BL_NE)	FSMC_NEx low to FSMC_BL valid	-	0	ns
th(BL_NWE)	FSMC_BL hold time after FSMC_NWE high	tHCLK – 0.5	-	ns
tv(Data_NE)	FSMC_NEx low to Data valid	-	tHCLK + 7	ns
th(Data_NWE)	Data hold time after FSMC_NWE high	tHCLK	-	ns
tv(NADV_NE)	FSMC_NEx low to FSMC_NADV low	-	5.5	ns
tw(NADV)	FSMC_NADV low time	-	tHCLK + 1.5	ns

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)

1. CL = 15 pF.

2. Guaranteed by characterization results.

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms

| | | Table 33. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) | |---|---|---|---|---| | Symbol | Parameter | Min | Max | Unit | | t_w(NE) | FSMC_NE low time | 7t_HCLK - 2 | 7t_HCLK + 2 | ns | | t_v(NOE_NE) | FSMC_NEx low to FSMC_NOE low | 3t_HCLK - 0.5 | 3t_HCLK + 1.5 | ns | | t_w(NOE) | FSMC_NOE low time | 4t_HCLK - 1 | 4t_HCLK + 2 | ns | | t_h(NE_NOE) | FSMC_NOE high to FSMC_NE high hold time | -1 | - | ns | | t_v(A_NE) | FSMC_NEx low to FSMC_A valid | - | 0 | ns | | t_v(NADV_NE) | FSMC_NEx low to FSMC_NADV low | 3 | 5 | ns | | t_w(NADV) | FSMC_NADV low time | t_HCLK - 1.5 | t_HCLK + 1.5 | ns | | t_h(AD_NADV) | FSMC_AD (address) valid hold time after FSMC_NADV high | t_HCLK | - | ns | | t_h(A_NOE) | Address hold time after FSMC_NOE high | t_HCLK - 2 | - | ns | | t_h(BL_NOE) | FSMC_BL hold time after FSMC_NOE high | 0 | - | ns | | t_v(BL_NE) | FSMC_NEx low to FSMC_BL valid | - | 0 | ns | | t_su(Data_NE) | Data to FSMC_NEx high setup time | 2t_HCLK + 24 | - | ns | | t_su(Data_NOE) | Data to FSMC_NOE high setup time | 2t_HCLK + 25 | - | ns |

Symbol	Parameter	Min	Max	Unit
tw(NE)	FSMC_NE low time	7tHCLK – 2	7tHCLK + 2	ns
tv(NOE_NE)	FSMC_NEx low to FSMC_NOE low	3tHCLK – 0.5	3tHCLK + 1.5	ns
tw(NOE)	FSMC_NOE low time	4tHCLK – 1	4tHCLK + 2	ns
th(NE_NOE)	FSMC_NOE high to FSMC_NE high hold time	–1	-	ns
tv(A_NE)	FSMC_NEx low to FSMC_A valid	-	0	ns
tv(NADV_NE)	FSMC_NEx low to FSMC_NADV low	3	5	ns
tw(NADV)	FSMC_NADV low time	tHCLK –1.5	tHCLK + 1.5	ns
th(AD_NADV)	FSMC_AD (address) valid hold time after FSMC_NADV high	tHCLK	-	ns
th(A_NOE)	Address hold time after FSMC_NOE high	tHCLK -2	-	ns
th(BL_NOE)	FSMC_BL hold time after FSMC_NOE high	0	-	ns
tv(BL_NE)	FSMC_NEx low to FSMC_BL valid	-	0	ns
tsu(Data_NE)	Data to FSMC_NEx high setup time	2tHCLK + 24	-	ns
tsu(Data_NOE)	Data to FSMC_NOE high setup time	2tHCLK + 25	-	ns

Symbol	Parameter	Min	Max	Unit
th(Data_NE)	Data hold time after FSMC_NEx high	0	-	ns
th(Data_NOE)	Data hold time after FSMC_NOE high	0	-	ns

Table 33. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued)

1. CL = 15 pF.

2. Guaranteed by characterization results.

Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms

Table 34. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FSMC_NE low time	5tHCLK – 1	5tHCLK + 2	ns
tv(NWE_NE)	FSMC_NEx low to FSMC_NWE low	2tHCLK	2tHCLK + 1	ns
tw(NWE)	FSMC_NWE low time	2tHCLK – 1	2tHCLK + 2	ns
th(NE_NWE)	FSMC_NWE high to FSMC_NE high hold time	tHCLK – 1	-	ns
tv(A_NE)	FSMC_NEx low to FSMC_A valid	-	7	ns
tv(NADV_NE)	FSMC_NEx low to FSMC_NADV low	3	5	ns
tw(NADV)	FSMC_NADV low time	tHCLK – 1	tHCLK + 1	ns

Symbol	Parameter	Min	Max	Unit
th(AD_NADV)	FSMC_AD (address) valid hold time after FSMC_NADV high	tHCLK – 3	-	ns
th(A_NWE)	Address hold time after FSMC_NWE high	4tHCLK	-	ns
tv(BL_NE)	FSMC_NEx low to FSMC_BL valid	-	1.6	ns
th(BL_NWE)	FSMC_BL hold time after FSMC_NWE high	tHCLK – 1.5	-	ns
tv(Data_NADV)	FSMC_NADV high to Data valid	-	tHCLK + 1.5	ns
th(Data_NWE)	Data hold time after FSMC_NWE high	tHCLK – 5	-	ns

Table 34. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

1. CL = 15 pF.

2. BGuaranteed by characterization results.

Synchronous waveforms and timings

Figure 28 through Figure 31 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration:

• BurstAccessMode = FSMC_BurstAccessMode_Enable;
• MemoryType = FSMC_MemoryType_CRAM;
• WriteBurst = FSMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

Figure 28. Synchronous multiplexed NOR/PSRAM read timings

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FSMC_CLK period	27.7	-	ns
td(CLKL-NExL)	FSMC_CLK low to FSMC_NEx low (x = 0...2)	-	1.5	ns
td(CLKL-NExH)	FSMC_CLK low to FSMC_NEx high (x = 0...2)	2	-	ns
td(CLKL-NADVL)	FSMC_CLK low to FSMC_NADV low	-	4	ns
td(CLKL-NADVH)	FSMC_CLK low to FSMC_NADV high	5	-	ns
td(CLKL-AV)	FSMC_CLK low to FSMC_Ax valid (x = 16...25)	-	0	ns
td(CLKL-AIV)	FSMC_CLK low to FSMC_Ax invalid (x = 16...25)	2	-	ns
td(CLKL-NOEL)	FSMC_CLK low to FSMC_NOE low	-	1	ns
td(CLKL-NOEH)	FSMC_CLK low to FSMC_NOE high	1.5	-	ns
td(CLKL-ADV)	FSMC_CLK low to FSMC_AD[15:0] valid	-	12	ns
td(CLKL-ADIV)	FSMC_CLK low to FSMC_AD[15:0] invalid	0	-	ns
tsu(ADV-CLKH)	FSMC_A/D[15:0] valid data before FSMC_CLK high	6	-	ns
th(CLKH-ADV)	FSMC_A/D[15:0] valid data after FSMC_CLK high	0	-	ns
tsu(NWAITV-CLKH)	FSMC_NWAIT valid before FSMC_CLK high	8	-	ns
th(CLKH-NWAITV)	FSMC_NWAIT valid after FSMC_CLK high	2	-	ns

1. CL = 15 pF.

2. Guaranteed by characterization results.

Figure 29. Synchronous multiplexed PSRAM write timings

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FSMC_CLK period	27.7	-	ns
td(CLKL-NExL)	FSMC_CLK low to FSMC_Nex low (x = 0...2)	-	2	ns
td(CLKL-NExH)	FSMC_CLK low to FSMC_NEx high (x = 0...2)	2	-	ns
td(CLKL-NADVL)	FSMC_CLK low to FSMC_NADV low	-	4	ns
td(CLKL-NADVH)	FSMC_CLK low to FSMC_NADV high	5	-	ns
td(CLKL-AV)	FSMC_CLK low to FSMC_Ax valid (x = 16...25)	-	0	ns
td(CLKL-AIV)	FSMC_CLK low to FSMC_Ax invalid (x = 16...25)	2	-	ns
td(CLKL-NWEL)	FSMC_CLK low to FSMC_NWE low	-	1	ns
td(CLKL-NWEH)	FSMC_CLK low to FSMC_NWE high	1	-	ns
td(CLKL-ADV)	FSMC_CLK low to FSMC_AD[15:0] valid	-	12	ns
td(CLKL-ADIV)	FSMC_CLK low to FSMC_AD[15:0] invalid	3	-	ns
td(CLKL-Data)	FSMC_A/D[15:0] valid after FSMC_CLK low	-	6	ns
td(CLKL-NBLH)	FSMC_CLK low to FSMC_NBL high	1	-	ns
tsu(NWAITV-CLKH)	FSMC_NWAIT valid before FSMC_CLK high	7	-	ns
th(CLKH-NWAITV)	FSMC_NWAIT valid after FSMC_CLK high	2	-	ns

Table 36. Synchronous multiplexed PSRAM write timings(1)(2)

1. CL = 15 pF.

2. Guaranteed by characterization results.

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings

	Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)
Symbol	Parameter
------------------	----------------------------------------------
tw(CLK)	FSMC_CLK period
td(CLKL-NExL)	FSMC_CLK low to FSMC_NEx low (x = 02)
td(CLKL-NExH)	FSMC_CLK low to FSMC_NEx high (x = 02)
td(CLKL-NADVL)	FSMC_CLK low to FSMC_NADV low
td(CLKL-NADVH)	FSMC_CLK low to FSMC_NADV high
td(CLKL-AV)	FSMC_CLK low to FSMC_Ax valid (x = 025)
td(CLKL-AIV)	FSMC_CLK low to FSMC_Ax invalid (x = 025)
td(CLKL-NOEL)	FSMC_CLK low to FSMC_NOE low
td(CLKL-NOEH)	FSMC_CLK low to FSMC_NOE high
tsu(DV-CLKH)	FSMC_D[15:0] valid data before FSMC_CLK high
th(CLKH-DV)	FSMC_D[15:0] valid data after FSMC_CLK high
tsu(NWAITV-CLKH)	FSMC_NWAIT valid before FSMC_SMCLK high
th(CLKH-NWAITV)	FSMC_NWAIT valid after FSMC_CLK high

1. CL = 15 pF.

1. Guaranteed by characterization results.

Figure 31. Synchronous non-multiplexed PSRAM write timings

Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2)

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FSMC_CLK period	27.7	-	ns
td(CLKL-NExL)	FSMC_CLK low to FSMC_NEx low (x = 0...2)	-	2	ns
td(CLKL-NExH)	FSMC_CLK low to FSMC_NEx high (x = 0...2)	2	-	ns
td(CLKL-NADVL)	FSMC_CLK low to FSMC_NADV low	-	4	ns
td(CLKL-NADVH)	FSMC_CLK low to FSMC_NADV high	5	-	ns
td(CLKL-AV)	FSMC_CLK low to FSMC_Ax valid (x = 16...25)	-	0	ns
td(CLKL-AIV)	FSMC_CLK low to FSMC_Ax invalid (x = 16...25)	2	-	ns
td(CLKL-NWEL)	FSMC_CLK low to FSMC_NWE low	-	1	ns
td(CLKL-NWEH)	FSMC_CLK low to FSMC_NWE high	1	-	ns
td(CLKL-Data)	FSMC_D[15:0] valid data after FSMC_CLK low	-	6	ns
td(CLKL-NBLH)	FSMC_CLK low to FSMC_NBL high	1	-	ns
tsu(NWAITV-CLKH)	FSMC_NWAIT valid before FSMC_CLK high	7	-	ns
th(CLKH-NWAITV)	FSMC_NWAIT valid after FSMC_CLK high	2	-	ns

1. CL = 15 pF.

1. Guaranteed by characterization results.

PC Card/CompactFlash controller waveforms and timings

Figure 32 through Figure 37 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x04;
• COM.FSMC_WaitSetupTime = 0x07;
• COM.FSMC_HoldSetupTime = 0x04;
• COM.FSMC_HiZSetupTime = 0x00;
• ATT.FSMC_SetupTime = 0x04;
• ATT.FSMC_WaitSetupTime = 0x07;
• ATT.FSMC_HoldSetupTime = 0x04;
• ATT.FSMC_HiZSetupTime = 0x00;
• IO.FSMC_SetupTime = 0x04;
• IO.FSMC_WaitSetupTime = 0x07;
• IO.FSMC_HoldSetupTime = 0x04;
• IO.FSMC_HiZSetupTime = 0x00;
• TCLRSetupTime = 0;
• TARSetupTime = 0;

Figure 32. PC Card/CompactFlash controller waveforms for common memory read access

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

Figure 33. PC Card/CompactFlash controller waveforms for common memory write access

Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access

1. Only data bits 0...7 are driven (bits 8...15 remains HiZ).

Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access

Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access

Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2)

Symbol	Parameter	Min	Max	Unit
tv(NCEx-A) tv(NCE4_1-A)	FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10)	-	0	ns
th(NCEx-AI) th(NCE4_1-AI)	FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10)	2.5	-	ns
td(NREG-NCEx) td(NREG-NCE4_1)	FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid	-	5	ns
th(NCEx-NREG) th(NCE4_1-NREG)	FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 high to FSMC_NREG invalid	tHCLK + 3	-	ns
td(NCE4_1-NOE)	FSMC_NCE4_1 low to FSMC_NOE low	-	5tHCLK + 2	ns
tw(NOE)	FSMC_NOE low width	8tHCLK -1.5	8tHCLK + 1	ns
td(NOE-NCE4_1)	FSMC_NOE high to FSMC_NCE4_1 high	5tHCLK + 2	-	ns
tsu(D-NOE)	FSMC_D[15:0] valid data before FSMC_NOE high	25	-	ns
th(NOE-D)	FSMC_D[15:0] valid data after FSMC_NOE high	15	-	ns
tw(NWE)	FSMC_NWE low width	8tHCLK - 1	8tHCLK + 2	ns
td(NWE-NCE4_1)	FSMC_NWE high to FSMC_NCE4_1 high	5tHCLK + 2	-	ns
td(NCE4_1-NWE)	FSMC_NCE4_1 low to FSMC_NWE low	-	5tHCLK + 1.5	ns
tv(NWE-D)	FSMC_NWE low to FSMC_D[15:0] valid	-	0	ns
th(NWE-D)	FSMC_NWE high to FSMC_D[15:0] invalid	11tH

Symbol	Parameter	Min	Max	Unit
tw(NIOWR)	FSMC_NIOWR low width	8tHCLK + 3	-	ns
tv(NIOWR-D)	FSMC_NIOWR low to FSMC_D[15:0] valid	-	5tHCLK +1	ns
th(NIOWR-D)	FSMC_NIOWR high to FSMC_D[15:0] invalid	11tHCLK	-	ns
td(NCE4_1-NIOWR)	FSMC_NCE4_1 low to FSMC_NIOWR valid	-	5tHCLK+3ns	ns
th(NCEx-NIOWR) th(NCE4_1-NIOWR)	FSMC_NCEx high to FSMC_NIOWR invalid FSMC_NCE4_1 high to FSMC_NIOWR invalid	5tHCLK – 5	-	ns
td(NIORD-NCEx) td(NIORD-NCE4_1)	FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1 low to FSMC_NIORD valid	-	5tHCLK + 2.5	ns
th(NCEx-NIORD) th(NCE4_1-NIORD)	FSMC_NCEx high to FSMC_NIORD invalid FSMC_NCE4_1 high to FSMC_NIORD invalid	5tHCLK – 5	-	ns
tsu(D-NIORD)	FSMC_D[15:0] valid before FSMC_NIORD high	4.5	-	ns
td(NIORD-D)	FSMC_D[15:0] valid after FSMC_NIORD high	9	-	ns
tw(NIORD)	FSMC_NIORD low width	8tHCLK + 2	-	ns

Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued)

1. CL = 15 pF.

2. Guaranteed by characterization results.

NAND controller waveforms and timings

Figure 38 through Figure 41 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x01;
• COM.FSMC_WaitSetupTime = 0x03;
• COM.FSMC_HoldSetupTime = 0x02;
• COM.FSMC_HiZSetupTime = 0x01;
• ATT.FSMC_SetupTime = 0x01;
• ATT.FSMC_WaitSetupTime = 0x03;
• ATT.FSMC_HoldSetupTime = 0x02;
• ATT.FSMC_HiZSetupTime = 0x01;
• Bank = FSMC_Bank_NAND;
• MemoryDataWidth = FSMC_MemoryDataWidth_16b;
• ECC = FSMC_ECC_Enable;
• ECCPageSize = FSMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0;

Figure 38. NAND controller waveforms for read access

Figure 39. NAND controller waveforms for write access

Figure 40. NAND controller waveforms for common memory read access

Figure 41. NAND controller waveforms for common memory write access

Symbol	Parameter	Min	Max	Unit
td(D-NWE)(2)	FSMC_D[15:0] valid before FSMC_NWE high	5tHCLK + 12	-	ns
tw(NOE)(2)	FSMC_NOE low width	4tHCLK-1.5	4tHCLK+1.5	ns
tsu(D-NOE)(2)	FSMC_D[15:0] valid data before FSMC_NOE high	25	-	ns
th(NOE-D)(2)	FSMC_D[15:0] valid data after FSMC_NOE high	7	-	-
tw(NWE)(2)	FSMC_NWE low width	4tHCLK-1	4tHCLK+1	ns
tv(NWE-D)(2)	FSMC_NWE low to FSMC_D[15:0] valid	-	0	ns
th(NWE-D)(2)	FSMC_NWE high to FSMC_D[15:0

Symbol	Parameter	Min	Max	Unit
td(D-NWE)(2)	FSMC_D[15:0] valid before FSMC_NWE high	5tHCLK + 12	-	ns
tsu(D-NOE)(2)	FSMC_D[15:0] valid data before FSMC_NOE high	25	-	ns
th(NOE-D)(2)	FSMC_D[15:0] valid data after FSMC_NOE high	7	-	-

1. CL = 15 pF.

2. Guaranteed by characterization results.

3. Guaranteed by design.

5.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709.

Symbol	Parameter	Conditions	Level/ Class
VFESD	Voltage limits to be applied on any I/O pin to induce a functional disturbance	VDD = 3.3 V, LQFP144, TA = +25 °C, fHCLK = 72 MHz conforms to IEC 61000-4-2	2B
VEFTB	Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance	VDD = 3.3 V, LQFP144, TA = +25 °C, fHCLK = 72 MHz conforms to IEC 61000-4-4	4A

Table 41. EMS characteristics

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol	Parameter	Conditions	Monitored frequency band	Max vs. [fHSE/fHCLK] 8/48 MHz	Max vs. [fHSE/fHCLK] 8/72 MHz	Unit
SEMI	Peak level	VDD = 3.3 V, TA = 25 °C, LQFP144 package compliant with IEC 61967-2	0.1 to 30 MHz	8	12	dBµV
			30 to 130 MHz	31	21	dBµV
			130 MHz to 1GHz	28	33	dBµV
			SAE EMI Level	4	4	-

Table 42. EMI characteristics
-------------------------------

5.3.12 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 43. ESD absolute maximum ratings
----------------------------------------

Symbol	Ratings	Conditions	Class	Maximum value(1)	Unit
VESD(HBM)	Electrostatic discharge voltage (human body model)	TA = +25 °C, conforming to JESD22-A114	2	2000	V
VESD(CDM)	Electrostatic discharge voltage (charge device model)	TA = +25 °C, conforming to JESD22-C101	III	500

1. Guaranteed by characterization results.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol	Parameter	Conditions	Class
LU	Static latch-up class	TA = +105 °C conforming to JESD78A	II level A

Table 44. Electrical sensitivities

5.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in Table 45

Symbol	Description	Functional susceptibility		Unit
		Negative injection	Positive injection
	Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13	-0	+0
IINJ	Injected current on all FT pins	-5	+0	mA
	Injected current on any other pin	-5	+5

Table 45. I/O current injection susceptibility

5.3.14 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	Standard IO input low level voltage		–0.3	-	0.28*(VDD-2 V)+0.8 V	V
VIL	IO FT(1) input low level voltage	-	–0.3	-	0.32*(VDD-2 V)+0.75 V	V
	Standard IO input high level voltage	-	0.41*(VDD-

Table 46. I/O static characteristics
--------------------------------------

1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled.

2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.

1. With a minimum of 100 mV.

2. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 42 and Figure 43 for standard I/Os, and in Figure 44 and Figure 45 for 5 V tolerant I/Os.

Figure 42. Standard I/O input characteristics - CMOS port

Figure 44. 5 V tolerant I/O input characteristics - CMOS port

Figure 45. 5 V tolerant I/O input characteristics - TTL port

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8).

Output voltage levels

Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant.

Symbol	Parameter	Conditions	Min	Max	Unit
VOL(1)	Output low level voltage for an I/O pin when 8 pins are sunk at same time	TTL port(3) IIO = +8 mA	-	0.4	V
VOH(2)	Output high level voltage for an I/O pin when 8 pins are sourced at same time	2.7 V < VDD < 3.6 V	VDD–0.4	-
VOL(1)	Output low level voltage for an I/O pin when 8 pins are sunk at same time	CMOS port(3) IIO = +8 mA	-	0.4
VOH(2)	Output high level voltage for an I/O pin when 8 pins are sourced at same time	2.7 V < VDD < 3.6 V	2.4	-	V

	Table 47. Output voltage characteristics

Symbol	Parameter	Conditions	Min	Max	Unit
VOL(1)	Output low level voltage for an I/O pin when 8 pins are sunk at same time	TTL port(3) IIO = +8 mA	-	0.4	V
VOH(2)	Output high level voltage for an I/O pin when 8 pins are sourced at same time	2.7 V < VDD < 3.6 V	VDD–0.4	-
VOL(1)	Output low level voltage for an I/O pin when 8 pins are sunk at same time	CMOS port(3) IIO = +8 mA	-	0.4	V
VOH(2)	Output high level voltage for an I/O pin when 8 pins are sourced at same time	2.7 V < VDD < 3.6 V	2.4	-

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.

3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

4. Guaranteed by characterization results.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 46 and Table 48, respectively.

Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

MODEx[1:0] bit value(1)	Symbol	Parameter	Conditions	Min	Max	Unit
10	fmax(IO)out	Maximum frequency(2)	CL = 50 pF, VDD = 2 V to 3.6 V	-	2	MHz
	tf(IO)out	Output high to low level fall time	CL = 50 pF, VDD = 2 V to 3.6 V	-	125(3)	ns
	tr(IO)out	Output low to
Table 48. I/O AC characteristics(1)

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 46.

3. Guaranteed by design.

5.3.15 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46).

Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VIL(NRST)(1)	NRST Input low level voltage	-	–0.5	-	0.8	V
VIH(NRST)(1)	NRST Input high level voltage	-	2	-	VDD+0.5	V
Vhys(NRST)	NRST Schmitt trigger voltage hysteresis	-	-	200	-	mV
RPU	Weak pull-up equivalent resistor(2)	VIN = VSS	30	40	50	kΩ
VF(NRST)(1)	NRST Input filtered pulse	-	-	-	100	ns
VNF(NRST)(1)	NRST Input not filtered pulse	-	300	-	-	ns

Table 49. NRST pin characteristics

1. Guaranteed by design.

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).

Figure 47. Recommended NRST pin protection

• 1. The reset network protects the device against parasitic resets.
• 1. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset will not be taken into account by the device.

5.3.16 TIM timer characteristics

The parameters given in Table 50 are guaranteed by design.

Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol	Parameter	Conditions	Min	Max	Unit
t$_{res(TIM)}$	Timer resolution time	-	1	-	t$_{TIMxCLK}$
		f$_{TIMxCLK}$ = 72 MHz	13.9	-	ns
f$_{EXT}$	Timer external clock frequency on CH1 to CH4	-	0	f$_{TIMxCLK}$/2	MHz
		f$_{TIMxCLK}$ = 72 MHz	0	36	MHz
Res$_{TIM}$	Timer resolution	-	-	16	bit
t$_{COUNTER}$	16-bit counter clock period when internal clock is selected	-	1	65536	t$_{TIMxCLK}$
		f$_{TIMxCLK}$ = 72 MHz	0.0139	910	μs
t$_{MAX_COUNT}$	Maximum possible count	-	-	65536 × 65536	t$_{TIMxCLK}$
		f$_{TIMxCLK}$ = 72 MHz	-	59.6	s

Table 50. TIMx(1) characteristics

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

5.3.17 Communications interfaces

I 2 C interface characteristics

The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I 2 C interface meets the requirements of the standard I² C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present.

The I² C characteristics are described in Table 51. Refer also to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).

Symbol	Parameter	Standard mode 2C(1)(2) I		Fast mode I2C(1)(2)		Unit
		Min	Max	Min	Max
tw(SCLL)	SCL clock low time	4.7	-	1.3	-	μs
tw(SCLH)	SCL clock high time	4.0	-	0.6	-
tsu(SDA)	SDA setup time	250	-	100	-
th(SDA)	SDA data hold time	-	3450(3)	-	900(3)
tr(SDA) tr(SCL)	SDA and SCL rise time	-	1000	-	300	ns
tf(SDA) tf(SCL)	SDA and SCL fall time	-	300	-	300
th(STA)	Start condition hold time	4.0	-	0.6	-
tsu(STA)	Repeated Start condition setup time	4.7	-	0.6	-	μs
tsu(STO)	Stop condition setup time	4.0	-	0.6	-	μs
tw(STO:STA)	Stop to Start condition time (bus free)	4.7	-	1.3	-	μs
Cb	Capacitive load for each bus line	-	400	-	400	pF
tSP	Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode	0	50(4)	0	50(4)	μs

1. Guaranteed by design.

2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz.

3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region on the falling edge of SCL.

4. The minimum width of the spikes filtered by the analog filter is above tSP(max).

Figure 48. I2C bus AC waveforms and measurement circuit

• 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
• 1. Rs: Series protection resistors.
• 1. Rp: Pull-up resistors.

1. VDD_I2C : I2C bus supply

	I2C_CCR value
fSCL (kHz)	RP = 4.7 kΩ
400	0x801E
300	0x8028
200	0x803C
100	0x00B4
50	0x0168
20	0x0384

Table 52. SCL frequency (fPCLK1= 36 MHz.,VDD_I2C = 3.3 V)(1)(2)

1. RP = External pull-up resistance, fSCL = I2C speed.

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application.

I 2S - SPI characteristics

Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10.

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).

Symbol	Parameter	Conditions	Min	Max	Unit
fSCK	SPI clock frequency	Master mode	-	18	MHz
1/tc(SCK)		Slave mode	-	18
tr(SCK) tf(SCK)	SPI clock rise and fall time	Capacitive load: C = 30 pF	-	8	ns
DuCy(SCK)	SPI slave input clock duty cycle	Slave mode	30	70	%
tsu(NSS)(1)	NSS setup time	Slave mode	4tPCLK	-
th(NSS)(1)	NSS hold time	Slave mode	2tPCLK	-
tw(SCKH)(1) tw(SCKL)(1)	SCK high and low time	Master mode, fPCLK = 36 MHz, presc = 4	50	60
tsu(MI) (1)	Data input setup time	Master mode	5	-
tsu(SI)(1)		Slave mode	5	-
th(MI) (1)		Master mode	5	-
th(SI)(1)	Data input hold time	Slave mode	4	-	ns
ta(SO)(1)(2)	Data output access time Slave mode, fPCLK = 20 MHz Data output disable time Slave mode		0	3tPCLK
tdis(SO)(1)(3)			2	10
tv(SO) (1)	Data output valid time	Slave mode (after enable edge)		25
tv(MO)(1)	Data output valid time Master mode (after enable edge)		-	5
th(SO)(1)		Slave mode (after enable edge)	15	-
th(MO)(1)	Data output hold time	Master mode (after enable edge)	2	-

			Table 53. SPI characteristics
--	--	--	-------------------------------

1. Guaranteed by characterization results.

1. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

2. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

Figure 51. SPI timing diagram - master mode(1)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

Symbol	Parameter	Conditions		Min	Max	Unit
DuCy(SCK)	I2S slave input clock duty cycle	Slave mode		30	70	%
fCK	2S clock frequency I	Master mode (data: 16 bits, Audio frequency = 48 kHz)		1.522	1.525	MHz
1/tc(CK)		Slave mode		0	6.5
tr(CK) tf(CK)	2S clock rise and fall time I	Capacitive load CL	= 50 pF	-	8
tv(WS) (1)	WS valid time	Master mode	I2S2	3 2	- -
th(WS) (1)	WS hold time	Master mode	I2S3	0	-
tsu(WS) (1)	WS setup time	Slave mode		4	-
th(WS) (1)	WS hold time	Slave mode		0	-
tw(CKH) (1)		Master fPCLK= 16 MHz, audio		312.5	-
tw(CKL) (1)	CK high and low time	frequency = 48 kHz		345	-	ns
	Data input setup time	Master receiver	I2S2	2	-
tsu(SD_MR) (1)			I2S3	6.5	-
tsu(SD_SR) (1)	Data input setup time	Slave receiver		1.5	-
th(SD_MR)(1)(2)		Master receiver		0	-
th(SD_SR) (1)(2)	Data input hold time Slave receiver			0.5	-
tv(SD_ST) (1)(2)	Data output valid time	Slave transmitter (after enable edge)		-	18
th(SD_ST) (1)	Data output hold time	Slave transmitter (after enable edge)		11	-
tv(SD_MT) (1)(2)	Data output valid time	Master transmitter (after enable edge)	-	3
th(SD_MT) (1)	Data output hold time	Master transmitter (after enable edge)	0	-

Table 54. I2S characteristics

1. Guaranteed by design and/or characterization results.

2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.

Figure 52. I2S slave timing diagram (Philips protocol)(1)

• 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
• 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 53. I2S master timing diagram (Philips protocol)(1)

• 1. Guaranteed by characterization results.
• 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10.

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK).

Figure 54. SDIO high-speed mode

Figure 55. SD default mode

Table 55. SD / MMC characteristics

Symbol	Parameter	Conditions	Min	Max	Unit
fPP	Clock frequency in data transfer mode	CL ≤ 30 pF	0	48	MHz
tW(CKL)	Clock low time, fPP = 16 MHz	CL ≤ 30 pF	32	-
tW(CKH)	Clock high time, fPP = 16 MHz	CL ≤ 30 pF	30	-	ns
tr	Clock rise time	CL ≤ 30 pF	-	4
tf	Clock fall time	CL ≤ 30 pF	-	5

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Symbol	Parameter	Conditions	Min	Max	Unit
	CMD, D inputs (referenced to CK)
tISU	Input setup time	CL ≤ 30 pF	2	-	ns
tIH	Input hold time	CL ≤ 30 pF	0	-
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV	Output valid time	CL ≤ 30 pF	-	6	ns
tOH	Output hold time	CL ≤ 30 pF	0	-
CMD, D outputs (referenced to CK) in SD default mode(1)
tOVD	Output valid default time	CL ≤ 30 pF	-	7	ns
tOHD	Output hold default time	CL ≤ 30 pF	0.5	-

Table 55. SD / MMC characteristics

1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.

USB characteristics

The USB interface is USB-IF certified (Full Speed).

Table 56. USB startup time

Symbol	Parameter	Max	Unit
tSTARTUP(1) USB transceiver startup time		1	μs

1. Guaranteed by design.

Symbol	Parameter	Conditions	Min.(1)	Max.(1)	Unit
	Input levels
VDD	USB operating voltage(2)	-	3.0(3)	3.6	V
VDI(4)	Differential input sensitivity	I(USB_DP, USB_DM)	0.2	-
(4) VCM	Differential common mode range	Includes VDI range	0.8	2.5	V
VSE(4)	Single ended receiver threshold	-	1.3	2.0
Output levels
VOL	Static output level low	RL of 1.5 kΩ to 3.6 V(5)	-	0.3	V
VOH	Static output level high	RL of 15 kΩ to VSS(5)	2.8	3.6

1. All the voltages are measured from the local ground potential.

1. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.

2. The STM32F103xC/D/E USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.

4. Guaranteed by characterization results.

5. RL is the load connected on the USB drivers

Figure 56. USB timings: definition of data signal rise and fall time

• Symbol
• tr
• tf
• trfm
• VCRS

Table 58. USB: full-speed electrical characteristics

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0).

5.3.18 CAN (controller area network) interface

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).

5.3.19 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 59 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10.

Note: It is recommended to perform a calibration after each power-up.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VDDA	Power supply	-	2.4	-	3.6	V
VREF+	Positive reference voltage	-	2.4	-	VDDA	V
VREF-	Negative reference voltage	-	0		V
IVREF	Current on the VREF input pin	-	-	160(1)	220	μA
fADC	ADC clock frequency	-	0.6	-	14	MHz
(2) fS	Sampling rate	-	0.05	-	1	MHz
		fADC = 14 MHz	-	-	823	kHz
fTRIG(2)	External trigger frequency	-	-	-	17	1/fADC
VAIN	Conversion voltage range(3)	-	0 (VSSA or VREF tied to ground)	-	VREF+	V
RAIN(2)	External input impedance	See Equation 1 and Table 60 for details	-	-	50	κΩ
RADC(2)	Sampling switch resistance	-	-	-	1	κΩ
CADC(2)	Internal sample and hold capacitor	-	-	-	8	pF
tCAL(2)	Calibration time	fADC = 14 MHz -	5.9 83		μs 1/fADC
tlat(2)	Injection trigger conversion	fADC = 14 MHz	-	-	0.214	μs
	latency	-	-	-	3(4)	1/fADC
Regular trigger conversion tlatr(2)		fADC = 14 MHz	-	-	0.143	μs
	latency	-	-	-	2(4)	1/fADC
(2)	Sampling time	fADC = 14 MHz	0.107	-	17.1	μs
tS		-	1.5	-	239.5	1/fADC
tSTAB(2)	Power-up time	-	0	0	1	μs
	Total conversion time	fADC = 14 MHz	1	-	18	μs
tCONV(2)	(including sampling time)	-	14 to 252 (tS for sampling +12.5 for successive approximation)			1/fADC

Table 59. ADC characteristics

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• 1. Guaranteed by characterization results.
• 2. Guaranteed by design.

• 1. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details.
• 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 59.

Equation 1: RAIN max formula

$mathsf{R}_mathsf{AIN} < frac{mathsf{T}_mathsf{S}}{mathsf{f}_mathsf{ADC} × mathsf{C}_mathsf{ADC} × ln(mathsf{2}^mathsf{N+2})} - mathsf{R}_mathsf{ADC}.$

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

• Ts (cycles) tS (μs) RAIN max (kΩ)
• 1.5 0.11 0.4
• 7.5 0.54 5.9
• 13.5 0.96 11.4
• 28.5 2.04 25.2
• 41.5 2.96 37.2
• 55.5 3.96 50
• 71.5 5.11 NA
• 239.5 17.1 NA

Table 60. RAIN max for fADC = 14 MHz(1)

Symbol	Parameter	Test conditions	Typ	Max(3)	Unit
ET	Total unadjusted error	fPCLK2 = 56 MHz,	±1.3	±2
EO	Offset error	fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3 V to 3.6 V	±1	±1.5
EG	Gain error	TA = 25 °C	±0.5	±1.5	LSB
ED	Differential linearity error	Measurements made after	±0.7	±1
EL	Integral linearity error	ADC calibration VREF+ = VDDA	±0.8	±1.5

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not affect the ADC accuracy.

1. Guaranteed by characterization results.

^2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Symbol	Parameter	Test conditions	Typ	Max(4)	Unit
ET	Total unadjusted error		±2	±5
EO	Offset error	fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ,	±1.5	±2.5
EG	Gain error	VDDA = 2.4 V to 3.6 V	±1.5	±3	LSB
ED	Differential linearity error	Measurements made after ADC calibration	±1	±2
EL	Integral linearity error		±1.5	±3

1. ADC DC accuracy values are measured after internal calibration.

1. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.14 does not affect the ADC accuracy.

4. Guaranteed by characterization results.

• 1. Example of an actual transfer curve.
• 1. Ideal transfer curve.
• 1. End point correlation line.
• 1. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

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Figure 58. Typical connection diagram using the ADC

1. Refer to Table 59 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 59 or Figure 60, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

1. VREF+ and VREF– inputs are available only on 100-pin packages.

Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA)

1. VREF+ and VREF– inputs are available only on 100-pin packages.

5.3.20 DAC electrical specifications

Symbol	Parameter	Min	Typ	Max	Unit	Comments
VDDA	Analog supply voltage	2.4	-	3.6	V	-
VREF+	Reference supply voltage	2.4	-	3.6	V	VREF+ must always be below VDDA
VSSA	Ground	0	-	0	V	-
RLOAD(1)	Resistive load with buffer ON 5		-	-	kΩ	-
(2) RO	Impedance output with buffer OFF	-	-	15	kΩ	When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ
CLOAD(1)	Capacitive load	-	-	50	pF	Maximum capacitive load at DAC_OUT pin (when the buffer is ON).
DAC_OUT min(1)	Lower DAC_OUT voltage with buffer ON	0.2	-	-	V	It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code
DAC_OUT max(1)	Higher DAC_OUT voltage with buffer ON	-	-	VDDA – 0.2	V	(0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V
DAC_OUT min(1)	Lower DAC_OUT voltage with buffer OFF	-	0.5	-	mV	It gives the maximum output
DAC_OUT max(1)	Higher DAC_OUT voltage with buffer OFF	-	-	VREF+ – 1LSB V		excursion of the DAC.
IDDVREF+	DAC DC current consumption in quiescent mode (Standby mode)	-	-	220	μA	With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs
	DAC DC current	-	-	380	μA	With no load, middle code (0x800) on the inputs
IDDA	consumption in quiescent mode(3)	-	-	480	μA	With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs
DNL(4)	Differential non linearity Difference between two consecutive code-1LSB)	-	-	±0.5	LSB	Given for the DAC in 10-bit configuration
		-	-	±2	LSB	Given for the DAC in 12-bit configuration
INL(3)	Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)	-	-	±1	LSB	Given for the DAC in 10-bit configuration
		-	-	±4	LSB	Given for the DAC in 12-bit configuration

Table 63. DAC characteristics

Symbol	Parameter	Min	Typ	Max	Unit	Comments
Offset(3)	Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2)	-	-	±10	mV	-
		-	-	±3	LSB	Given for the DAC in 10-bit at VREF+ = 3.6 V
		-	-	±12	LSB	Given for the DAC in 12-bit at VREF+ = 3.6 V
Gain error(3)	Gain error	-	-	±0.5	%	Given for the DAC in 12bit configuration
tSETTLING(3)	Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB	-	3	4	μs	CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Update rate(3)	Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)	-	-	1		MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
tWAKEUP(3)	Wakeup time from off state (Setting the ENx bit in the DAC Control register)	-	6.5	10	μs	CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones.
PSRR+ (1)	Power supply rejection ratio (to VDDA) (static DC measurement	-	–67	–40	dB	No RLOAD, CLOAD = 50 pF

Table 63. DAC characteristics (continued)

1. Guaranteed by design.

1. Guaranteed by characterization.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.

1. Guaranteed by characterization results.

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

5.3.21 Temperature sensor characteristics

Symbol	Parameter	Min	Typ	Max	Unit
TL	VSENSE linearity with temperature	-	±1	±2	°C
Avg_Slope	Average slope	4.0	4.3	4.6	mV/°C
V25	Voltage at 25 °C	1.34	1.43	1.52	V
tSTART(1)	Startup time	4	-	10	μs
TS_temp(2)(1)	ADC sampling time when reading the temperature	-	-	17.1	μs

1. Guaranteed by design.

1. Shortest sampling time can be determined in the application by multiple iterations.