STM32F103RE
ARM-based 32-bit MCUThe STM32F103RE is a arm-based 32-bit mcu from STMicroelectronics. View the full STM32F103RE datasheet below including pinout, electrical characteristics, absolute maximum ratings.
Manufacturer
STMicroelectronics
Category
Integrated CircuitsOverview
Part: STM32F103xC, STM32F103xD, STM32F103xE
Type: ARM Cortex-M3 MCU
Description: ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces, and up to 72 MHz maximum frequency.
Operating Conditions:
- Supply voltage: 2.0 to 3.6 V
- Operating temperature: -40 to +125 °C (Junction temperature)
- Max CPU frequency: 72 MHz
- ADC conversion range: 0 to 3.6 V
Absolute Maximum Ratings:
- Max supply voltage: 4.0 V
- Max continuous current: 200 mA (VDD)
- Max junction/storage temperature: -65 to +150 °C (Storage temperature)
Key Specs:
- CPU: ARM 32-bit Cortex-M3
- Max CPU frequency: 72 MHz
- Flash memory: 256 to 512 Kbytes
- SRAM: up to 64 Kbytes
- ADC resolution: 12-bit
- DAC resolution: 12-bit
- SPI speed: 18 Mbit/s
- DMIPS/MHz: 1.25 DMIPS/MHz (Dhrystone 2.1)
Features:
- Single-cycle multiplication and hardware division
- Flexible static memory controller (FSMC)
- LCD parallel interface (8080/6800 modes)
- Power-on reset (POR), Power-down reset (PDR), Programmable voltage detector (PVD)
- Low-power modes: Sleep, Stop, Standby
- 12-channel DMA controller
- Serial wire debug (SWD) & JTAG interfaces
- CRC calculation unit, 96-bit unique ID
- ECOPACK® packages
Package:
- LFBGA144 (144-ball)
- LFBGA100 (100-ball)
- WLCSP64 (64-ball)
- LQFP144 (144-pin)
- LQFP64 (64-pin)
Features
- Core: ARM ® 32-bit Cortex ® -M3 CPU
- -72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
- -Single-cycle multiplication and hardware division
- Memories
- -256 to 512 Kbytes of Flash memory
- -up to 64 Kbytes of SRAM
- -Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
- -LCD parallel interface, 8080/6800 modes
- Clock, reset and supply management
- -2.0 to 3.6 V application supply and I/Os
- -POR, PDR, and programmable voltage detector (PVD)
- -4-to-16 MHz crystal oscillator
- -Internal 8 MHz factory-trimmed RC
- -Internal 40 kHz RC with calibration
- -32 kHz oscillator for RTC with calibration
- Low power
- -Sleep, Stop and Standby modes
- -VBAT supply for RTC and backup registers
- 3 × 12-bit, 1 μs A/D converters (up to 21 channels)
- -Conversion range: 0 to 3.6 V
- -Triple-sample and hold capability
- -Temperature sensor
- 2 × 12-bit D/A converters
- DMA: 12-channel DMA controller
- -Supported peripherals: timers, ADCs, DAC, SDIO, I 2 Ss, SPIs, I 2 Cs and USARTs
- Debug mode
- -Serial wire debug (SWD) & JTAG interfaces
- -Cortex ® -M3 Embedded Trace Macrocell™
- Up to 112 fast I/O ports
- -51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
Pin Configuration
STM32F103RE – LQFP144 Pinout
| Pin | Name | Type | Main Function | Alternate Functions (Default) | Alternate Functions (Remap) |
|---|---|---|---|---|---|
| 1 | PE2 | I/O | FT PE2 | TRACECK/FSMC_A23 | |
| 2 | PE3 | I/O | FT PE3 | TRACED0/FSMC_A19 | |
| 3 | PE4 | I/O | FT PE4 | TRACED1/FSMC_A20 | |
| 4 | PE5 | I/O | FT PE5 | TRACED2/FSMC_A21 | |
| 5 | PE6 | I/O | FT PE6 | TRACED3/FSMC_A22 | |
| 6 | VBAT | S | VBAT | ||
| 7 | PC13-TAMPER-RTC | I/O | PC13 | TAMPER-RTC | |
| 8 | PC14-OSC32_IN | I/O | PC14 | OSC32_IN | |
| 9 | PC15-OSC32_OUT | I/O | PC15 | OSC32_OUT | |
| 10 | PF0 | I/O | FT PF0 | FSMC_A0 | |
| 11 | PF1 | I/O | FT PF1 | FSMC_A1 | |
| 12 | PF2 | I/O | FT PF2 | FSMC_A2 | |
| 13 | PF3 | I/O | FT PF3 | FSMC_A3 | |
| 14 | PF4 | I/O | FT PF4 | FSMC_A4 | |
| 15 | PF5 | I/O | FT PF5 | FSMC_A5 | |
| 16 | VSS_5 | S | VSS_5 | ||
| 17 | VDD_5 | S | VDD_5 | ||
| 18 | PF6 | I/O | PF6 | ADC3_IN4/FSMC_NIORD | |
| 19 | PF7 | I/O | PF7 | ADC3_IN5/FSMC_NREG | |
| 20 | PF8 | I/O | PF8 | ADC3_IN6/FSMC_NIOWR | |
| 21 | PF9 | I/O | PF9 | ADC3_IN7/FSMC_CD | |
| 22 | PF10 | I/O | PF10 | ADC3_IN8/FSMC_INTR | |
| 23 | OSC_IN | I | OSC_IN | ||
| 24 | OSC_OUT | O | OSC_OUT | ||
| 25 | NRST | I/O | NRST | ||
| 26 | PC0 | I/O | PC0 | ADC123_IN10 | |
| 27 | PC1 | I/O | PC1 | ADC123_IN11 | |
| 28 | PC2 | I/O | PC2 | ADC123_IN12 | |
| 29 | PC3 | I/O | PC3 | ADC123_IN13 | |
| 30 | VSSA | S | VSSA | ||
| 31 | VREF- | S | VREF- | ||
| 32 | VREF+ | S | VREF+ | ||
| 33 | VDDA | S | VDDA | ||
| 34 | PA0-WKUP | I/O | PA0 WKUP | USART2_CTS/ADC123_IN0/TIM2_CH1_ETR/TIM5_CH1/TIM8_ETR | |
| 35 | PA1 | I/O | PA1 | USART2_RTS/ADC123_IN1/TIM5_CH2/TIM2_CH2 | |
| 36 | PA2 | I/O | PA2 | USART2_TX/ADC123_IN2/TIM5_CH3/TIM2_CH3 | |
| 37 | PA3 | I/O | PA3 | USART2_RX/ADC123_IN3/TIM5_CH4/TIM2_CH4 | |
| 38 | VSS_4 | S | VSS_4 | ||
| 39 | VDD_4 | S | VDD_4 | ||
| 40 | PA4 | I/O | PA4 | SPI1_NSS/USART2_CK/DAC_OUT1/ADC12_IN4 | |
| 41 | PA5 | I/O | PA5 | SPI1_SCK/DAC_OUT2/ADC12_IN5 | |
| 42 | PA6 | I/O | PA6 | SPI1_MISO/TIM8_BKIN/ADC12_IN6/TIM3_CH1 | TIM1_BKIN |
| 43 | PA7 | I/O | PA7 | SPI1_MOSI/TIM8_CH1N/ADC12_IN7/TIM3_CH2 | TIM1_CH1N |
| 44 | PC4 | I/O | PC4 | ADC12_IN14 | |
| 45 | PC5 | I/O | PC5 | ADC12_IN15 | |
| 46 | PB0 | I/O | PB0 | ADC12_IN8/TIM3_CH3/TIM8_CH2N | TIM1_CH2N |
| 47 | PB1 | I/O | PB1 | ADC12_IN9/TIM3_CH4/TIM8_CH3N | TIM1_CH3N |
| 48 | PB2 | I/O | FT | PB2/BOOT1 | |
| 49 | PF11 | I/O | FT | PF11 FSMC_NIOS16 | |
| 50 | PF12 | I/O | FT | PF12 FSMC_A6 | |
| 51 | VSS_6 | S | VSS_6 | ||
| 52 | VDD_6 | S | VDD_6 | ||
| 53 | PF13 | I/O | FT | PF13 FSMC_A7 | |
| 54 | PF14 | I/O | FT | PF14 FSMC_A8 | |
| 55 | PF15 | I/O | FT | PF15 FSMC_A9 | |
| 56 | PG0 | I/O | FT | PG0 FSMC_A10 | |
| 57 | PG1 | I/O | FT | PG1 FSMC_A11 | |
| 58 | PE7 | I/O | FT | PE7 FSMC_D4 | TIM1_ETR |
| 59 | PE8 | I/O | FT | PE8 FSMC_D5 | TIM1_CH1N |
| 60 | PE9 | I/O | FT | PE9 FSMC_D6 | TIM1_CH1 |
| 61 | VSS_7 | S | VSS_7 | ||
| 62 | VDD_7 | S | VDD_7 | ||
| 63 | PE10 | I/O | FT | PE10 FSMC_D7 | TIM1_CH2N |
| 64 | PE11 | I/O | FT | PE11 FSMC_D8 | TIM1_CH2 |
| 65 | PE12 | I/O | FT | PE12 FSMC_D9 | TIM1_CH3N |
| 66 | PE13 | I/O | FT | PE13 FSMC_D10 | TIM1_CH3 |
| 67 | PE14 | I/O | FT | PE14 FSMC_D11 | TIM1_CH4 |
| 68 | PE15 | I/O | FT | PE15 FSMC_D12 | TIM1_BKIN |
| 69 | PB10 | I/O | FT | PB10 I2C2_SCL/USART3_TX | TIM2_CH3 |
| 70 | PB11 | I/O | FT | PB11 I2C2_SDA/USART3_RX | TIM2_CH4 |
| 71 | VSS_1 | S | VSS_1 | ||
| 72 | VDD_1 | S | VDD_1 | ||
| 73 | PB12 | I/O | FT | PB12 SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK/TIM1_BKIN | |
| 74 | PB13 | I/O | FT | PB13 SPI2_SCK/I2S2_CK/USART3_CTS/TIM1_CH1N | |
| 75 | PB14 | I/O | FT | PB14 SPI2_MISO/TIM1_CH2N/USART3_RTS | |
| 76 | PB15 | I/O | FT | PB15 SPI2_MOSI/I2S2_SD/TIM1_CH3N | |
| 77 | PD8 | I/O | FT | PD8 FSMC_D13 | USART3_TX |
| 78 | PD9 | I/O | FT | PD9 FSMC_D14 | USART3_RX |
| 79 | PD10 | I/O | FT | PD10 FSMC_D15 | USART3_CK |
| 80 | PD11 | I/O | FT | PD11 FSMC_A16 | USART3_CTS |
| 81 | PD12 | I/O | FT | PD12 FSMC_A17 | TIM4_CH1/USART3_RTS |
| 82 | PD13 | I/O | FT | PD13 FSMC_A18 | TIM4_CH2 |
| 83 | VSS_8 | S | VSS_8 | ||
| 84 | VDD_8 | S | VDD_8 | ||
| 85 | PD14 | I/O | FT | PD14 FSMC_D0 | TIM4_CH3 |
| 86 | PD15 | I/O | FT | PD15 FSMC_D1 | TIM4_CH4 |
| 87 | PG2 | I/O | FT | PG2 FSMC_A12 | |
| 88 | PG3 | I/O | FT | PG3 FSMC_A13 | |
| 89 | PG4 | I/O | FT | PG4 FSMC_A14 | |
| 90 | PG5 | I/O | FT | PG5 FSMC_A15 | |
| 91 | PG6 | I/O | FT | PG6 FSMC_INT2 | |
| 92 | PG7 | I/O | FT | PG7 FSMC_INT3 | |
| 93 | PG8 | I/O | FT | PG8 | |
| 94 | VSS_9 | S | VSS_9 | ||
| 95 | VDD_9 | S | VDD_9 | ||
| 96 | PC6 | I/O | FT | PC6 I2S2_MCK/TIM8_CH1/SDIO_D6 | TIM3_CH1 |
| 97 | PC7 | I/O | FT | PC7 I2S3_MCK/TIM8_CH2/SDIO_D7 | TIM3_CH2 |
| 98 | PC8 | I/O | FT | PC8 TIM8_CH3/SDIO_D0 | TIM3_CH3 |
| 99 | PC9 | I/O | FT | PC9 TIM8_CH4/SDIO_D1 | TIM3_CH4 |
| 100 | PA8 | I/O | FT | PA8 USART1_CK/TIM1_CH1/MCO | |
| 101 | PA9 | I/O | FT | PA9 USART1_TX/TIM1_CH2 | |
| 102 | PA10 | I/O | FT | PA10 USART1_RX/TIM1_CH3 | |
| 103 | PA11 | I/O | FT | PA11 USART1_CTS/USBDM/CAN_RX/TIM1_CH4 | |
| 104 | PA12 | I/O | FT | PA12 USART1_RTS/USBDP/CAN_TX/TIM1_ETR | |
| 105 | PA13 | I/O | FT | JTMS-SWDIO | PA13 |
| 106 | NC | — | Not connected | ||
| 107 | VSS_2 | S | VSS_2 | ||
| 108 | VDD_2 | S | VDD_2 | ||
| 109 | PA14 | I/O | FT | JTCK-SWCLK | PA14 |
| 110 | PA15 | I/O | FT | JTDI | SPI3_NSS/I2S3_WS/TIM2_CH1_ETR/PA15/SPI1_NSS |
| 111 | PC10 | I/O | FT | PC10 UART4_TX/SDIO_D2 | USART3_TX |
| 112 | PC11 | I/O | FT | PC11 UART4_RX/SDIO_D3 | USART3_RX |
| 113 | PC12 | I/O | FT | PC12 UART5_TX/SDIO_CK | USART3_CK |
| 114 | PD0 | I/O | FT | OSC_IN | FSMC_D2/CAN_RX |
| 115 | PD1 | I/O | FT | OSC_OUT | FSMC_D3/CAN_TX |
| 116 | PD2 | I/O | FT | PD2 TIM3_ETR/UART5_RX/SDIO_CMD | |
| 117 | PD3 | I/O | FT | PD3 FSMC_CLK | USART2_CTS |
| 118 | PD4 | I/O | FT | PD4 FSMC_NOE | USART2_RTS |
| 119 | PD5 | I/O | FT | PD5 FSMC_NWE | USART2_TX |
| 120 | VSS_10 | S | VSS_10 | ||
| 121 | VDD_10 | S | VDD_10 | ||
| 122 | PD6 | I/O | FT | PD6 FSMC_NWAIT | USART2_RX |
| 123 | PD7 | I/O | FT | PD7 FSMC_NE1/FSMC_NCE2 | USART2_CK |
| 124 | PG9 | I/O | FT | PG9 FSMC_NE2/FSMC_NCE3 | |
| 125 | PG10 | I/O | FT | PG10 FSMC_NCE4_1/FSMC_NE3 | |
| 126 | PG11 | I/O | FT | PG11 FSMC_NCE4_2 | |
| 127 | PG12 | I/O | FT | PG12 FSMC_NE4 | |
| 128 | PG13 | I/O | FT | PG13 FSMC_A24 | |
| 129 | PG14 | I/O | FT | PG14 FSMC_A25 | |
| 130 | VSS_11 | S | VSS_11 | ||
| 131 | VDD_11 | S | VDD_11 | ||
| 132 | PG15 | I/O | FT | PG15 | |
| 133 | PB3 | I/O | FT | JTDO | SPI3_SCK/I2S3_CK/PB3/TRACESWO/TIM2_CH2/SPI1_SCK |
| 134 | PB4 | I/O | FT | NJTRST | SPI3_MISO/PB4/TIM3_CH1/SPI1_MISO |
| 135 | PB5 | I/O | — | PB5 | I2C1_SMBA/SPI3_MOSI/I2S3_SD/TIM3_CH2/SPI1_MOSI |
| 136 | PB6 | I/O | FT | PB6 | I2C1_SCL/TIM4_CH1/USART1_TX |
| 137 | PB7 | I/O | FT | PB7 | I2C1_SDA/FSMC_NADV/TIM4_CH2/USART1_RX |
| 138 | BOOT0 | I | — | BOOT0 | |
| 139 | PB8 | I/O | FT | PB8 | TIM4_CH3/SDIO_D4/I2C1_SCL/CAN_RX |
| 140 | PB9 | I/O | FT | PB9 | TIM4_CH4/SDIO_D5/I2C1_SDA/CAN_TX |
| 141 | PE0 | I/O | FT | PE0 | TIM4_ETR/FSMC_NBL0 |
| 142 | PE1 | I/O | FT | PE1 | FSMC_NBL1 |
| 143 | VSS_3 | S | VSS_3 | ||
| 144 | VDD_3 | S | VDD_3 |
Notes
- FT designation: Pins marked "FT" are 5V-tolerant.
- PC13–PC15 limitations: These pins are supplied through a power switch with limited current (3 mA max). Output speed must not exceed 2 MHz with a maximum load of 30 pF, and these pins must not be used as current sources.
- PD0/PD1 dual function: In LQFP144 packages, PD0 and PD1 are available by default as GPIO; they are not configured as OSC_IN/OSC_OUT after reset (unlike LQFP64). Software remapping can reassign them to oscillator functions if needed.
- FSMC availability: Full FSMC support is available in LQFP144 packages (unlike LQFP64, which has no FSMC).
- Alternate function remapping: Many pins support software-remappable alternate functions. Refer to the STM32F10xxx reference manual for detailed remapping procedures.
Electrical Characteristics
The definition and values of input/output AC characteristics are given in Figure 46 and Table 48 , respectively.
Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 10 .
Table 48. I/O AC characteristics (1)
| MODEx[1:0] bit value (1) | Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|---|
| 10 | f max(IO)out | Maximum frequency (2) | C L = 50 pF, V DD = 2 V to 3.6 V | - | 2 | MHz |
| 10 | t f(IO)out | Output high to low level fall time | C L = 50 pF, V DD = 2 V to 3.6 V | - | 125 (3) | ns |
| 10 | t r(IO)out | Output low to high level rise time | C L = 50 pF, V DD = 2 V to 3.6 V | - | 125 (3) | ns |
| 01 | f max(IO)out | Maximum frequency (2) | C L = 50 pF, V DD = 2 V to 3.6 V | - | 10 | MHz |
| 01 | t f(IO)out | Output high to low level fall time | C L = 50 pF, V DD = 2 V to 3.6 V | - | 25 (3) | ns |
| 01 | t r(IO)out | Output low to high level rise time | C L = 50 pF, V DD = 2 V to 3.6 V | - | 25 (3) | ns |
| 11 | F max(IO)out | Maximum frequency (2) | C L = 30 pF, V DD = 2.7 V to 3.6 V | - | 50 | MHz |
| 11 | F max(IO)out | Maximum frequency (2) | C L = 50 pF, V DD = 2.7 V to 3.6 V | - | 30 | MHz |
| 11 | F max(IO)out | Maximum frequency (2) | C L = 50 pF, V DD = 2 V to 2.7 V | - | 20 | MHz |
| 11 | t f(IO)out | Output high to low level fall time | C L = 30 pF, V DD = 2.7 V to 3.6 V | - | 5 (3) | ns |
| 11 | t f(IO)out | Output high to low level fall time | C L = 50 pF, V DD = 2.7 V to 3.6 V | - | 8 (3) | ns |
| 11 | t f(IO)out | Output high to low level fall time | C L = 50 pF, V DD = 2 V to 2.7 V | - | 12 (3) | ns |
| 11 | t r(IO)out | Output low to high level rise time | C L = 30 pF, V DD = 2.7 V to 3.6 V | - | 5 (3) | ns |
| 11 | t r(IO)out | Output low to high level rise time | C L = 50 pF, V DD = 2.7 V to 3.6 V | - | 8 (3) | ns |
| 11 | t r(IO)out | Output low to high level rise time | C L = 50 pF, V DD = 2 V to 2.7 V | - | 12 (3) | ns |
| - | t EXTIpw | Pulse width of external signals detected by the EXTI controller | - | 10 | - | ns |
- The maximum frequency is defined in Figure 46 .
- Guaranteed by design.
Figure 46. I/O AC characteristics definition
Figure 46. I/O AC characteristics definition
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics , Table 8: Current characteristics , and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 7. Voltage characteristics
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DD -V SS | External main supply voltage (including V DDA and V DD ) (1) | -0.3 | 4.0 | V |
| V IN (2) | Input voltage on five volt tolerant pin | V SS - 0.3 | V DD + 4.0 | V |
| V IN (2) | Input voltage on any other pin | V SS - 0.3 | 4.0 | V |
| \ | ∆ V DDx \ | Variations between different V DD power pins | - | |
| \ | V SSX - V SS \ | Variations between all the different ground pins (3) | - | |
| V ESD(HBM) | Electrostatic discharge voltage (human body model) | see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) | see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) | - |
Table 8. Current characteristics
Table 8. Current characteristics
| Symbol | Ratings | Max. | Unit |
|---|---|---|---|
| I VDD | Total current into V DD /V DDA power lines (source) (1) | 150 | mA |
| I VSS | Total current out of V SS ground lines (sink) (1) | 150 | mA |
| I IO | Output current sunk by any I/O and control pin | 25 | mA |
| I IO | Output current source by any I/Os and control pin | - 25 | mA |
| I INJ(PIN) (2) | Injected current on five volt tolerant pins (3) | -5/+0 | mA |
| I INJ(PIN) (2) | Injected current on any other pin (4) | ± 5 | mA |
| Σ I INJ(PIN) | Total injected current (sum of all I/O and control pins) (5) | ± 25 | mA |
- Positive injection is not possible on these I/Os. A negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.
- A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.
- When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).
136
Table 9. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 150 | °C |
Thermal Information
The maximum chip junction temperature (T J max) must never exceed the values given in Table 10: General operating conditions on page 44 .
The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| STM32F103RC | STMicroelectronics | — |
| STM32F103RCT6 | STMicroelectronics | 64-LQFP |
| STM32F103RD | STMicroelectronics | — |
| STM32F103RX | STMicroelectronics | — |
| STM32F103VC | STMicroelectronics | — |
| STM32F103VD | STMicroelectronics | — |
| STM32F103VE | STMicroelectronics | — |
| STM32F103VX | STMicroelectronics | — |
| STM32F103X4 | STMicroelectronics | — |
| STM32F103X4/6 | STMicroelectronics | — |
| STM32F103X6 | STMicroelectronics | — |
| STM32F103X8 | STMicroelectronics | — |
| STM32F103X8/B | STMicroelectronics | — |
| STM32F103XB | STMicroelectronics | — |
| STM32F103XC | STMicroelectronics | — |
| STM32F103XC/D/E | STMicroelectronics | — |
| STM32F103XD | STMicroelectronics | LQFP64 10 × 10 mm |
| STM32F103XE | STMicroelectronics | — |
| STM32F103XESTM32F103XF | STMicroelectronics | — |
| STM32F103XF | STMicroelectronics | — |
| STM32F103XG | STMicroelectronics | — |
| STM32F103XGSTM32F103XF | STMicroelectronics | LQFP-28 |
| STM32F103XX | STMicroelectronics | — |
| STM32F103ZC | STMicroelectronics | — |
| STM32F103ZD | STMicroelectronics | — |
| STM32F103ZE | STMicroelectronics | — |
| STM32F103ZX | STMicroelectronics | LQFP64 1 |
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