STM32F103X8

Part: STM32F103x6, STM32F103x8, STM32F103xB

Type: ARM-based 32-bit MCU

Key Specs:

• Core Frequency: 72 MHz (max)
• Flash Memory: 32 to 128 Kbytes
• SRAM: 6 to 20 Kbytes
• Supply Voltage: 2.0 to 3.6 V
• ADC: 2 x 12-bit, 1 µs (16-channel)
• DMA: 7-channel
• I/O Ports: Up to 80
• Timers: Up to 7
• Communication Interfaces: Up to 9

Features:

• ARM 32-bit Cortex™-M3 CPU
• Single-cycle multiplication and hardware division
• POR, PDR, and programmable voltage detector (PVD)
• Sleep, Stop and Standby low power modes
• VBAT supply for RTC and backup registers
• Temperature sensor
• Dual-sample and hold capability for ADC
• DMA supports timers, ADC, SPIs, I2Cs and USARTs
• 5 V-tolerant I/Os (except analog inputs)
• Serial wire debug (SWD) & JTAG interfaces
• I2C (SMBus/PMBus), USART (ISO 7816, LIN, IrDA, modem control), SPI (18 Mbit/s), CAN (2.0B Active), USB 2.0 full speed interfaces
• ECOPACK® (RoHS compliant) packages

Applications:

• null

Package:

• ECOPACK® (RoHS compliant): dimensions not specified

• Core: ARM 32-bit Cortex™-M3 CPU
  • 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
  • Single-cycle multiplication and hardware division

■ Memories

• 32 to 128 Kbytes of Flash memory
• 6 to 20 Kbytes of SRAM
• Clock, reset and supply management
  • 2.0 to 3.6 V application supply and I/Os
  • POR, PDR, and programmable voltage detector (PVD)
  • 4-to-16 MHz crystal oscillator
  • Internal 8 MHz factory-trimmed RC
  • Internal 40 kHz RC
  • PLL for CPU clock
  • 32 kHz oscillator for RTC with calibration

■ Low power

• Sleep, Stop and Standby modes
• VBAT supply for RTC and backup registers
• 2 x 12-bit, 1 µs A/D converters (16-channel)
  • Conversion range: 0 to 3.6 V
  • Dual-sample and hold capability
  • Temperature sensor

■ DMA

• 7-channel DMA controller
• Peripherals supported: timers, ADC, SPIs, I 2Cs and USARTs

■ Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

■ Up to 7 timers

• Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter
• 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output, deadtime generation and emergency stop
• 2 watchdog timers (Independent and Window)
• SysTick timer: a 24-bit downcounter
• Up to 9 communication interfaces
  • Up to 2 x I2C interfaces (SMBus/PMBus)
  • Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
  • Up to 2 SPIs (18 Mbit/s)
  • CAN interface (2.0B Active)
  • USB 2.0 full speed interface
• Packages are ECOPACK® (RoHS compliant)

Table 1. Device summary

Reference	Root part number
STM32F103x6	STM32F103C6, STM32F103R6, STM32F103T6
STM32F103x8	STM32F103C8, STM32F103R8 STM32F103V8, STM32F103T8
STM32F103xB	STM32F103RB STM32F103VB, STM32F103CB

Contents STM32F103xx

Figure 2. STM32F103xx performance line BGA100 ballout

STM32F103xx Pin descriptions

Figure 3. STM32F103xx performance line LQFP100 pinout

23 24 25

PA0-WKUP PA1 PA2

PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

53 52 51 PB14 PB13 PB12

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Pin descriptions STM32F103xx

Figure 5. STM32F103xx performance line LQFP48 pinout

STM32F103xx Pin descriptions

Figure 6. STM32F103xx VFQFPN36 pinout

Pin descriptions STM32F103xx

Table 3. Pin definitions

| | | Pins | | | | | | | Alternate functions | |--------|--------|--------|---------|----------|-----------------------|---------|----------------|--------------------------------------|----------------------------------------------------------|-------| | BGA100 | LQFP48 | LQFP64 | LQFP100 | VFQFPN36 | Pin name | Type(1) | I / O Level(2) | Main
function(3)
(after reset) | Default | Remap | | A3 | - | - | 1 | - | PE2 | I/O | FT | PE2 | TRACECK | | B3 | - | - | 2 | - | PE3 | I/O | FT | PE3 | TRACED0 | | C3 | - | - | 3 | - | PE4 | I/O | FT | PE4 | TRACED1 | | D3 | - | - | 4 | - | PE5 | I/O | FT | PE5 | TRACED2 | | E3 | - | - | 5 | - | PE6 | I/O | FT | PE6 | TRACED3 | | B2 | 1 | 1 | 6 | - | VBAT | S | | VBAT | | A2 | 2 | 2 | 7 | - | PC13-TAMPER
RTC(4) | I/O | | PC13(5) | TAMPER-RTC | | A1 | 3 | 3 | 8 | - | PC14-OSC32_IN(4) | I/O | | PC14(5) | OSC32_IN | | B1 | 4 | 4 | 9 | - | PC15-
OSC32_OUT(4) | I/O | | PC15(5) | OSC32_OUT | | C2 | - | - | 10 | - | VSS_5 | S | | VSS_5 | | D2 | - | - | 11 | - | VDD_5 | S | | VDD_5 | | C1 | 5 | 5 | 12 | 2 | OSC_IN | I | | OSC_IN | | D1 | 6 | 6 | 13 | 3 | OSC_OUT | O | | OSC_OUT | | E1 | 7 | 7 | 14 | 4 | NRST | I/O | | NRST | | F1 | - | 8 | 15 | - | PC0 | I/O | | PC0 | ADC12_IN10 | | F2 | - | 9 | 16 | - | PC1 | I/O | | PC1 | ADC12_IN11 | | E2 | - | 10 | 17 | - | PC2 | I/O | | PC2 | ADC12_IN12 | | F3 | - | 11 | 18 | - | PC3 | I/O | | PC3 | ADC12_IN13 | | G1 | 8 | 12 | 19 | 5 | VSSA | S | | VSSA | | H1 | - | - | 20 | - | VREF- | S | | VREF | | J1 | - | - | 21 | - | VREF+ | S | | VREF+ | | K1 | 9 | 13 | 22 | 6 | VDDA | S | | VDDA | | G2 | 10 | 14 | 23 | 7 | PA0-WKUP | I/O | | PA0 | WKUP/USART2_
CTS(7)/
ADC12_IN0/
TIM2_CH1_ETR(7) | | H2 | 11 | 15 | 24 | 8 | PA1 | I/O | | PA1 | USART2_RTS(7)/
ADC12_IN1/
TIM2_CH2(7) | | J2 | 12 | 16 | 25 | 9 | PA2 | I/O | | PA2 | USART2_TX(7)/
ADC12_IN2/
TIM2_CH3(7) |

Table 3. Pin definitions (continued)

| | | Pins | | | | | | | Alternate functions | |--------|--------|--------|---------|----------|-------------|---------|----------------|--------------------------------------|--------------------------------------------|-----------| | BGA100 | LQFP48 | LQFP64 | LQFP100 | VFQFPN36 | Pin name | Type(1) | I / O Level(2) | Main
function(3)
(after reset) | Default | Remap | | K2 | 13 | 17 | 26 | 10 | PA3 | I/O | | PA3 | USART2_RX(7)/
ADC12_IN3/
TIM2_CH4(7) | | E4 | - | 18 | 27 | - | VSS_4 | S | | VSS_4 | | F4 | - | 19 | 28 | - | VDD_4 | S | | VDD_4 | | G3 | 14 | 20 | 29 | 11 | PA4 | I/O | | PA4 | SPI1_NSS(7)/
USART2_CK(7)/
ADC12_IN4 | | H3 | 15 | 21 | 30 | 12 | PA5 | I/O | | PA5 | SPI1_SCK(7)/
ADC12_IN5 | | J3 | 16 | 22 | 31 | 13 | PA6 | I/O | | PA6 | SPI1_MISO(7)/
ADC12_IN6/
TIM3_CH1(7) | TIM1_BKIN | | K3 | 17 | 23 | 32 | 14 | PA7 | I/O | | PA7 | SPI1_MOSI(7)/
ADC12_IN7/
TIM3_CH2(7) | TIM1_CH1N | | G4 | - | 24 | 33 | | PC4 | I/O | | PC4 | ADC12_IN14 | | H4 | - | 25 | 34 | | PC5 | I/O | | PC5 | ADC12_IN15 | | J4 | 18 | 26 | 35 | 15 | PB0 | I/O | | PB0 | ADC12_IN8/
TIM3_CH3(7) | TIM1_CH2N | | K4 | 19 | 27 | 36 | 16 | PB1 | I/O | | PB1 | ADC12_IN9/
TIM3_CH4(7) | TIM1_CH3N | | G5 | 20 | 28 | 37 | 17 | PB2 / BOOT1 | I/O | FT | PB2/BOOT1 | | H5 | - | - | 38 | - | PE7 | I/O | FT | PE7 | | TIM1_ETR | | J5 | - | - | 39 | - | PE8 | I/O | FT | PE8 | | TIM1_CH1N | | K5 | - | - | 40 | - | PE9 | I/O | FT | PE9 | | TIM1_CH1 | | G6 | - | - | 41 | - | PE10 | I/O | FT | PE10 | | TIM1_CH2N | | H6 | - | - | 42 | - | PE11 | I/O | FT | PE11 | | TIM1_CH2 | | J6 | - | - | 43 | - | PE12 | I/O | FT | PE12 | | TIM1_CH3N | | K6 | - | - | 44 | - | PE13 | I/O | FT | PE13 | | TIM1_CH3 | | G7 | - | - | 45 | - | PE14 | I/O | FT | PE14 | | TIM1_CH4 | | H7 | - | - | 46 | - | PE15 | I/O | FT | PE15 | | TIM1_BKIN | | J7 | 21 | 29 | 47 | - | PB10 | I/O | FT | PB10 | I2C2_SCL/
USART3_TX(6)(7) | TIM2_CH3 | | K7 | 22 | 30 | 48 | - | PB11 | I/O | FT | PB11 | I2C2_SDA/
USART3_RX(6)(7) | TIM2_CH4 | | E7 | 23 | 31 | 49 | 18 | VSS_1 | S | | VSS_1 |

Table 3. Pin definitions (continued)

		Pins					(2)		Alternate	unctions
BGA100	LQFP48	LQFP64	LQFP100	VFQFPN36	Pin name	Type (1)	I / O Level (2)	Main function (3) (after reset)	Default	Remap
F7	24	32	50	19	$V_{DD_1}$	S		$V_{DD_1}$
K8	25	33	51	-	PB12	I/O	FT	PB12	SPI2_NSS (6) / I2C2_SMBAI (6) / USART3_CK (6)(7) / TIM1_BKIN (7)
J8	26	34	52	1	PB13	I/O	FT	PB13	SPI2_SCK (6) / USART3_CTS (6)(7) TIM1_CH1N (7)
H8	27	35	53	1	PB14	I/O	FT	PB14	SPI2_MISO (6) / USART3_RTS (6)(7) TIM1_CH2N (7)
G8	28	36	54	1	PB15	I/O	FT	PB15	SPI2_MOSI (6) / TIM1_CH3N (7)
K9	-	-	55	-	PD8	I/O	FT	PD8		USART3_TX
J9	-	-	56	-	PD9	I/O	FT	PD9		USART3_RX
H9	-	-	57	-	PD10	I/O	FT	PD10		USART3_CK
G9	-	ı	58	-	PD11	I/O	FT	PD11		USART3_CTS
K10	-	-	59	-	PD12	I/O	FT	PD12		TIM4_CH1 / USART3_RTS
J10	-	-	60	-	PD13	I/O	FT	PD13		TIM4_CH2
H10	-	ı	61	-	PD14	I/O	FT	PD14		TIM4_CH3
G10	-	-	62	-	PD15	I/O	FT	PD15		TIM4_CH4
F10	-	37	63	-	PC6	I/O	FT	PC6		TIM3_CH1
E10		38	64	-	PC7	I/O	FT	PC7		TIM3_CH2
F9		39	65	-	PC8	I/O	FT	PC8		TIM3_CH3
E9	-	40	66	-	PC9	I/O	FT	PC9		TIM3_CH4
D9	29	41	67	20	PA8	I/O	FT	PA8	USART1_CK/ TIM1_CH1 (7) /MCO
C9	30	42	68	21	PA9	I/O	FT	PA9	USART1_TX (7) / TIM1_CH2 (7)
D10	31	43	69	22	PA10	I/O	FT	PA10	USART1_RX (7) / TIM1_CH3 (7)
C10	32	44	70	23	PA11	I/O	FT	PA11	USART1_CTS/ CANRX (7) / TIM1_CH4 (7) / USBDM

Table 3. Pin definitions (continued)

	e 3.	Pins	45		ions (continued)		2)		Alternate	functions
BGA100	LQFP48	LQFP64	LQFP100	VFQFPN36	Pin name	Type (1)	I / O Level (2)	Main function (3) (after reset)	Default	Remap
B10	33	45	71	24	PA12	I/O	FT	PA12	USART1_RTS/ CANTX (7) / TIM1_ETR (7) / USBDP
A10	34	46	72	25	PA13/JTMS/SWDIO	I/O	FT	JTMS/SWDIO	PA13
F8	-	-	73	-			Not c	connected
E6	35	47	74	26	$V_{SS_2}$	S		$V_{SS_2}$
F6	36	48	75	27	$V_{DD_2}$	S		$V_{DD_2}$
A9	37	49	76	28	PA14/JTCK/SWCLK	I/O	FT	JTCK/SWCLK	PA14
A8	38	50	77	29	PA15/JTDI	I/O	FT	JTDI	PA15	TIM2_CH1_ETR/ SPI1_NSS
B9	-	51	78		PC10	I/O	FT	PC10		USART3_TX
B8	-	52	79		PC11	I/O	FT	PC11		USART3_RX
C8	-	53	80		PC12	I/O	FT	PC12		USART3_CK
D8	5	5	81	2	PD0	I/O	FT	OSC_IN (8)		CANRX
E8	6	6	82	3	PD1	I/O	FT	OSC_OUT (8)		CANTX
B7		54	83	-	PD2	I/O	FT	PD2	TIM3_ETR
C7	-	-	84	-	PD3	I/O	FT	PD3		USART2_CTS
D7	-	-	85	-	PD4	I/O	FT	PD4		USART2_RTS
B6	-	-	86	-	PD5	I/O	FT	PD5		USART2_TX
C6	-	-	87	-	PD6	I/O	FT	PD6		USART2_RX
D6	-	-	88	-	PD7	I/O	FT	PD7		USART2_CK
A7	39	55	89	30	PB3/JTDO	I/O	FT	JTDO	PB3/TRACESWO	TIM2_CH2 / SPI1_SCK
A6	40	56	90	31	PB4/JNTRST	I/O	FT	JNTRST	PB4	TIM3_CH1 / SPI1_MISO
C5	41	57	91	32	PB5	I/O		PB5	I2C1_SMBAI	TIM3_CH2 / SPI1_MOSI
B5	42	58	92	33	PB6	I/O	FT	PB6	I2C1_SCL (7) / TIM4_CH1 (6)(7)	USART1_TX
A5	43	59	93	34	PB7	I/O	FT	PB7	I2C1_SDA (7) / TIM4_CH2 (6) (7)	USART1_RX
D5	44	60	94	35	BOOT0	I		BOOT0
B4	45	61	95	-	PB8	I/O	FT	PB8	TIM4_CH3 (6) (7)	I2C1_SCL / CANRX

Pin descriptions STM32F103xx

Table 3. Pin definitions (continued)

| | Pins | | | | | | | | Alternate functions | |--------|--------|--------|---------|----------|----------|---------|----------------|--------------------------------------|---------------------|---------------------|--| | BGA100 | LQFP48 | LQFP64 | LQFP100 | VFQFPN36 | Pin name | Type(1) | I / O Level(2) | Main
function(3)
(after reset) | Default | Remap | | A4 | 46 | 62 | 96 | - | PB9 | I/O | FT | PB9 | TIM4_CH4(6) (7) | I2C1_SDA /
CANTX | | D4 | - | - | 97 | - | PE0 | I/O | FT | PE0 | TIM4_ETR(6) | | C4 | - | - | 98 | - | PE1 | I/O | FT | PE1 | | E5 | 47 | 63 | 99 | 36 | VSS_3 | S | | VSS_3 | | F5 | 48 | 64 | 100 | 1 | VDD_3 | S | | VDD_3 |

STM32F103xx Memory mapping

The definition and values of input/output AC characteristics are given in Figure 21 and Table 35, respectively.

Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7.

Table 35. I/O AC characteristics(1)

MODEx[1:0] bit value(1)	Symbol	Parameter	Conditions	Min	Max	Unit
	fmax(IO)out	Maximum frequency(2)	CL = 50 pF, VDD = 2 V to 3.6 V		2	MHz
10	tf(IO)out	Output high to low level fall time			125(3)
	tr(IO)out	Output low to high level rise time	CL = 50 pF, VDD = 2 V to 3.6 V		125(3)	ns
	fmax(IO)out		Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V		10	MHz
01	tf(IO)out	Output high to low level fall time			25(3)	ns
tr(IO)out		Output low to high level rise time	CL = 50 pF, VDD = 2 V to 3.6 V		25(3)
			CL = 30 pF, VDD = 2.7 V to 3.6 V		50	MHz
	Fmax(IO)out	Maximum frequency(2)	CL = 50 pF, VDD = 2.7 V to 3.6 V		30	MHz
			CL = 50 pF, VDD = 2 V to 2.7 V		20	MHz
			CL = 30 pF, VDD = 2.7 V to 3.6 V		5(3)
11	tf(IO)out	Output high to low level fall time	CL = 50 pF, VDD = 2.7 V to 3.6 V		8(3)
			CL = 50 pF, VDD = 2 V to 2.7 V		12(3)	ns
			CL = 30 pF, VDD = 2.7 V to 3.6 V		5(3)
	tr(IO)out	Output low to high level rise time	CL = 50 pF, VDD = 2.7 V to 3.6 V		8(3)
			CL = 50 pF, VDD = 2 V to 2.7 V		12(3)
-	tEXTIpw	Pulse width of external signals detected by the EXTI controller		10		ns

^1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

^2. The maximum frequency is defined in Figure 21.

^3. Values based on design simulation and validated on silicon, not tested in production.

Figure 21. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics, Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 4. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
V DD -V SS	External main supply voltage (including $V_{DDA}$ and $V_{DD}$ ) (1)	-0.3	4.0
V	Input voltage on five volt tolerant pin (2)	V SS -0.3	+5.5	V
V IN	Input voltage on any other pin (2)	V SS -0.3	V DD +0.3
ΔV DDx	Variations between different power pins	50	50	mV
V SSX -V SS	Variations between all the different ground pins	50	50	IIIV
V ESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 5 Absolute max (electrical ser	imum ratings

Table 5. Current characteristics

Symbol	Ratings	Max.	Unit
I VDD	Total current into V DD power lines (source) (1)	150
I VSS	Total current out of V SS ground lines (sink) (1)	150
1.	Output current sunk by any I/O and control pin	25
l IO	Output current source by any I/Os and control pin	-25	mA
	Injected current on NRST pin	± 5	IIIA
I INJ(PIN) (2)(3)	Injected current on HSE OSC_IN and LSE OSC_IN pins	± 5
	Injected current on any other pin (4)	± 5
ΣΙ ΙΝJ(PIN) (2)	Total injected current (sum of all I/O and control pins) (4)	± 25

I_INJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if V_IN maximum is respected. If V_IN maximum cannot be respected, the injection current must be limited externally to the I_INJ(PIN) value. A positive injection is induced by V_IN>V_DD while a negative injection is induced by V_IN < V_SS.

^2. $I_{INJ(PIN)}$ must never be exceeded. This is implicitly insured if $V_{IN}$ maximum is respected. If $V_{IN}$ maximum cannot be respected, the injection current must be limited externally to the $I_{INJ(PIN)}$ value. A positive injection is induced by $V_{IN} > V_{DD}$ while a negative injection is induced by $V_{IN} < V_{SS}$ .

^3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC characteristics.

^4. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣI_INJ(PIN) maximum current injection on four I/O port pins of the device.

Table 6. Thermal characteristics

| Symbol | Ratings | Value | Unit | |--------|---------------------------|------------------------------------------------------------|------|--|--|--| | TSTG | Storage temperature range | –65 to +150 | °C | | TJ | | Maximum junction temperature (see Thermal characteristics) |

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation:

$$T_{J} = T_{A} + (P_{D} \times \Theta_{JA}) \tag{1}$$

Where:

• TA is the Ambient Temperature in ° C,
• ΘJA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
• PD is the sum of PINT and PI/O (PD = PINT + PI/O),
• PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power.

PI/O represents the Power Dissipation on Input and Output Pins;

Most of the time for the application PI/O< PINT and can be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories.

An approximate relationship between PD and TJ (if PI/O is neglected) is given by:

$$P_D = K / (T_J + 273 ,^{\circ}C)$$ (2)

Therefore (solving equations 1 and 2):

$$K = P_D x (T_A + 273^{\circ}C) + \Theta_{JA} x P_D^2$$ (3)

where:

K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA.

Table 53. Thermal characteristics

Symbol	Parameter	Value	Unit
	Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm / 0.5 mm pitch	41
	Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch	46
ΘJA	Thermal Resistance Junction-Ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch	45	°C/W
	Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch	55
	Thermal resistance junction-ambient VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch	18