STM32F103C8T6

STM32F103x6 STM32F103x8 STM32F103xB

Manufacturer

STMicroelectronics

Overview

Part: STM32F103x6, STM32F103x8, STM32F103xB

Type: ARM-based 32-bit MCU

Key Specs:

  • Core Frequency: 72 MHz (max)
  • Flash Memory: 32 to 128 Kbytes
  • SRAM: 6 to 20 Kbytes
  • Supply Voltage: 2.0 to 3.6 V
  • ADC: 2 x 12-bit, 1 µs (16-channel)
  • DMA: 7-channel
  • I/O Ports: Up to 80
  • Timers: Up to 7
  • Communication Interfaces: Up to 9

Features:

  • ARM 32-bit Cortex™-M3 CPU
  • Single-cycle multiplication and hardware division
  • POR, PDR, and programmable voltage detector (PVD)
  • Sleep, Stop and Standby low power modes
  • VBAT supply for RTC and backup registers
  • Temperature sensor
  • Dual-sample and hold capability for ADC
  • DMA supports timers, ADC, SPIs, I2Cs and USARTs
  • 5 V-tolerant I/Os (except analog inputs)
  • Serial wire debug (SWD) & JTAG interfaces
  • I2C (SMBus/PMBus), USART (ISO 7816, LIN, IrDA, modem control), SPI (18 Mbit/s), CAN (2.0B Active), USB 2.0 full speed interfaces
  • ECOPACK® (RoHS compliant) packages

Applications:

  • null

Package:

  • ECOPACK® (RoHS compliant): dimensions not specified

Features

  • Core: ARM 32-bit Cortex™-M3 CPU
    • 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
    • Single-cycle multiplication and hardware division

■ Memories

  • 32 to 128 Kbytes of Flash memory
  • 6 to 20 Kbytes of SRAM
  • Clock, reset and supply management
    • 2.0 to 3.6 V application supply and I/Os
    • POR, PDR, and programmable voltage detector (PVD)
    • 4-to-16 MHz crystal oscillator
    • Internal 8 MHz factory-trimmed RC
    • Internal 40 kHz RC
    • PLL for CPU clock
    • 32 kHz oscillator for RTC with calibration

■ Low power

  • Sleep, Stop and Standby modes
  • VBAT supply for RTC and backup registers
  • 2 x 12-bit, 1 µs A/D converters (16-channel)
    • Conversion range: 0 to 3.6 V
    • Dual-sample and hold capability
    • Temperature sensor

■ DMA

  • 7-channel DMA controller
  • Peripherals supported: timers, ADC, SPIs, I 2Cs and USARTs

■ Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

■ Up to 7 timers

  • Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter
  • 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output, deadtime generation and emergency stop
  • 2 watchdog timers (Independent and Window)
  • SysTick timer: a 24-bit downcounter
  • Up to 9 communication interfaces
    • Up to 2 x I2C interfaces (SMBus/PMBus)
    • Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
    • Up to 2 SPIs (18 Mbit/s)
    • CAN interface (2.0B Active)
    • USB 2.0 full speed interface
  • Packages are ECOPACK® (RoHS compliant)

Table 1. Device summary

ReferenceRoot part number
STM32F103x6STM32F103C6, STM32F103R6,
STM32F103T6
STM32F103x8STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103xBSTM32F103RB STM32F103VB,
STM32F103CB

Contents STM32F103xx

Pin Configuration

Figure 2. STM32F103xx performance line BGA100 ballout

STM32F103xx Pin descriptions

Figure 3. STM32F103xx performance line LQFP100 pinout

23 24 25

PA0-WKUP PA1 PA2

PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

53 52 51 PB14 PB13 PB12

ai14391

Pin descriptions STM32F103xx

Figure 5. STM32F103xx performance line LQFP48 pinout

STM32F103xx Pin descriptions

Figure 6. STM32F103xx VFQFPN36 pinout

Pin descriptions STM32F103xx

Table 3. Pin definitions

| | | Pins | | | | | | | Alternate functions | |--------|--------|--------|---------|----------|-----------------------|---------|----------------|--------------------------------------|----------------------------------------------------------|-------| | BGA100 | LQFP48 | LQFP64 | LQFP100 | VFQFPN36 | Pin name | Type(1) | I / O Level(2) | Main
function(3)
(after reset) | Default | Remap | | A3 | - | - | 1 | - | PE2 | I/O | FT | PE2 | TRACECK | | B3 | - | - | 2 | - | PE3 | I/O | FT | PE3 | TRACED0 | | C3 | - | - | 3 | - | PE4 | I/O | FT | PE4 | TRACED1 | | D3 | - | - | 4 | - | PE5 | I/O | FT | PE5 | TRACED2 | | E3 | - | - | 5 | - | PE6 | I/O | FT | PE6 | TRACED3 | | B2 | 1 | 1 | 6 | - | VBAT | S | | VBAT | | A2 | 2 | 2 | 7 | - | PC13-TAMPER
RTC(4) | I/O | | PC13(5) | TAMPER-RTC | | A1 | 3 | 3 | 8 | - | PC14-OSC32_IN(4) | I/O | | PC14(5) | OSC32_IN | | B1 | 4 | 4 | 9 | - | PC15-
OSC32_OUT(4) | I/O | | PC15(5) | OSC32_OUT | | C2 | - | - | 10 | - | VSS_5 | S | | VSS_5 | | D2 | - | - | 11 | - | VDD_5 | S | | VDD_5 | | C1 | 5 | 5 | 12 | 2 | OSC_IN | I | | OSC_IN | | D1 | 6 | 6 | 13 | 3 | OSC_OUT | O | | OSC_OUT | | E1 | 7 | 7 | 14 | 4 | NRST | I/O | | NRST | | F1 | - | 8 | 15 | - | PC0 | I/O | | PC0 | ADC12_IN10 | | F2 | - | 9 | 16 | - | PC1 | I/O | | PC1 | ADC12_IN11 | | E2 | - | 10 | 17 | - | PC2 | I/O | | PC2 | ADC12_IN12 | | F3 | - | 11 | 18 | - | PC3 | I/O | | PC3 | ADC12_IN13 | | G1 | 8 | 12 | 19 | 5 | VSSA | S | | VSSA | | H1 | - | - | 20 | - | VREF- | S | | VREF | | J1 | - | - | 21 | - | VREF+ | S | | VREF+ | | K1 | 9 | 13 | 22 | 6 | VDDA | S | | VDDA | | G2 | 10 | 14 | 23 | 7 | PA0-WKUP | I/O | | PA0 | WKUP/USART2_
CTS(7)/
ADC12_IN0/
TIM2_CH1_ETR(7) | | H2 | 11 | 15 | 24 | 8 | PA1 | I/O | | PA1 | USART2_RTS(7)/
ADC12_IN1/
TIM2_CH2(7) | | J2 | 12 | 16 | 25 | 9 | PA2 | I/O | | PA2 | USART2_TX(7)/
ADC12_IN2/
TIM2_CH3(7) | STM32F103xx Pin descriptions

Table 3. Pin definitions (continued)

| | | Pins | | | | | | | Alternate functions | |--------|--------|--------|---------|----------|-------------|---------|----------------|--------------------------------------|--------------------------------------------|-----------| | BGA100 | LQFP48 | LQFP64 | LQFP100 | VFQFPN36 | Pin name | Type(1) | I / O Level(2) | Main
function(3)
(after reset) | Default | Remap | | K2 | 13 | 17 | 26 | 10 | PA3 | I/O | | PA3 | USART2_RX(7)/
ADC12_IN3/
TIM2_CH4(7) | | E4 | - | 18 | 27 | - | VSS_4 | S | | VSS_4 | | F4 | - | 19 | 28 | - | VDD_4 | S | | VDD_4 | | G3 | 14 | 20 | 29 | 11 | PA4 | I/O | | PA4 | SPI1_NSS(7)/
USART2_CK(7)/
ADC12_IN4 | | H3 | 15 | 21 | 30 | 12 | PA5 | I/O | | PA5 | SPI1_SCK(7)/
ADC12_IN5 | | J3 | 16 | 22 | 31 | 13 | PA6 | I/O | | PA6 | SPI1_MISO(7)/
ADC12_IN6/
TIM3_CH1(7) | TIM1_BKIN | | K3 | 17 | 23 | 32 | 14 | PA7 | I/O | | PA7 | SPI1_MOSI(7)/
ADC12_IN7/
TIM3_CH2(7) | TIM1_CH1N | | G4 | - | 24 | 33 | | PC4 | I/O | | PC4 | ADC12_IN14 | | H4 | - | 25 | 34 | | PC5 | I/O | | PC5 | ADC12_IN15 | | J4 | 18 | 26 | 35 | 15 | PB0 | I/O | | PB0 | ADC12_IN8/
TIM3_CH3(7) | TIM1_CH2N | | K4 | 19 | 27 | 36 | 16 | PB1 | I/O | | PB1 | ADC12_IN9/
TIM3_CH4(7) | TIM1_CH3N | | G5 | 20 | 28 | 37 | 17 | PB2 / BOOT1 | I/O | FT | PB2/BOOT1 | | H5 | - | - | 38 | - | PE7 | I/O | FT | PE7 | | TIM1_ETR | | J5 | - | - | 39 | - | PE8 | I/O | FT | PE8 | | TIM1_CH1N | | K5 | - | - | 40 | - | PE9 | I/O | FT | PE9 | | TIM1_CH1 | | G6 | - | - | 41 | - | PE10 | I/O | FT | PE10 | | TIM1_CH2N | | H6 | - | - | 42 | - | PE11 | I/O | FT | PE11 | | TIM1_CH2 | | J6 | - | - | 43 | - | PE12 | I/O | FT | PE12 | | TIM1_CH3N | | K6 | - | - | 44 | - | PE13 | I/O | FT | PE13 | | TIM1_CH3 | | G7 | - | - | 45 | - | PE14 | I/O | FT | PE14 | | TIM1_CH4 | | H7 | - | - | 46 | - | PE15 | I/O | FT | PE15 | | TIM1_BKIN | | J7 | 21 | 29 | 47 | - | PB10 | I/O | FT | PB10 | I2C2_SCL/
USART3_TX(6)(7) | TIM2_CH3 | | K7 | 22 | 30 | 48 | - | PB11 | I/O | FT | PB11 | I2C2_SDA/
USART3_RX(6)(7) | TIM2_CH4 | | E7 | 23 | 31 | 49 | 18 | VSS_1 | S | | VSS_1 | Pin descriptions STM32F103xx

Table 3. Pin definitions (continued)

Pins(2)Alternateunctions
BGA100LQFP48LQFP64LQFP100VFQFPN36Pin nameType (1)I / O Level (2)Main
function (3)
(after reset)		DefaultRemap
F724325019$V_{DD_1}$S$V_{DD_1}$
K8253351-PB12I/OFTPB12SPI2_NSS (6) /
I2C2_SMBAI (6) /
USART3_CK (6)(7) /
TIM1_BKIN (7)
J82634521PB13I/OFTPB13SPI2_SCK (6) /
USART3_CTS (6)(7)
TIM1_CH1N (7)
H82735531PB14I/OFTPB14SPI2_MISO (6) /
USART3_RTS (6)(7)
TIM1_CH2N (7)
G82836541PB15I/OFTPB15SPI2_MOSI (6) /
TIM1_CH3N (7)
K9--55-PD8I/OFTPD8USART3_TX
J9--56-PD9I/OFTPD9USART3_RX
H9--57-PD10I/OFTPD10USART3_CK
G9-ı58-PD11I/OFTPD11USART3_CTS
K10--59-PD12I/OFTPD12TIM4_CH1 /
USART3_RTS
J10--60-PD13I/OFTPD13TIM4_CH2
H10-ı61-PD14I/OFTPD14TIM4_CH3
G10--62-PD15I/OFTPD15TIM4_CH4
F10-3763-PC6I/OFTPC6TIM3_CH1
E103864-PC7I/OFTPC7TIM3_CH2
F93965-PC8I/OFTPC8TIM3_CH3
E9-4066-PC9I/OFTPC9TIM3_CH4
D929416720PA8I/OFTPA8USART1_CK/
TIM1_CH1 (7) /MCO
C930426821PA9I/OFTPA9USART1_TX (7) /
TIM1_CH2 (7)
D1031436922PA10I/OFTPA10USART1_RX (7) /
TIM1_CH3 (7)
C1032447023PA11I/OFTPA11USART1_CTS/
CANRX (7) /
TIM1_CH4 (7) /
USBDM
STM32F103xx Pin descriptions

Table 3. Pin definitions (continued)

e 3.Pins45ions (continued)2)Alternatefunctions
BGA100LQFP48LQFP64LQFP100VFQFPN36Pin nameType (1)I / O Level (2)Main
function (3)
(after reset)		DefaultRemap
B1033457124PA12I/OFTPA12USART1_RTS/
CANTX (7) /
TIM1_ETR (7) /
USBDP
A1034467225PA13/JTMS/SWDIOI/OFTJTMS/SWDIOPA13
F8--73-Not cconnected
E635477426$V_{SS_2}$S$V_{SS_2}$
F636487527$V_{DD_2}$S$V_{DD_2}$
A937497628PA14/JTCK/SWCLKI/OFTJTCK/SWCLKPA14
A838507729PA15/JTDII/OFTJTDIPA15TIM2_CH1_ETR/
SPI1_NSS
B9-5178PC10I/OFTPC10USART3_TX
B8-5279PC11I/OFTPC11USART3_RX
C8-5380PC12I/OFTPC12USART3_CK
D855812PD0I/OFTOSC_IN (8)CANRX
E866823PD1I/OFTOSC_OUT (8)CANTX
B75483-PD2I/OFTPD2TIM3_ETR
C7--84-PD3I/OFTPD3USART2_CTS
D7--85-PD4I/OFTPD4USART2_RTS
B6--86-PD5I/OFTPD5USART2_TX
C6--87-PD6I/OFTPD6USART2_RX
D6--88-PD7I/OFTPD7USART2_CK
A739558930PB3/JTDOI/OFTJTDOPB3/TRACESWOTIM2_CH2 /
SPI1_SCK
A640569031PB4/JNTRSTI/OFTJNTRSTPB4TIM3_CH1 /
SPI1_MISO
C541579132PB5I/OPB5I2C1_SMBAITIM3_CH2 /
SPI1_MOSI
B542589233PB6I/OFTPB6I2C1_SCL (7) /
TIM4_CH1 (6)(7)		USART1_TX
A543599334PB7I/OFTPB7I2C1_SDA (7) /
TIM4_CH2 (6) (7)		USART1_RX
D544609435BOOT0IBOOT0
B4456195-PB8I/OFTPB8TIM4_CH3 (6) (7)I2C1_SCL /
CANRX

Pin descriptions STM32F103xx

Table 3. Pin definitions (continued)

| | Pins | | | | | | | | Alternate functions | |--------|--------|--------|---------|----------|----------|---------|----------------|--------------------------------------|---------------------|---------------------|--| | BGA100 | LQFP48 | LQFP64 | LQFP100 | VFQFPN36 | Pin name | Type(1) | I / O Level(2) | Main
function(3)
(after reset) | Default | Remap | | A4 | 46 | 62 | 96 | - | PB9 | I/O | FT | PB9 | TIM4_CH4(6) (7) | I2C1_SDA /
CANTX | | D4 | - | - | 97 | - | PE0 | I/O | FT | PE0 | TIM4_ETR(6) | | C4 | - | - | 98 | - | PE1 | I/O | FT | PE1 | | E5 | 47 | 63 | 99 | 36 | VSS_3 | S | | VSS_3 | | F5 | 48 | 64 | 100 | 1 | VDD_3 | S | | VDD_3 |

    1. I = input, O = output, S = supply, HiZ = high impedance.
    1. FT = 5 V tolerant.
    1. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 8.
    1. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
    1. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
    1. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
    1. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
    1. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.

STM32F103xx Memory mapping

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 21 and Table 35, respectively.

Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7.

Table 35. I/O AC characteristics(1)

MODEx[1:0]
bit value(1)		SymbolParameterConditionsMinMaxUnit
fmax(IO)outMaximum frequency(2)CL = 50 pF, VDD = 2 V to 3.6 V2MHz
10tf(IO)outOutput high to low
level fall time		125(3)
tr(IO)outOutput low to high
level rise time		CL = 50 pF, VDD = 2 V to 3.6 V125(3)ns
fmax(IO)outMaximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V10MHz
01tf(IO)outOutput high to low
level fall time		25(3)ns
tr(IO)outOutput low to high
level rise time		CL = 50 pF, VDD = 2 V to 3.6 V25(3)
CL = 30 pF, VDD = 2.7 V to 3.6 V50MHz
Fmax(IO)outMaximum frequency(2)CL = 50 pF, VDD = 2.7 V to 3.6 V30MHz
CL = 50 pF, VDD = 2 V to 2.7 V20MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V5(3)
11tf(IO)outOutput high to low
level fall time		CL = 50 pF, VDD = 2.7 V to 3.6 V8(3)
CL = 50 pF, VDD = 2 V to 2.7 V12(3)ns
CL = 30 pF, VDD = 2.7 V to 3.6 V5(3)
tr(IO)outOutput low to high
level rise time		CL = 50 pF, VDD = 2.7 V to 3.6 V8(3)
CL = 50 pF, VDD = 2 V to 2.7 V12(3)
-tEXTIpwPulse width of
external signals
detected by the EXTI
controller		10ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 21.

3. Values based on design simulation and validated on silicon, not tested in production.

Figure 21. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics, Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 4. Voltage characteristics

SymbolRatingsMinMaxUnit
V DD -V SSExternal main supply voltage (including $V_{DDA}$ and $V_{DD}$ ) (1)-0.34.0
VInput voltage on five volt tolerant pin (2)V SS -0.3+5.5V
V INInput voltage on any other pin (2)V SS -0.3V DD +0.3
ΔV DDxVariations between different power pins5050mV
V SSX -V SSVariations between all the different ground pins5050IIIV
V ESD(HBM)Electrostatic discharge voltage (human body model)see Section 5
Absolute max
(electrical ser		imum ratings
All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

Table 5. Current characteristics

SymbolRatingsMax.Unit
I VDDTotal current into V DD power lines (source) (1)150
I VSSTotal current out of V SS ground lines (sink) (1)150
1.Output current sunk by any I/O and control pin25
l IOOutput current source by any I/Os and control pin-25mA
Injected current on NRST pin± 5IIIA
I INJ(PIN) (2)(3)Injected current on HSE OSC_IN and LSE OSC_IN pins± 5
Injected current on any other pin (4)± 5
ΣΙ ΙΝJ(PIN) (2)Total injected current (sum of all I/O and control pins) (4)± 25
All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN < VSS.

2. $I_{INJ(PIN)}$ must never be exceeded. This is implicitly insured if $V_{IN}$ maximum is respected. If $V_{IN}$ maximum cannot be respected, the injection current must be limited externally to the $I_{INJ(PIN)}$ value. A positive injection is induced by $V_{IN} > V_{DD}$ while a negative injection is induced by $V_{IN} < V_{SS}$ .

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC characteristics.

4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.

Table 6. Thermal characteristics

| Symbol | Ratings | Value | Unit | |--------|---------------------------|------------------------------------------------------------|------|--|--|--| | TSTG | Storage temperature range | –65 to +150 | °C | | TJ | | Maximum junction temperature (see Thermal characteristics) |

Thermal Information

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation:

$$T_{J} = T_{A} + (P_{D} \times \Theta_{JA}) \tag{1}$$

Where:

  • TA is the Ambient Temperature in ° C,
  • ΘJA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
  • PD is the sum of PINT and PI/O (PD = PINT + PI/O),
  • PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power.

PI/O represents the Power Dissipation on Input and Output Pins;

Most of the time for the application PI/O< PINT and can be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories.

An approximate relationship between PD and TJ (if PI/O is neglected) is given by:

$$P_D = K / (T_J + 273 ,^{\circ}C)$$ (2)

Therefore (solving equations 1 and 2):

$$K = P_D x (T_A + 273^{\circ}C) + \Theta_{JA} x P_D^2$$ (3)

where:

K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA.

Table 53. Thermal characteristics

SymbolParameterValueUnit
Thermal resistance junction-ambient
LFBGA100 - 10 x 10 mm / 0.5 mm pitch		41
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch		46
ΘJAThermal Resistance Junction-Ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch		45°C/W
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch		55
Thermal resistance junction-ambient
VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch		18
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