Part: STM32F103x6, STM32F103x8, STM32F103xB (STMicroelectronics)

Type: ARM Cortex-M3 MCU

Description: ARM Cortex-M3 32-bit MCU operating at 72 MHz with up to 128 KB Flash, 20 KB SRAM, two 12-bit ADCs, and extensive communication interfaces including USB and CAN.

Operating Conditions:

• Supply voltage: 2.0 to 3.6 V
• Operating temperature: -40 to +105 °C
• Max CPU frequency: 72 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max continuous current: 120 mA (Total current into VDD_x and VDD_x pins)
• Max junction/storage temperature: 150 °C (Storage temperature range)

Key Specs:

• Core: ARM 32-bit Cortex-M3 CPU
• Max CPU frequency: 72 MHz
• Flash memory: 32 to 128 Kbytes
• SRAM: 6 to 20 Kbytes
• ADC: 2 x 12-bit, 1 μs A/D converters (16-channel)
• I/O ports: Up to 80 fast I/O ports, 5 V-tolerant (except analog inputs)
• SPI speed: Up to 18 Mbit/s
• Run mode current consumption: Max 36 mA (at VDD=3.6V, fHCLK=72MHz, code from Flash, all peripherals enabled)

Features:

• ARM 32-bit Cortex-M3 CPU, 72 MHz max frequency
• 32 to 128 Kbytes Flash, 6 to 20 Kbytes SRAM
• 2 x 12-bit, 1 μs A/D converters (16-channel)
• Up to 9 communication interfaces (I2C, USART, SPI, CAN, USB)
• Serial wire debug (SWD) & JTAG interfaces

Applications:

• Motor drive and application control
• Medical and handheld equipment
• PC peripherals gaming and GPS platforms
• Industrial applications: PLC, inverters, printers, and scanners
• Alarm systems, Video intercom, and HVAC

Package:

• LQFP100 14 x 14 mm
• LQFP64 10 x 10 mm
• LQFP48 7 x 7 mm
• VFQFPN36 6 × 6 mm
• BGA100 10 x 10 mm

• ■ Core: ARM 32-bit Cortex™-M3 CPU
• -72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
• -Single-cycle multiplication and hardware division
• ■ Memories
• -32 to 128 Kbytes of Flash memory
• -6 to 20 Kbytes of SRAM
• ■ Clock, reset and supply management
• -2.0 to 3.6 V application supply and I/Os
• -POR, PDR, and programmable voltage detector (PVD)
• -4-to-16 MHz crystal oscillator
• -Internal 8 MHz factory-trimmed RC
• -Internal 40 kHz RC
• -PLL for CPU clock
• -32 kHz oscillator for RTC with calibration
• ■ Low power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC and backup registers
• ■ 2 x 12-bit, 1 μs A/D converters (16-channel)
• -Conversion range: 0 to 3.6 V
• -Dual-sample and hold capability
• -Temperature sensor
• ■ DMA
• -7-channel DMA controller
• -Peripherals supported: timers, ADC, SPIs, I 2 Cs and USARTs
• ■ Up to 80 fast I/O ports
• -26/37/51/80 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs

LQFP100 14 x 14 mm

LQFP48 7 x 7 mm

VFQFPN36 6 × 6 mm

• ■ Debug mode
• -Serial wire debug (SWD) & JTAG interfaces
• ■ Up to 7 timers
• -Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter
• -16-bit, 6-channel advanced control timer: up to 6 channels for PWM output, deadtime generation and emergency stop
• -2 watchdog timers (Independent and Window)
• -SysTick timer: a 24-bit downcounter
• ■ Up to 9 communication interfaces
• -Up to 2 x I 2 C interfaces (SMBus/PMBus)
• -Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
• -Up to 2 SPIs (18 Mbit/s)
• -CAN interface (2.0B Active)
• -USB 2.0 full speed interface
• ■ Packages are ECOPACK® (RoHS compliant)

STM32F103C8T6 – 48-LQFP Pinout

Pin	Pin Name	Type	I/O Level	Main Function	Alternate Functions (Default)	Alternate Functions (Remap)
1	VBAT	S	—	VBAT	—	—
2	PC13-TAMPER-RTC	I/O	—	PC13	TAMPER-RTC	—
3	PC14-OSC32_IN	I/O	—	PC14	OSC32_IN	—
4	PC15-OSC32_OUT	I/O	—	PC15	OSC32_OUT	—
5	OSC_IN	I	—	OSC_IN	—	—
6	OSC_OUT	O	—	OSC_OUT	—	—
7	NRST	I/O	—	NRST	—	—
8	VSSA	S	—	VSSA	—	—
9	VDDA	S	—	VDDA	—	—
10	PA0-WKUP	I/O	—	PA0	WKUP / USART2_CTS / ADC12_IN0 / TIM2_CH1_ETR	—
11	PA1	I/O	—	PA1	USART2_RTS / ADC12_IN1 / TIM2_CH2	—
12	PA2	I/O	—	PA2	USART2_TX / ADC12_IN2 / TIM2_CH3	—
13	PA3	I/O	—	PA3	USART2_RX / ADC12_IN3 / TIM2_CH4	—
14	PA4	I/O	—	PA4	SPI1_NSS / USART2_CK / ADC12_IN4	—
15	PA5	I/O	—	PA5	SPI1_SCK / ADC12_IN5	—
16	PA6	I/O	—	PA6	SPI1_MISO / ADC12_IN6 / TIM3_CH1	TIM1_BKIN
17	PA7	I/O	—	PA7	SPI1_MOSI / ADC12_IN7 / TIM3_CH2	TIM1_CH1N
18	PB0	I/O	—	PB0	ADC12_IN8 / TIM3_CH3	TIM1_CH2N
19	PB1	I/O	—	PB1	ADC12_IN9 / TIM3_CH4	TIM1_CH3N
20	PB2/BOOT1	I/O	FT	PB2/BOOT1	—	—
21	PB10	I/O	FT	PB10	I2C2_SCL / USART3_TX	TIM2_CH3
22	PB11	I/O	FT	PB11	I2C2_SDA / USART3_RX	TIM2_CH4
23	VSS_1	S	—	VSS_1	—	—
24	VDD_1	S	—	VDD_1	—	—
25	PB12	I/O	FT	PB12	SPI2_NSS / I2C2_SMBAL / USART3_CK / TIM1_BKIN	—
26	PB13	I/O	FT	PB13	SPI2_SCK / USART3_CTS / TIM1_CH1N	—
27	PB14	I/O	FT	PB14	SPI2_MISO / USART3_RTS / TIM1_CH2N	—
28	PB15	I/O	FT	PB15	SPI2_MOSI / TIM1_CH3N	—
29	PA8	I/O	FT	PA8	USART1_CK / TIM1_CH1 / MCO	—
30	PA9	I/O	FT	PA9	USART1_TX / TIM1_CH2	—
31	PA10	I/O	FT	PA10	USART1_RX / TIM1_CH3	—
32	PA11	I/O	FT	PA11	USART1_CTS / CANRX / TIM1_CH4 / USBDM	—
33	PA12	I/O	FT	PA12	USART1_RTS / CANTX / TIM1_ETR / USBDP	—
34	PA13/JTMS/SWDIO	I/O	FT	JTMS/SWDIO	PA13	—
35	VSS_2	S	—	VSS_2	—	—
36	VDD_2	S	—	VDD_2	—	—
37	PA14/JTCK/SWCLK	I/O	FT	JTCK/SWCLK	PA14	—
38	PA15/JTDI	I/O	FT	JTDI	PA15	TIM2_CH1_ETR / SPI1_NSS
39	PB3/JTDO	I/O	FT	JTDO	PB3/TRACESWO	TIM2_CH2 / SPI1_SCK
40	PB4/JNTRST	I/O	FT	JNTRST	PB4	TIM3_CH1 / SPI1_MISO
41	PB5	I/O	—	PB5	I2C1_SMBAL	TIM3_CH2 / SPI1_MOSI
42	PB6	I/O	FT	PB6	I2C1_SCL / TIM4_CH1	USART1_TX
43	PB7	I/O	FT	PB7	I2C1_SDA / TIM4_CH2	USART1_RX
44	BOOT0	I	—	BOOT0	—	—
45	PB8	I/O	FT	PB8	TIM4_CH3	I2C1_SCL / CANRX
46	PB9	I/O	FT	PB9	TIM4_CH4	I2C1_SDA / CANTX
47	VSS_3	S	—	VSS_3	—	—
48	VDD_3	S	—	VDD_3	—	—

Notes

• FT (5V Tolerant): Pins marked FT can tolerate 5V input levels.
• PC13–PC15 limitations: These pins are supplied through the power switch and are limited to 2 MHz output mode with a maximum load of 30 pF. Only one of these pins can be in output mode at a time.
• PD0/PD1 remapping: Pins 5 and 6 (OSC_IN/OSC_OUT) are configured as oscillator pins after reset, but PD0 and PD1 functionality can be remapped via software. When used in output mode, they are limited to 50 MHz.
• Alternate functions: Many pins support software-remappable alternate functions. Refer to the STM32F10xxx reference manual for detailed remapping procedures.
• Peripheral availability: Function availability depends on the device variant. The STM32F103C8 has reduced peripheral counts compared to higher-density variants (e.g., STM32F103RB, STM32F103VB).

The definition and values of input/output AC characteristics are given in Figure 21 and Table 35 , respectively.

Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 7 .

Table 35. I/O AC characteristics (1)

MODEx[1:0] bit value (1)	Symbol	Parameter	Conditions	Min	Max	Unit
10	f max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 3.6 V		2	MHz
10	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 3.6 V		125 (3)	ns
10	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 3.6 V		125 (3)	ns
01	f max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 3.6 V		10	MHz
01	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 3.6 V		25 (3)	ns
01	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 3.6 V		25 (3)	ns
11	F max(IO)out	Maximum frequency (2)	C L = 30 pF, V DD = 2.7 V to 3.6 V		50	MHz
11	F max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2.7 V to 3.6 V		30	MHz
11	F max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 2.7 V		20	MHz
11	t f(IO)out	Output high to low level fall time	C L = 30 pF, V DD = 2.7 V to 3.6 V		5 (3)	ns
11	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2.7 V to 3.6 V		8 (3)	ns
11	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 2.7 V		12 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 30 pF, V DD = 2.7 V to 3.6 V		5 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2.7 V to 3.6 V		8 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 2.7 V		12 (3)	ns
-	t EXTIpw	Pulse width of external signals detected by the EXTI controller		10		ns

1. The maximum frequency is defined in Figure 21 .
2. Values based on design simulation and validated on silicon, not tested in production.

Figure 21. I/O AC characteristics definition

Figure 21. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics , Table 5: Current characteristics , and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 4. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
V DD -V SS	External main supply voltage (including V DDA and V DD ) (1)	-0.3	4.0	V
V IN	Input voltage on five volt tolerant pin (2)	V SS - 0.3	+5.5	V
V IN	Input voltage on any other pin (2)	V SS - 0.3	V DD +0.3	V
\	∆ V DDx \		Variations between different power pins	50
\	V SSX - V SS \		Variations between all the different ground pins	50
V ESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 5.3.11: Absolute maximum ratings (electrical sensitivity)	see Section 5.3.11: Absolute maximum ratings (electrical sensitivity)

Symbol	Ratings	Max.	Unit
I VDD	Total current into V DD power lines (source) (1)	150	mA
I VSS	Total current out of V SS ground lines (sink) (1)	150	mA
I IO	Output current sunk by any I/O and control pin	25	mA
I IO	Output current source by any I/Os and control pin	- 25	mA
I INJ(PIN) (2)(3)	Injected current on NRST pin	± 5	mA
I INJ(PIN) (2)(3)	Injected current on HSE OSC_IN and LSE OSC_IN pins	± 5	mA
I INJ(PIN) (2)(3)	Injected current on any other pin (4)	± 5	mA
Σ I INJ(PIN) (2)	Total injected current (sum of all I/O and control pins) (4)	± 25	mA

1. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with Σ I INJ(PIN) maximum current injection on four I/O port pins of the device.

Table 6. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature (see Thermal characteristics)	Maximum junction temperature (see Thermal characteristics)	Maximum junction temperature (see Thermal characteristics)

The average chip-junction temperature, T J , in degrees Celsius, may be calculated using the following equation:T _ { J } = T _ { A } + ( P _ { D } × Θ _ { J A } )

Where:

• T A is the Ambient Temperature in ° C,
• Θ JA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
• PD is the sum of P INT and P I/O (P D = P INT + P I/O ),
• PINT is the product of I DD and VDD , expressed in Watts. This is the Chip Internal Power.

PI/O represents the Power Dissipation on Input and Output Pins;

Most of the time for the application P I/O < PINT and can be neglected. On the other hand, P I/O may be significant if the device is configured to drive continuously external modules and/or memories.

An approximate relationship between P D and T J (if P I/O is neglected) is given by:

P_D= K /(T_J+ 2 7 3 °ledast C)

Therefore (solving equations 1 and 2):

K = P_D×(T_A+ 2 7 3^°C)+ Θ_JA× P_D²(3)

where:

K is a constant for the particular part, which may be determined from equation (3) by measuring P D (at equilibrium) for a known T A. Using this value of K, the values of P D and T J may be obtained by solving equations (1) and (2) iteratively for any value of T A .

Table 53. Thermal characteristics

Symbol	Parameter	Value	Unit
Θ JA	Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm/ 0.5 mm pitch	41	°C/W
Θ JA	Thermal resistance junction-ambient LQFP100 - 14 x 14 mm/ 0.5 mm pitch	46	°C/W
Θ JA	Thermal Resistance Junction-Ambient LQFP64 - 10 x 10 mm/ 0.5 mm pitch	45	°C/W
Θ JA	Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch	55	°C/W
Θ JA	Thermal resistance junction-ambient VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch	18	°C/W

Table 53. Thermal characteristics