STM32F103C8T6

Part: STM32F103C8T6 (STM32F103x6/x8/xB performance line) — STMicroelectronics

Type: ARM Cortex-M3 32-bit MCU

Description: 72 MHz ARM Cortex-M3 MCU with 64 Kbytes Flash and 20 Kbytes SRAM, 2.0–3.6 V supply, USB 2.0 full speed, CAN 2.0B, two 12-bit ADCs and up to nine communication interfaces.

Operating Conditions:

• Supply voltage (VDD): 2.0–3.6 V
• Operating temperature: -40 to 85 °C (suffix-dependent: the family is also offered in a -40 to 105 °C extended range; Table 7 lists a TA maximum of 105 °C)
• Max AHB clock (fHCLK): 72 MHz (APB1 36 MHz, APB2 72 MHz)
• Backup supply (VBAT): 1.8–3.6 V

Absolute Maximum Ratings:

• Max supply voltage (VDD–VSS): 4.0 V (min -0.3 V)
• Input voltage on five-volt tolerant pin: VSS - 0.3 to +5.5 V
• Input voltage on any other pin: VSS - 0.3 to VDD + 0.3 V
• Total current into VDD lines: 150 mA; total current out of VSS lines: 150 mA
• Output current sunk/sourced by any I/O pin: 25 mA
• Injected current per pin: ±5 mA (total ±25 mA)
• Storage temperature: -65 to +150 °C

Key Specs:

• Core: ARM Cortex-M3, up to 72 MHz, 1.25 DMIPS/MHz
• Memory (STM32F103C8): 64 Kbytes Flash, 20 Kbytes SRAM
• I/O: 37 GPIOs on the LQFP48 (C-series) package, mostly 5 V tolerant except analog inputs
• ADC: 2 × 12-bit, 1 μs conversion, 10 channels (C-series), 0 to 3.6 V conversion range
• Timers: three 16-bit general-purpose timers, one 16-bit 6-channel advanced control timer, 2 watchdogs, 24-bit SysTick
• Communication: 2 × I2C, 3 × USART, 2 × SPI (up to 18 Mbit/s), CAN 2.0B, USB 2.0 full speed
• DMA: 7-channel controller
• Clocks: 4–16 MHz crystal oscillator, internal 8 MHz RC, internal 40 kHz RC, PLL, 32 kHz RTC oscillator

Features:

• ARM 32-bit Cortex-M3 CPU with single-cycle multiplication and hardware division
• POR, PDR and programmable voltage detector (PVD)
• Sleep, Stop and Standby low-power modes; VBAT supply for RTC and backup registers
• Temperature sensor
• Serial wire debug (SWD) and JTAG interfaces
• ECOPACK (RoHS compliant) packages

Applications:

• Motor drive and application control
• Medical and handheld equipment
• PC peripherals, gaming and GPS platforms
• Industrial applications: PLC, inverters, printers, scanners
• Alarm systems, video intercom, HVAC

Package:

• LQFP48 (7 × 7 mm) for the STM32F103Cx series
• Family also offered in VFQFPN36 (6 × 6 mm), LQFP64 (10 × 10 mm), LQFP100 (14 × 14 mm) and BGA100 (10 × 10 mm)

• ■ Core: ARM 32-bit Cortex™-M3 CPU
• -72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
• -Single-cycle multiplication and hardware division
• ■ Memories
• -32 to 128 Kbytes of Flash memory
• -6 to 20 Kbytes of SRAM
• ■ Clock, reset and supply management
• -2.0 to 3.6 V application supply and I/Os
• -POR, PDR, and programmable voltage detector (PVD)
• -4-to-16 MHz crystal oscillator
• -Internal 8 MHz factory-trimmed RC
• -Internal 40 kHz RC
• -PLL for CPU clock
• -32 kHz oscillator for RTC with calibration
• ■ Low power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC and backup registers
• ■ 2 x 12-bit, 1 μs A/D converters (16-channel)
• -Conversion range: 0 to 3.6 V
• -Dual-sample and hold capability
• -Temperature sensor
• ■ DMA
• -7-channel DMA controller
• -Peripherals supported: timers, ADC, SPIs, I 2 Cs and USARTs
• ■ Up to 80 fast I/O ports
• -26/37/51/80 I/Os, all mappable on 16 external interrupt vectors, all 5 V-tolerant except for analog inputs

LQFP100 14 x 14 mm

LQFP48 7 x 7 mm

VFQFPN36 6 × 6 mm

• ■ Debug mode
• -Serial wire debug (SWD) & JTAG interfaces
• ■ Up to 7 timers
• -Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter
• -16-bit, 6-channel advanced control timer: up to 6 channels for PWM output, deadtime generation and emergency stop
• -2 watchdog timers (Independent and Window)
• -SysTick timer: a 24-bit downcounter
• ■ Up to 9 communication interfaces
• -Up to 2 x I 2 C interfaces (SMBus/PMBus)
• -Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
• -Up to 2 SPIs (18 Mbit/s)
• -CAN interface (2.0B Active)
• -USB 2.0 full speed interface
• ■ Packages are ECOPACK® (RoHS compliant)

Figure 2. STM32F103xx performance line BGA100 ballout

Figure 3. STM32F103xx performance line LQFP100 pinout

Figure 4. STM32F103xx performance line LQFP64 pinout

Figure 5. STM32F103xx performance line LQFP48 pinout

Figure 6. STM32F103xx VFQFPN36 pinout

Table 3. Pin definitions

Pins	Pins	Pins	Pins	Pins		(1)	Level (2)		Alternate functions	Alternate functions
BGA100	LQFP48	LQFP64	LQFP100	VFQFPN36	Pin name	(1)	Level (2)	Main function (3) (after reset)	Default	Remap
A3	-	-	1	-	PE2	I/O	FT	PE2	TRACECK
B3	-	-	2	-	PE3	I/O	FT	PE3	TRACED0
C3	-	-	3	-	PE4	I/O	FT	PE4	TRACED1
D3	-	-	4	-	PE5	I/O	FT	PE5	TRACED2
E3	-	-	5	-	PE6	I/O	FT	PE6	TRACED3
B2	1	1	6	-	V BAT	S		V BAT
A2	2	2	7	-	PC13-TAMPER- RTC (4)	I/O		PC13 (5)	TAMPER-RTC
A1	3	3	8	-	PC14-OSC32_IN (4)	I/O		PC14 (5)	OSC32_IN
B1	4	4	9	-	PC15- OSC32_OUT (4)	I/O		PC15 (5)	OSC32_OUT
C2	-	-	10	-	V SS_5	S		V SS_5
D2	-	-	11	-	V DD_5	S		V DD_5
C1	5	5	12	2	OSC_IN	I		OSC_IN
D1	6	6	13	3	OSC_OUT	O		OSC_OUT
E1	7	7	14	4	NRST	I/O		NRST
F1	-	8	15	-	PC0	I/O		PC0	ADC12_IN10
F2	-	9	16	-	PC1	I/O		PC1	ADC12_IN11
E2	-	10	17	-	PC2	I/O		PC2	ADC12_IN12
F3	-	11	18	-	PC3	I/O		PC3	ADC12_IN13
G1	8	12	19	5	V SSA	S		V SSA
H1	-	-	20	-	V REF-	S		V REF-
J1	-	-	21	-	V REF+	S		V REF+
K1	9	13	22	6	V DDA	S		V DDA
G2	10	14	23	7	PA0-WKUP	I/O		PA0	WKUP/USART2_ CTS (7) / ADC12_IN0/ TIM2_CH1_ETR (7)
H2	11	15	24	8	PA1	I/O		PA1	USART2_RTS (7) / ADC12_IN1/ TIM2_CH2 (7)
J2	12	16	25	9	PA2	I/O		PA2	USART2_TX (7) / ADC12_IN2/ TIM2_CH3 (7)

Table 3. Pin definitions

Table 3. Pin definitions (continued)

Pins	Pins	Pins	Pins	Pins		(1)	Level (2)	Main function (3)	Alternate functions	Alternate functions
BGA100	LQFP48	LQFP64	LQFP100	VFQFPN36	Pin name	(1)	Level (2)	(after reset)	Default	Remap
K2	13	17	26	10	PA3	I/O		PA3	USART2_RX (7) / ADC12_IN3/ TIM2_CH4 (7)
E4	-	18	27	-	V SS_4	S		V SS_4
F4	-	19	28	-	V DD_4	S		V DD_4
G3	14	20	29	11	PA4	I/O		PA4	SPI1_NSS (7) / USART2_CK (7) / ADC12_IN4
H3	15	21	30	12	PA5	I/O		PA5	SPI1_SCK (7) / ADC12_IN5
J3	16	22	31	13	PA6	I/O		PA6	SPI1_MISO (7) / ADC12_IN6/ TIM3_CH1 (7)	TIM1_BKIN
K3	17	23	32	14	PA7	I/O		PA7	SPI1_MOSI (7) / ADC12_IN7/ TIM3_CH2 (7)	TIM1_CH1N
G4	-	24	33		PC4	I/O		PC4	ADC12_IN14
H4	-	25	34		PC5	I/O		PC5	ADC12_IN15
J4	18	26	35	15	PB0	I/O		PB0	ADC12_IN8/ TIM3_CH3 (7)	TIM1_CH2N
K4	19	27	36	16	PB1	I/O		PB1	ADC12_IN9/ TIM3_CH4 (7)	TIM1_CH3N
G5	20	28	37	17	PB2 / BOOT1	I/O	FT	PB2/BOOT1
H5	-	-	38	-	PE7	I/O	FT	PE7		TIM1_ETR
J5	-	-	39	-	PE8	I/O	FT	PE8		TIM1_CH1N
K5	-	-	40	-	PE9	I/O	FT	PE9		TIM1_CH1
G6	-	-	41	-	PE10	I/O	FT	PE10		TIM1_CH2N
H6	-	-	42	-	PE11	I/O	FT	PE11		TIM1_CH2
J6	-	-	43	-	PE12	I/O	FT	PE12		TIM1_CH3N
K6	-	-	44	-	PE13	I/O	FT	PE13		TIM1_CH3
G7	-	-	45	-	PE14	I/O	FT	PE14		TIM1_CH4
H7	-	-	46	-	PE15	I/O	FT	PE15		TIM1_BKIN
J7	21	29	47	-	PB10	I/O	FT	PB10	I2C2_SCL/ USART3_TX (6)(7)	TIM2_CH3
K7	22	30	48	-	PB11	I/O	FT	PB11	I2C2_SDA/ USART3_RX (6)(7)	TIM2_CH4
E7	23	31	49	18	V SS_1	S		V SS_1

Table 3. Pin definitions (continued)

Table 3. Pin definitions (continued)

Pins - BGA100	Pins - LQFP48	Pins - LQFP64	Pins - LQFP100	Pins - VFQFPN36	Pin name	Type (1)	(2) - I / O Level	Main (3) - function (after reset)	Alternate functions - Default	Alternate functions - Remap
F7	24	32	50	19	V DD_1	S		V DD_1
K8	25	33	51	-	PB12	I/O	FT	PB12	SPI2_NSS (6) / I2C2_SMBAl (6) / USART3_CK (6)(7) / TIM1_BKIN (7)
J8	26	34	52	-	PB13	I/O	FT	PB13	SPI2_SCK (6) / USART3_CTS (6)(7) TIM1_CH1N (7)
H8	27	35	53	-	PB14	I/O	FT	PB14	SPI2_MISO (6) / USART3_RTS (6)(7) TIM1_CH2N (7)
G8	28	36	54	-	PB15	I/O	FT	PB15	SPI2_MOSI (6) / TIM1_CH3N (7)
K9	-	-	55	-	PD8	I/O	FT	PD8		USART3_TX
J9	-	-	56	-	PD9	I/O	FT	PD9		USART3_RX
H9	-	-	57	-	PD10	I/O	FT	PD10		USART3_CK
G9	-	-	58	-	PD11	I/O	FT	PD11		USART3_CTS
K10	-	-	59	-	PD12	I/O	FT	PD12		TIM4_CH1 / USART3_RTS
J10	-	-	60	-	PD13	I/O	FT	PD13		TIM4_CH2
H10	-	-	61	-	PD14	I/O	FT	PD14		TIM4_CH3
G10	-	-	62	-	PD15	I/O	FT	PD15		TIM4_CH4
F10	-	37	63	-	PC6	I/O	FT	PC6		TIM3_CH1
E10		38	64	-	PC7	I/O	FT	PC7		TIM3_CH2
F9		39	65	-	PC8	I/O	FT	PC8		TIM3_CH3
E9	-	40	66	-	PC9	I/O	FT	PC9		TIM3_CH4
D9	29	41	67	20	PA8	I/O	FT	PA8	USART1_CK/ TIM1_CH1 (7) /MCO
C9	30	42	68	21	PA9	I/O	FT	PA9	USART1_TX (7) / TIM1_CH2 (7)
D10	31	43	69	22	PA10	I/O	FT	PA10	USART1_RX (7) / TIM1_CH3 (7)
C10	32	44	70	23	PA11	I/O	FT	PA11	USART1_CTS/ CANRX (7) / TIM1_CH4 (7) / USBDM

Table 3. Pin definitions (continued)

Table 3. Pin definitions (continued)

Pins - BGA100	Pins - LQFP48	Pins - LQFP64	Pins - LQFP100	Pins - VFQFPN36	Pin name	(1) - Type	(2) - I / O Level	Main function (3) (after reset)	Alternate functions - Default	Alternate functions - Remap
B10	33	45	71	24	PA12	I/O	FT	PA12	USART1_RTS/ CANTX (7) / TIM1_ETR (7) / USBDP
A10	34	46	72	25	PA13/JTMS/SWDIO	I/O	FT	JTMS/SWDIO	PA13
F8	-	-	73	-			Not connected	Not connected	Not connected
E6	35	47	74	26	V SS_2	S		V SS_2
F6	36	48	75	27	V DD_2	S		V DD_2
A9	37	49	76	28	PA14/JTCK/SWCLK	I/O	FT	JTCK/SWCLK	PA14
A8	38	50	77	29	PA15/JTDI	I/O	FT	JTDI	PA15	TIM2_CH1_ETR/ SPI1_NSS
B9	-	51	78		PC10	I/O	FT	PC10		USART3_TX
B8	-	52	79		PC11	I/O	FT	PC11		USART3_RX
C8	-	53	80		PC12	I/O	FT	PC12		USART3_CK
D8	5	5	81	2	PD0	I/O	FT	OSC_IN (8)		CANRX
E8	6	6	82	3	PD1	I/O	FT	OSC_OUT (8)		CANTX
B7		54	83	-	PD2	I/O	FT	PD2	TIM3_ETR
C7	-	-	84	-	PD3	I/O	FT	PD3		USART2_CTS
D7	-	-	85	-	PD4	I/O	FT	PD4		USART2_RTS
B6	-	-	86	-	PD5	I/O	FT	PD5		USART2_TX
C6	-	-	87	-	PD6	I/O	FT	PD6		USART2_RX
D6	-	-	88	-	PD7	I/O	FT	PD7		USART2_CK
A7	39	55	89	30	PB3/JTDO	I/O	FT	JTDO	PB3/TRACESWO	TIM2_CH2 / SPI1_SCK
A6	40	56	90	31	PB4/JNTRST	I/O	FT	JNTRST	PB4	TIM3_CH1 / SPI1_MISO
C5	41	57	91	32	PB5	I/O		PB5	I2C1_SMBAl	TIM3_CH2 / SPI1_MOSI
B5	42	58	92	33	PB6	I/O	FT	PB6	I2C1_SCL (7) / TIM4_CH1 (6)(7)	USART1_TX
A5	43	59	93	34	PB7	I/O	FT	PB7	I2C1_SDA (7) / TIM4_CH2 (6) (7)	USART1_RX
D5	44	60	94	35	BOOT0	I		BOOT0
B4	45	61	95	-	PB8	I/O	FT	PB8	TIM4_CH3 (6) (7)	I2C1_SCL / CANRX

Table 3. Pin definitions (continued)

Table 3. Pin definitions (continued)

Pins - BGA100	Pins - LQFP48	Pins - LQFP64	Pins - LQFP100	Pins - VFQFPN36	Pin name	(1) - Type	(2) - I / O Level	Main function (3) (after reset)	Alternate functions - Default	Alternate functions - Remap
A4	46	62	96	-	PB9	I/O	FT	PB9	TIM4_CH4 (6) (7)	I2C1_SDA / CANTX
D4	-	-	97	-	PE0	I/O	FT	PE0	TIM4_ETR (6)
C4	-	-	98	-	PE1	I/O	FT	PE1
E5	47	63	99	36	V SS_3	S		V SS_3
F5	48	64	100	1	V DD_3	S		V DD_3

1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 8 .
4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
6. Available only on devices with a Flash memory density equal or higher than 64 Kbytes.
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
8. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.

The definition and values of input/output AC characteristics are given in Figure 21 and Table 35 , respectively.

Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 7 .

Table 35. I/O AC characteristics (1)

MODEx[1:0] bit value (1)	Symbol	Parameter	Conditions	Min	Max	Unit
10	f max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 3.6 V		2	MHz
10	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 3.6 V		125 (3)	ns
10	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 3.6 V		125 (3)	ns
01	f max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 3.6 V		10	MHz
01	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 3.6 V		25 (3)	ns
01	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 3.6 V		25 (3)	ns
11	F max(IO)out	Maximum frequency (2)	C L = 30 pF, V DD = 2.7 V to 3.6 V		50	MHz
11	F max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2.7 V to 3.6 V		30	MHz
11	F max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 2.7 V		20	MHz
11	t f(IO)out	Output high to low level fall time	C L = 30 pF, V DD = 2.7 V to 3.6 V		5 (3)	ns
11	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2.7 V to 3.6 V		8 (3)	ns
11	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 2.7 V		12 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 30 pF, V DD = 2.7 V to 3.6 V		5 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2.7 V to 3.6 V		8 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 2.7 V		12 (3)	ns
-	t EXTIpw	Pulse width of external signals detected by the EXTI controller		10		ns

1. The maximum frequency is defined in Figure 21 .
2. Values based on design simulation and validated on silicon, not tested in production.

Figure 21. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics , Table 5: Current characteristics , and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 4. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
V DD -V SS	External main supply voltage (including V DDA and V DD ) (1)	-0.3	4.0	V
V IN	Input voltage on five volt tolerant pin (2)	V SS - 0.3	+5.5	V
V IN	Input voltage on any other pin (2)	V SS - 0.3	V DD +0.3	V
| ∆ V DDx |	Variations between different power pins	50	50	mV
|V SSX - V SS |	Variations between all the different ground pins	50	50	mV
V ESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 5.3.11: Absolute maximum ratings (electrical sensitivity)	see Section 5.3.11: Absolute maximum ratings (electrical sensitivity)

Table 5. Current characteristics

Symbol	Ratings	Max.	Unit
I VDD	Total current into V DD power lines (source) (1)	150	mA
I VSS	Total current out of V SS ground lines (sink) (1)	150	mA
I IO	Output current sunk by any I/O and control pin	25	mA
I IO	Output current source by any I/Os and control pin	- 25	mA
I INJ(PIN) (2)(3)	Injected current on NRST pin	± 5	mA
I INJ(PIN) (2)(3)	Injected current on HSE OSC_IN and LSE OSC_IN pins	± 5	mA
I INJ(PIN) (2)(3)	Injected current on any other pin (4)	± 5	mA
Σ I INJ(PIN) (2)	Total injected current (sum of all I/O and control pins) (4)	± 25	mA

1. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with Σ I INJ(PIN) maximum current injection on four I/O port pins of the device.

Table 6. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature (see Thermal characteristics)	Maximum junction temperature (see Thermal characteristics)	Maximum junction temperature (see Thermal characteristics)

The average chip-junction temperature, T J , in degrees Celsius, may be calculated using the following equation:

$$T_J = T_A + (P_D \times \Theta_{JA})$$

Where:

• T A is the Ambient Temperature in ° C,
• Θ JA is the Package Junction-to-Ambient Thermal Resistance, in ° C/W,
• PD is the sum of P INT and P I/O (P D = P INT + P I/O ),
• PINT is the product of I DD and VDD , expressed in Watts. This is the Chip Internal Power.

PI/O represents the Power Dissipation on Input and Output Pins;

Most of the time for the application P I/O < PINT and can be neglected. On the other hand, P I/O may be significant if the device is configured to drive continuously external modules and/or memories.

An approximate relationship between P D and T J (if P I/O is neglected) is given by:

$$P_D = K / (T_J + 273\ \text{°C})$$

Therefore (solving equations 1 and 2):

$$K = P_D \times (T_A + 273°C) + \Theta_{JA} \times P_D^2$$

where:

K is a constant for the particular part, which may be determined from equation (3) by measuring P D (at equilibrium) for a known T A. Using this value of K, the values of P D and T J may be obtained by solving equations (1) and (2) iteratively for any value of T A .

Table 53. Thermal characteristics

Symbol	Parameter	Value	Unit
Θ JA	Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm/ 0.5 mm pitch	41	°C/W
Θ JA	Thermal resistance junction-ambient LQFP100 - 14 x 14 mm/ 0.5 mm pitch	46	°C/W
Θ JA	Thermal Resistance Junction-Ambient LQFP64 - 10 x 10 mm/ 0.5 mm pitch	45	°C/W
Θ JA	Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch	55	°C/W
Θ JA	Thermal resistance junction-ambient VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch	18	°C/W

Table 53. Thermal characteristics