STM32F103RCT6

Part: STM32F103RCT6 — STMicroelectronics (STM32F103xC/D/E family)

Type: ARM Cortex-M3 32-bit MCU (high-density performance line)

Description: 32-bit ARM Cortex-M3 MCU at up to 72 MHz with 256 to 512 KB Flash and up to 64 KB SRAM, USB 2.0 FS, CAN, 3 ADCs and 2.0–3.6 V supply.

Operating Conditions:

• Supply voltage (VDD): 2.0–3.6 V (VDDA 2.4–3.6 V when ADC is used)
• Operating temperature: -40 to 85 °C (suffix 6 at maximum power dissipation; suffix 7 is -40 to 105 °C)
• Max AHB/APB2 clock: 72 MHz; APB1: 36 MHz
• VBAT backup supply: 1.8–3.6 V

Absolute Maximum Ratings:

• Max supply voltage (VDD–VSS): 4.0 V (min -0.3 V)
• Input voltage on five-volt tolerant pin: VDD + 4.0 V max
• Input voltage on any other pin: 4.0 V max
• Total current into VDD/VDDA: 150 mA; total out of VSS: 150 mA
• Current sunk/sourced by any I/O pin: 25 mA
• Maximum junction temperature: 150 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• VDD: 2.0–3.6 V
• fHCLK: 0–72 MHz
• Junction temperature (suffix 6): -40 to 105 °C
• Power dissipation at TA = 85 °C (suffix 6): 444 mW for LQFP64
• ADC: 3 × 12-bit, 1 μs conversion, up to 21 channels, 0–3.6 V range
• DAC: 2 × 12-bit
• Up to 3 SPIs (18 Mbit/s), up to 2 I2C, up to 5 USARTs

Features:

• Cortex-M3 core, 1.25 DMIPS/MHz, single-cycle multiply and hardware divide
• 256–512 KB Flash, up to 64 KB SRAM
• Flexible static memory controller (FSMC) with 4 chip selects, plus LCD parallel interface
• Up to 11 timers, including 2 motor control PWM timers
• 12-channel DMA
• USB 2.0 full speed, CAN 2.0B, SDIO
• POR, PDR and PVD; internal 8 MHz and 40 kHz RC oscillators; 4–16 MHz crystal oscillator
• Sleep, Stop and Standby low-power modes with VBAT for RTC
• SWD and JTAG debug, Embedded Trace Macrocell
• CRC unit, 96-bit unique ID
• Up to 112 fast I/Os, almost all 5 V tolerant

Applications:

Package:

• LQFP64 (10 × 10 mm) for the RC variant
• Other family packages: LQFP100, LQFP144, LFBGA100, LFBGA144, WLCSP64

• Core: ARM ® 32-bit Cortex ® -M3 CPU
• -72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
• -Single-cycle multiplication and hardware division
• Memories
• -256 to 512 Kbytes of Flash memory
• -up to 64 Kbytes of SRAM
• -Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
• -LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
• -2.0 to 3.6 V application supply and I/Os
• -POR, PDR, and programmable voltage detector (PVD)
• -4-to-16 MHz crystal oscillator
• -Internal 8 MHz factory-trimmed RC
• -Internal 40 kHz RC with calibration
• -32 kHz oscillator for RTC with calibration
• Low power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC and backup registers
• 3 × 12-bit, 1 μs A/D converters (up to 21 channels)
• -Conversion range: 0 to 3.6 V
• -Triple-sample and hold capability
• -Temperature sensor
• 2 × 12-bit D/A converters
• DMA: 12-channel DMA controller
• -Supported peripherals: timers, ADCs, DAC, SDIO, I 2 Ss, SPIs, I 2 Cs and USARTs
• Debug mode
• -Serial wire debug (SWD) & JTAG interfaces
• -Cortex ® -M3 Embedded Trace Macrocell™
• Up to 112 fast I/O ports
• -51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

Figure 3. STM32F103xC/D/E BGA144 ballout

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Figure 4. STM32F103xC/D/E performance line BGA100 ballout

1. The above figure shows the package top view.

Figure 5. STM32F103xC/D/E performance line LQFP144 pinout

1. The above figure shows the package top view.

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Figure 6. STM32F103xC/D/E performance line LQFP100 pinout

Figure 7. STM32F103xC/D/E performance line LQFP64 pinout

1. The above figure shows the package top view.

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Figure 8. STM32F103xC/D/E performance line WLCSP64 ballout, ball side

Table 5. High-density STM32F103xC/D/E pin definitions

Table 5. High-density STM32F103xC/D/E pin definitions

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1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com .
7. In the WCLSP64 package, the PC3 I/O pin is not bonded and it must be configured by software to output mode (Push-pull) and writing 0 to the data register in order to avoid an extra consumption during low-power modes.
8. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The V REF+ functionality is provided instead.
9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com .
10. For the WCLSP64/LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
11. For devices delivered in LQFP64 packages, the FSMC function is not available.

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Table 6. FSMC pin definition

Table 6. FSMC pin definition

Table 6. FSMC pin definition (continued)

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The definition and values of input/output AC characteristics are given in Figure 46 and Table 48 , respectively.

Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 10 .

Table 48. I/O AC characteristics (1)

1. The maximum frequency is defined in Figure 46 .
2. Guaranteed by design.

Figure 46. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics , Table 8: Current characteristics , and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 7. Voltage characteristics

Table 8. Current characteristics

1. Positive injection is not possible on these I/Os. A negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.
2. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.
3. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

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Table 9. Thermal characteristics

The maximum chip junction temperature (T J max) must never exceed the values given in Table 10: General operating conditions on page 44 .

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

$$T_{J\ max} = T_{A\ max} + (P_{D\ max} \times \Theta_{JA})$$

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.