STM32H563AI/G
Arm Cortex-M33 32-bit MCUThe STM32H563AI/G is a arm cortex-m33 32-bit mcu from STMicroelectronics. View the full STM32H563AI/G datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
STM32H563AI/G shares its datasheet with STM32H563RIT6, whose page lists every part number it covers.
Official STM32H563AI/G datasheet (PDF) — the source this page was extracted from.
Manufacturer
STMicroelectronicsCategory
Microcontrollers (MCU)STM32H563AI/G Key Specifications
| Parameter | Value |
|---|---|
| ADC | 2x 12-bit, up to 5 MSPS |
| DAC | 2x 12-bit |
| Core | Arm Cortex-M33 with TrustZone, FPU, MPU |
| I/Os | up to 139 fast I/Os (most 5 V tolerant) |
| SRAM | 640 Kbytes (plus 4 Kbytes backup SRAM) |
| Timers | up to 24 (18x 16-bit, 2x 32-bit) |
| Performance | 375 DMIPS, 1023 CoreMark |
| Power Modes | Sleep, Stop, Standby, VBAT |
| Flash Memory | up to 2 Mbytes with ECC (2 banks) |
| CPU Frequency | up to 250 MHz |
| Supply Voltage | 1.71 V to 3.6 V |
| External Memory | FMC (SRAM/PSRAM/NOR/NAND/SDRAM), Octo-SPI |
| External Oscillators | 4-50 MHz HSE, 32.768 kHz LSE |
| Internal Oscillators | 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI |
| Communication Interfaces | I2C (up to 4), I3C, USART/UART (up to 12), LPUART, SPI/I2S, SAI (2), FD-CAN (2), USB 2.0 FS, Ethernet MAC, SDMMC (2), UCPD |
STM32H563AI/G Overview
Part: STM32H563xx — STMicroelectronics
Type: 32-bit ARM Cortex-M33 MCU
Description: 250 MHz 32-bit ARM Cortex-M33 MCU with TrustZone, FPU, up to 2 MB Flash, 640 KB SRAM, Ethernet MAC, and advanced security and math accelerators.
Operating Conditions:
- Supply voltage: 1.71 to 3.6 V (standard operating voltage, HSLV = 0)
- Operating temperature: -40 to 85 °C (suffix-dependent)
- Maximum CPU/bus clock frequency (fHCLK): up to 250 MHz (VOS0)
Absolute Maximum Ratings:
- Max supply voltage: 4.0 V (VDDx - VSS)
- Max continuous current: 350 mA (Total current into sum of all VDD power lines)
- Max junction/storage temperature: -65 to +150 °C (storage temperature), 130 °C (junction temperature)
Key Specs:
- Maximum CPU core frequency: 250 MHz (at VCORE VOS0, 1.30–1.40 V)
- Flash memory capacity: up to 2 MB with ECC
- SRAM capacity: 640 KB total (including 64 KB SRAM2 with ECC, 320 KB SRAM3 with flexible ECC)
- Analog-to-digital converter: Two 12-bit ADCs up to 5 Msps
- Digital-to-analog converter: One 12-bit DAC with 2 output channels
- I/O pins: up to 140 fast I/Os (most 5 V-tolerant)
- Total current sink: 350 mA max out of sum of all VSS lines
- Output pin current: 20 mA max sunk/sourced by any single I/O pin
Features:
- Arm Cortex-M33 core with TrustZone, MPU, FPU, DSP, achieving 375 DMIPS and 1023 CoreMark
- Mathematical hardware accelerators including CORDIC and FMAC (Filter Math Accelerator)
- ART Accelerator with 8 KB instruction cache and 4 KB data cache
- Rich digital communication interfaces: 4x I2C, 1x I3C, 12x U(S)ART, 1x LPUART, 6x SPI, 2x SAI, 2x FDCAN, 1x Octo-SPI
- Connectivity including USB 2.0 full-speed host/device, USB Type-C / USB-PD r3.1, and 10/100 Ethernet MAC
- Security suite with authenticated debug, life cycle management, HASH engine, TRNG, and ECDSA signature verification
Applications:
- Industrial automation and motor control
- Secure IoT connected devices
- Smart metering and power management systems
- Medical and health monitoring equipment
Package:
- LQFP64
- VFQFPN68
- WLCSP80
- LQFP100
- LQFP144
- UFBGA169
- LQFP176
- UFBGA(176+25)
- TFBGA225
STM32H563AI/G Features
- Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
- MPCBB and TZIC accessible only with secure transactions
- -Enable illegal access events that may trigger a secure interrupt
- Secure and nonsecure access supported for privileged/non-privileged part of TZSC
- Set of registers to define product security settings:
- -Secure/privilege regions for external memories
- -Secure/privilege access mode for securable peripherals
- -Secure/privilege access mode for securable legacy masters
STM32H563AI/G Pin Configuration
Table 13. Legend/abbreviations used in the pinout table
| Name | Name | Abbreviation | Definition |
|---|---|---|---|
| Pin name | Pin name | Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name | Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name |
| S | Supply pin | ||
| Pin type | Pin type | I | Input only pin |
| I/O | Input/output pin | ||
| FT | 5 V-tolerant I/O | ||
| I/O structure | TT RST | Option for TT or | 3.6 V-tolerant I/O FT I/Os (1) |
| Pin functions | _u Alternate functions Functions selected through | I/O, with USB function GPIOx_AFR registers | Bidirectional reset pin with embedded weak pull-up resistor supplied by V DDUSB |
| _a | I/O, with | analog switch function supplied by V DDA | |
| _c | I/O | with USB Type-C power delivery function | |
| _d | I/O with | USB Type-C power delivery dead battery function | |
| _f | I/O, | Fm+ capable | |
| _h | I/O with | high-speed low-voltage mode | |
| _s | I/O supplied only by V | DDIO2 | |
| _t | I/O with tamper function functional in | VBAT mode | |
| Notes | Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset | Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset | Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset |
| Additional functions | Functions directly selected/enabled through peripheral registers | Functions directly selected/enabled through peripheral registers | Functions directly selected/enabled through peripheral registers |
Table 13. Legend/abbreviations used in the pinout table
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| 78/277 | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - LQFP176 SMPS UFBGA176+25 SMPS | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - TFBGA225 SMPS | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - LQFP64 | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - VFQFPN68 | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - LQFP100 | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - LQFP144 | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - UFBGA169 | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - LQFP176 UFBGA176+25 | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin number (1)(2) - name (function after reset) | Table 14. STM32H562xx STM32H563xx pin/ball definition - Pin type - (3)(4) | Table 14. STM32H562xx STM32H563xx pin/ball definition - I/O structure | Table 14. STM32H562xx STM32H563xx pin/ball definition - Notes | Table 14. STM32H562xx STM32H563xx pin/ball definition - Alternate functions | Table 14. STM32H562xx STM32H563xx pin/ball definition - Additional functions | Table 14. STM32H562xx STM32H563xx pin/ball definition |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | 1 | 1 C3 | 1 | D4 B3 | - | - | 1 | 1 A1 | 1 A2 | PE2 | I/O | FT_h | - | TRACECLK, LPTIM1_IN2, SAI1_CK1, SPI4_SCK, SAI1_MCLK_A, USART10_RX, UART8_TX, OCTOSPI1_IO2, ETH_MII_TXD3, FMC_A23, DCMI_D3/PSSI_D3, EVENTOUT | - | ||||
| - | 2 | 2 | D4 | 2 | B2 D5 | - | - | 2 | 2 | B2 | 2 A1 | PE3 | I/O | FT_h | - | TRACED0, TIM15_BKIN, SAI1_SD_B, USART10_TX, FMC_A19, EVENTOUT | TAMP_IN6/TAMP_OUT3 | ||
| - | 3 | 3 | D3 | 3 | C3 C4 | - | - | 3 | 3 | D4 | 3 B1 | PE4 | I/O | FT_h | - | TRACED1, SAI1_D2, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4/PSSI_D4, EVENTOUT | TAMP_IN7/TAMP_OUT8 | ||
| - | 4 | 4 | C2 | 4 | D3 D4 | - - | 4 | 4 | C2 | 4 B2 | PE5 | I/O | FT_h | - | TRACED2, SAI1_CK2, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6/PSSI_D6, EVENTOUT | TAMP_IN8/TAMP_OUT7 | |||
| - | 5 | 5 | D2 | 5 | C2 F6 | - | - | 5 | 5 D3 | 5 B3 | PE6 | I/O | FT_h | - | TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCLK_B, FMC_A22, DCMI_D7/PSSI_D7, EVENTOUT | TAMP_IN3/TAMP_OUT6 | |||
| A1 | - | - | - | - | - F7 | - | - | - | - - | - - | VDD | S | - | - | - | - | |||
| B8 | - | - | - | - | - A1 | - | - | - | - | - | - - | VSS | S | - | - | - | - | ||
| B10 | 6 | 6 | C1 | 6 | B1 D3 | 1 | 1 | 6 | 6 E2 | 6 C1 | VBAT | S | - | - | - | - | |||
| D2 | - | - | - | - | - E3 | - | - | - | - - | - - | VSS | S | - | - | - | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| Pin number (1)(2) |
|---|
| 80/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 80/277 | WLCSP80 SMPS | LQFP100 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP176 SMPS | UFBGA176+25 SMPS TFBGA225 SMPS | LQFP64 | VFQFPN68 | LQFP100 | LQFP144 | UFBGA169 | Pin name (function after reset) LQFP176 UFBGA176+25 | (3)(4) Pin type | I/O structure | Notes | Alternate functions | Additional functions | ||
| 80/277 | - | - | 12 F4 | 18 | G3 F2 | - | - | - | 12 F2 | 18 H2 | PF2 | I/O | FT_h | - | LPTIM3_CH2, LPTIM3_IN2, I2C2_SMBA, UART12_TX, USART11_CK, FMC_A2, LPTIM5_IN1, EVENTOUT | - | |||
| 80/277 | - | - | 13 | G6 | 19 | G2 | H5 | - | - | - | 13 F5 | 19 J2 | PF3 | I/O | FT_h | - | LPTIM3_IN1, USART11_TX, FMC_A3, LPTIM5_IN2, EVENTOUT | - | |
| 80/277 | - | - | 14 | G5 | 20 | G1 G1 | - | - | - | 14 F1 | 20 J3 | PF4 | I/O | FT_h | - | LPTIM3_ETR, USART11_RX, FMC_A4, EVENTOUT | - | ||
| 80/277 | - | - | 15 | G3 | 21 | H3 | H4 | - | - - | 15 | F6 | 21 K3 | PF5 | I/O | FT_fh | - | LPTIM3_CH1, I2C4_SCL, I3C1_SCL, UART12_RX, USART11_CTS/USART11_NSS, FMC_A5, LPTIM3_IN1, EVENTOUT | - | |
| 80/277 | H2 | 10 | 16 | F2 | 22 | G4 | - | - | - | 10 | 16 G2 | 22 F2 | VSS | S | - | - | - | - | |
| 80/277 | A7 | 11 | 17 | G1 | 23 | E4 | - | - | - | 11 | 17 G1 | 23 F3 | VDD | S | - | - | - | - | |
| 80/277 | - | - | 18 | G7 | 24 | H1 | H3 | - | - | - | 18 G4 | 24 K2 | PF6 | I/O | FT_h | - | TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, OCTOSPI1_IO3, LPTIM5_CH1, EVENTOUT | - | |
| 80/277 | - | - | 19 | F1 | 25 | K2 | H2 | - | - - | 19 | G3 | 25 K1 | PF7 | I/O | FT_h | - | TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, OCTOSPI1_IO2, LPTIM5_CH2, EVENTOUT | - | |
| - | - | 20 | G4 | 26 | H2 H1 | - | - | - | 20 G5 | 26 L3 | PF8 | I/O | FT_h | - | TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE, TIM13_CH1, OCTOSPI1_IO0, LPTIM5_IN1, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| Pin number (1)(2) - WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 SMPS | Pin number (1)(2) - UFBGA169 SMPS | Pin number (1)(2) - LQFP176 SMPS UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - LQFP176 UFBGA176+25 | Pin number (1)(2) - Pin name (function after reset) (3)(4) | Pin number (1)(2) - Pin type | I/O structure Notes | Alternate functions | Additional functions | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | - 21 | G2 | 27 | J3 | J4 | - | - | - | 21 H3 | 27 L2 | PF9 | I/O | FT_h | - | TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, OCTOSPI1_IO1, LPTIM5_IN2, EVENTOUT | - | |
| - | - | 22 | H4 | - J4 | K1 | - | - | - | 22 G6 | 28 L1 | PF10 | I/O | FT_h | - | TIM16_BKIN, SAI1_D3, PSSI_D15, OCTOSPI1_CLK, DCMI_D11/PSSI_D11, EVENTOUT | - | |
| K10 | 12 | 23 | H1 | 28 J1 | J1 | 5 | 5 | 12 | 23 | H1 | 29 G1 | PH0- OSC_IN(PH0) | I/O | FT | - | EVENTOUT | OSC_IN |
| J9 | 13 | 24 | J1 | 29 J2 | J2 | 6 | 6 | 13 | 24 | H2 | 30 H1 | PH1- OSC_OUT(PH1) | I/O | FT | - | EVENTOUT | OSC_OUT |
| F8 | 14 | 25 | H3 | 30 K3 | J5 | 7 | 7 | 14 | 25 | H4 | 31 J1 | NRST | I/O | RST | - | - | - |
| H8 | 15 | 26 | J2 | 31 L1 | L1 | 8 | 8 | 15 | 26 J1 | 32 M2 | PC0 | I/O | FT_a | - | TIM16_BKIN, SAI1_MCLK_A, SPI2_RDY, SAI2_FS_B, FMC_A25, OCTOSPI1_IO7, FMC_SDNWE, EVENTOUT | ADC12_INP10 | |
| G7 | 16 | 27 | J3 | 32 L2 | K2 | 9 | 9 | 16 | 27 J2 | 33 M3 | PC1 | I/O | FT_ah | - | TRACED0, SAI1_D1, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, USART11_RTS/USART11_DE, SAI2_SD_A, SDMMC2_CK, OCTOSPI1_IO4, ETH_MDC, EVENTOUT | ADC12_INP11, ADC12_INN10, TAMP_IN3/TAMP_OUT5, WKUP6 | |
| M10 | 17 | 28 | K1 | 33 K4 | M1 | 10 | 10 | 17 | 28 | J3 | 34 M4 | PC2 | I/O | FT_a | - | PWR_CSLEEP, TIM17_CH1, TIM4_CH4,SPI2_MISO/I2S2_SDI, OCTOSPI1_IO5, OCTOSPI1_IO2, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT | ADC12_INP12, ADC12_INN11 |
| 82/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 SMPS TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 LQFP176 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin name (function after reset) (3)(4) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin type | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - I/O structure Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 82/277 | L9 | 18 | 29 K2 | 34 | N3 | M2 | 11 | 11 | 18 | 29 | H5 | 35 M5 | PC3 | I/O | FT_a | - | PWR_CSTOP, SAI1_D3, LPTIM3_CH1, SPI2_MOSI/I2S2_SDO, OCTOSPI1_IO6, OCTOSPI1_IO0, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT | ADC12_INP13, ADC12_INN12 | |
| 82/277 | G1 | - | - | - | 35 | H4 G10 | - | - | - | 30 | M1 36 | G3 | VDD | S | - | - | - | - | |
| 82/277 | P2 | - | - | H2 | - | K1 H6 | - | - | - | - | M2 - | G2 | VSS | S | - | - | - | - | |
| 82/277 | N9 | 19 | 30 | L1 | 36 | M2 K3 | 12 | 12 | 19 | 31 | K2 37 | M1 | VSSA | S | - | - | - | - | |
| 82/277 | - | - | - | L2 | - | N2 K4 | - | - | 20 | - | K1 - | N1 | VREF- | S | - | - | - | - | |
| 82/277 | - | 20 | 31 | M2 | 37 | N1 K5 | - | - | 21 | 32 | L2 38 | P1 | VREF+ | S | - | - | - | - | |
| 82/277 | P10 | 21 | 32 | M1 | 38 | M1 L3 | 13 | 13 22 | 33 | L1 39 | R1 | VDDA | S | - | - | - | - | ||
| K8 | 22 | 33 | K3 | 39 | P2 L2 | 14 | 14 23 | 34 | J4 | 40 | N3 | PA0 | I/O | FT_at | (5) | TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SPI6_NSS, SPI3_RDY, USART2_CTS/USART2_NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH_MII_CRS, TIM2_ETR, EVENTOUT | ADC12_INP0,ADC12_INN1, TAMP_IN2/TAMP_OUT1, WKUP1 | ||
| J7 | 23 | 34 | H5 | 40 | L3 L4 | 15 | 15 | 24 | 35 | J5 | 41 N2 | PA1 | I/O | FT_aht | (5) | TIM2_CH2, TIM5_CH2, TIM15_CH1N, LPTIM1_IN1, OCTOSPI1_DQS, USART2_RTS/USART2_DE, UART4_RX, OCTOSPI1_IO3, SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_RMII_RE F_CLK, EVENTOUT | ADC12_INP1, TAMP_IN5/TAMP_OUT4 |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| WLCSP80 SMPS | LQFP100 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP176 SMPS UFBGA176+25 SMPS | TFBGA225 SMPS | LQFP64 | VFQFPN68 | LQFP144 UFBGA169 | LQFP176 UFBGA176+25 | Pin name (function after reset) (3)(4) | Pin type | I/O structure Notes | Alternate functions | Additional functions | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| M8 | 24 | 35 | L3 | 41 | M3 | M3 | 16 | 16 | 36 L3 | 42 P2 | PA2 | I/O | FT_hat | (5) | TIM2_CH3, TIM5_CH3, TIM15_CH1, LPTIM1_IN2, USART2_TX, SAI2_SCK_B, ETH_MDIO, EVENTOUT | ADC12_INP14, TAMP_IN4/TAMP_OUT3, WKUP2 |
| - | - | - | J4 | 42 R2 | N1 | - | - | - K3 | 43 F4 | PH2 | I/O | FT_h | - | LPTIM1_IN2, OCTOSPI1_IO4, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, EVENTOUT | - | |
| H10 | - | - | - | - L4 | J6 | - | - | - - | - K4 | VDD | S | - | - | - | - | |
| DS14258 P8 | - | - | - | - M4 | - | - | - | - - | - L4 | VSS | S | - | - | - | - | |
| Rev 6 - | - | - | N2 | 43 P3 | N2 | - | - | - N2 | 44 G4 | PH3 | I/O | FT_h | - | OCTOSPI1_IO5, SAI2_MCLK_B, ETH_MII_COL, FMC_SDNE0, EVENTOUT | - | |
| - | - | - | N1 | - R1 | P1 | - | - | - N1 | 45 H4 | PH4 | I/O | FT_fa | - | I2C2_SCL, SPI5_RDY, SPI6_RDY, PSSI_D14, EVENTOUT | - | |
| - | - | - | L4 | - P1 | K6 | - | - | - M3 | 46 J4 | PH5 | I/O | FT_fa | - | I2C2_SDA, SPI5_NSS, SPI6_RDY, FMC_SDNWE, EVENTOUT | - | |
| T10 | 25 | 36 | K4 | 44 N5 | M4 | 17 | 17 | 37 N3 | 47 R2 | PA3 | I/O | FT_ah | - | TIM2_CH4, TIM5_CH4, OCTOSPI1_CLK, TIM15_CH2, SPI2_NSS/I2S2_WS,SAI1_SD_B, USART2_RX, ETH_MII_COL, EVENTOUT | ADC12_INP15 | |
| - | 26 | 37 | M3 | 45 M7 | - | 18 | 18 | 38 M4 | 48 M8 | VSS | S | - | - | - | - | |
| R1 | 27 | 38 | N3 | 46 M6 | - | 19 | 19 | 39 N4 | 49 N8 | VDD | S | - | - | - | - |
| 84/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 SMPS TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin name (function after reset) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin type | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - (3)(4) I/O structure | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84/277 | R9 | 28 | 39 M4 | 47 | M5 | N3 | 20 | 20 | 29 | 40 | L4 | 50 N4 | PA4 | I/O | TT_a | - | TIM5_ETR, LPTIM2_CH1, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, DCMI_HSYNC/PSSI_DE, EVENTOUT | ADC12_INP18, DAC1_OUT1 | |
| 84/277 | L7 | 29 | 40 | J5 | 48 | R3 P2 | 21 | 21 | 30 | 41 | K4 | 51 P4 | PA5 | I/O | TT_ah | - | TIM2_CH1, TIM8_CH1N, SPI1_SCK/I2S1_CK, SPI6_SCK, ETH_MII_TX_EN/ETH_RMII_TX_ EN, PSSI_D14, TIM2_ETR, EVENTOUT | ADC12_INP19, ADC12_INN18, DAC1_OUT2 | |
| 84/277 | H6 | 30 | 41 | N4 | 49 | P5 R2 | 22 | 22 | 31 | 42 | M5 | 52 P3 | PA6 | I/O | FT_ah | - | TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, OCTOSPI1_IO3, USART11_TX, SPI6_MISO, TIM13_CH1, DCMI_PIXCLK/PSSI_PDCK, EVENTOUT | ADC12_INP3 | |
| 84/277 | K6 | 31 | 42 | K5 | 50 | R4 P3 | 23 | 23 | 32 | 43 | K5 | 53 R3 | PA7 | I/O | FT_ah | - | TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, USART11_RX, SPI6_MOSI, TIM14_CH1, OCTOSPI1_IO2, ETH_MII_RX_DV/ETH_RMII_CRS _DV, FMC_SDNWE, FMC_NWE, EVENTOUT | ADC12_INP7, ADC12_INN3 | |
| M6 | - | - | L5 | 51 | N4 N4 | 24 | 24 | 33 | 44 | N5 | 54 N5 | PC4 | I/O | FT_a | - | TIM2_CH4, SAI1_CK1, LPTIM2_ETR, I2S1_MCK, USART3_RX, ETH_MII_RXD0/ETH_RMII_RXD0 , FMC_SDNE0, EVENTOUT | ADC12_INP4 |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| Pin number (1)(2) |
|---|
| Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WLCSP80 SMPS | LQFP100 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP176 SMPS | UFBGA176+25 SMPS TFBGA225 SMPS | LQFP64 | VFQFPN68 | LQFP100 | LQFP144 | UFBGA169 | LQFP176 UFBGA176+25 | Pin name (function after reset) (3)(4) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | |
| - | - | 48 | M7 | 58 | - J3 | - | - | - | 51 M7 | 61 - | VSS | S | - | - | - | - | ||
| - | - | 49 | N7 | 59 | - K7 | - | - | - | 52 N7 | 62 | N9 | VDD | S | - | - | - | - | |
| - | - | 50 | H7 | 60 | P7 R6 | - | - | - | 53 H7 | 63 | N6 | PF13 | I/O | FT_ah | - | I2C4_SMBA, FMC_A7, LPTIM6_IN1, EVENTOUT | ADC2_INP2 | |
| - | - | 51 | L6 | 61 | R7 M7 | - | - | - | 54 M6 | 64 | R7 | PF14 | I/O | FT_fah | - | FMC_A8, LPTIM6_IN2, EVENTOUT | ADC2_INP6, ADC2_INN2 | |
| - | - | 52 | J7 | 62 | N8 | N7 | - | - | - | 55 J7 | 65 | P7 | PF15 | I/O | FT_fh | - | I2C4_SDA, I3C1_SDA, FMC_A9, EVENTOUT | - |
| - | - | 53 | M6 | 63 | R8 | P7 | - | - | - | 56 L7 | 66 | N7 | PG0 | I/O | FT_h | - | UART9_RX, FMC_A10, LPTIM4_IN1, EVENTOUT | - |
| - | - | - | - | - | - | K9 | - | - | - - | - | - | - | VDD | S | - | - | - | - |
| - | - | 54 | K7 | 64 | P8 | R7 | - | - - | 57 | K7 | 67 | M7 | PG1 | I/O | FT_h | - | SPI2_MOSI/I2S2_SDO, UART9_TX, FMC_A11, EVENTOUT | - |
| T6 | 35 | 55 | L7 | 65 | R9 L8 | - | - | 38 | 58 N8 | 68 R8 | PE7 | I/O | FT_h | - | TIM1_ETR, UART12_RTS/UART12_DE, UART7_RX, OCTOSPI1_IO4, FMC_D4/FMC_AD4, EVENTOUT | - | ||
| N5 | 36 | 56 | J8 | 66 | P9 | M8 | - | - | 39 59 | G7 | 69 | P8 | PE8 | I/O | FT_h | - | TIM1_CH1N, UART12_CTS/UART12_NSS, UART7_TX, OCTOSPI1_IO5, FMC_D5/FMC_AD5, EVENTOUT | - |
| R5 | 37 | 57 | N8 | 67 | N9 N8 | - | - | 40 | 60 L8 | 70 | P9 | PE9 | I/O | FT_h | - | TIM1_CH1, UART12_RX, UART7_RTS/UART7_DE, OCTOSPI1_IO6, FMC_D6/FMC_AD6, EVENTOUT | - | |
| - | - | 58 | - | 68 | - K8 | - - | - | 61 - | 71 - | VSS | S | - | - | - | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
DS14258 Rev 6
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - SMPS | Pin number (1)(2) - UFBGA169 SMPS LQFP176 SMPS | Pin number (1)(2) - UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 LQFP176 | Pin number (1)(2) - UFBGA176+25 | Pin number (1)(2) - Pin reset) (3)(4) | name (function after type - Pin | I/O structure | Notes | Alternate functions | Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | - | 59 | - | 69 - | - | - | - | - | 62 | - 72 | - | VDD | S | - | - | - | - | |
| M4 | 38 | 60 | L8 | 70 | R10 | M9 | - | - | 41 | 63 | H8 73 | R9 | PE10 | I/O | FT_h | - | TIM1_CH2N, UART12_TX, UART7_CTS, OCTOSPI1_IO7, FMC_D7/FMC_AD7, EVENTOUT | - |
| - | 39 | 61 | M8 | 71 | P10 | R10 | - | - | 42 | 64 | M8 74 | P10 | PE11 | I/O | FT_h | - | TIM1_CH2, SPI1_RDY, SPI4_NSS, OCTOSPI1_NCS, SAI2_SD_B, FMC_D8/FMC_AD8, EVENTOUT | - |
| - | 40 | 62 | M9 72 | R11 | L9 | - | - | 43 | 65 | K8 75 | R10 | PE12 | I/O | FT_h | - | TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_AD9, EVENTOUT | - | |
| - | 41 | 63 | K8 | 73 | P11 | P10 | - | - | 44 | 66 | L9 76 | N11 | PE13 | I/O | FT_h | - | TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_AD10, EVENTOUT | - |
| - | 42 | 64 | J9 | 74 | N10 | N10 | - | - | 45 | 67 | J8 77 | P11 | PE14 | I/O | FT_h | - | TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11/FMC_AD11, EVENTOUT | - |
| - | 43 | 65 | L9 | 75 | N11 | R11 | - | - | 46 | 68 | N9 78 | R11 | PE15 | I/O | FT_h | - | TIM1_BKIN, TIM1_CH4N, USART10_CK, FMC_D12/FMC_AD12, EVENTOUT | - |
| P4 | 44 | 66 | K9 76 | M10 | M10 | 29 | 29 | 47 | 69 | K9 79 | R12 | PB10 | I/O | FT_f | - | TIM2_CH3, LPTIM3_CH1, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OCTOSPI1_NCS, ETH_MII_RX_ER, EVENTOUT | - |
| 88/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP176 SMPS UFBGA176+25 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - number LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - (1)(2) VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169 LQFP176 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin name (function after reset) (3)(4) UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin type | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - I/O structure | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Additional functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | 45 | 67 L10 | 77 | N12 | P11 | - | 30 | - | - | M9 80 | R13 | PB11 | I/O | FT_f | - | TIM2_CH4, LPTIM2_ETR, I2C2_SDA,SPI2_RDY,SPI4_RDY, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_ EN, FMC_NBL1, EVENTOUT | - | ||
| T4 | 46 | 68 | N9 | 78 | R12 R12 | - | - | - | - | - - | - | VLXSMPS | S | - | - | - | - | ||
| R3 | 47 | 69 | N10 | 79 | R13 R13 | - | - | - | - | - - | - | VDDSMPS | S | - | - | - | - | ||
| DS14258 | N3 | 48 | 70 | M10 | 80 | P12 P12 | - | - | - | - | - - | - | VSSSMPS | S | - | - | - | - | |
| T2 | 49 | 71 | N11 | 81 | R14 L10 | 30 | 31 | 48 | 70 | N10 81 | M10 | VCAP | S | - | - | - | - | ||
| Rev | - | 50 | 72 | M11 | 82 | M9 L5 | 31 | 32 | 49 | 71 | M12 82 | M9 | VSS | S | - | - | - | - | |
| - | 51 | 73 | N12 | 83 | M11 - | 32 | 33 | 50 | 72 | N11 83 | N10 | VDD | S | - | - | - | - | ||
| - | - | - | N13 | 84 | P13 N11 | - | - | - | - | K10 | 84 M11 | PH6 | I/O | FT | - | TIM1_CH3N, TIM12_CH1, TIM8_CH1, I2C2_SMBA, SPI5_SCK, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8/PSSI_D8, EVENTOUT | - | ||
| - | - | - | L11 | 85 | P14 M11 | - | - | - | - | L10 85 | N12 | PH7 | I/O | FT_f | - | TIM1_CH3, TIM8_CH1N, I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9/PSSI_D9, EVENTOUT | - | ||
| - | - | - | M12 | - | N13 N12 | - | - | - | - | M10 86 | M12 | PH8 | I/O | FT_fh | - | TIM1_CH2N, TIM5_ETR, TIM8_CH2, I2C3_SDA, SPI5_MOSI, DCMI_HSYNC/PSSI_DE, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| Pin number (1)(2) - WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS LQFP144 SMPS | Pin number (1)(2) | Pin number (1)(2) - UFBGA169 SMPS | Pin number (1)(2) - LQFP176 SMPS UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 LQFP144 | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - LQFP176 | Pin number (1)(2) - UFBGA176+25 | Pin number (1)(2) - Pin name (function after reset) (3)(4) | Pin number (1)(2) - Pin type | I/O structure Notes | Alternate functions | Additional functions | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | - - | M13 | 86 | M12 | P13 | - | - | - | - - | 87 | M13 | PH9 | I/O | FT_h | - | TIM1_CH2, TIM12_CH2, TIM8_CH2N, I2C3_SMBA, SPI5_NSS, DCMI_D0/PSSI_D0, EVENTOUT | - |
| - | - | - | K10 | 87 N14 | K10 | - | - | - - | M11 | 88 | L13 | PH10 | I/O | FT_h | - | TIM1_CH1N, TIM5_CH1, TIM8_CH3, I2C4_SMBA, SPI5_RDY, DCMI_D1/PSSI_D1, EVENTOUT | - |
| - | - | - | L13 | 88 P15 | M12 | - | - | - - | N12 | 89 L12 | PH11 | I/O | FT_fh | - | TIM1_CH1, TIM5_CH2, TIM8_CH3N, I2C4_SCL, I3C1_SCL, DCMI_D2/PSSI_D2, EVENTOUT | - | |
| - | - | - | L12 | 89 M13 | R14 | - | - | - - | N13 | 90 K12 | PH12 | I/O | FT_fh | - | TIM1_BKIN, TIM5_CH3, TIM8_BKIN, I2C4_SDA, I3C1_SDA, TIM8_CH4N, DCMI_D3/PSSI_D3, EVENTOUT | - | |
| - | - | - | - | 90 H12 | R15 | - | - | - - | - | - | - | VSS | S | - | - | - | - |
| - | - | - | - | 91 J12 | - | - | - | - | - L13 | 91 | J12 | VDD | S | - | - | - | - |
| L3 | - | - | K11 | 92 L12 | P14 | 33 | 34 | 51 | 73 K11 | 92 | P12 | PB12 | I/O | FT_fh | - | TIM1_BKIN, OCTOSPI1_NCLK, I2C2_SDA, SPI2_NSS/I2S2_WS, UCPD1_FRSTX, USART3_CK, FDCAN2_RX, ETH_MII_TXD0/ETH_RMII_TXD0, UART5_RX, EVENTOUT | - |
| 90/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 SMPS TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin name (function after reset) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - (3)(4) Pin type I/O structure Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 90/277 | M2 | 52 | 74 K12 | 93 | R15 | N13 | 34 | 35 | 52 | 74 | L11 | 93 P13 | PB13 | I/O | FT_c | (6) | TIM1_CH1N, LPTIM3_IN1, LPTIM2_CH1, I2C2_SMBA, SPI2_SCK/I2S2_CK, USART3_CTS/USART3_NSS, FDCAN2_TX, SDMMC1_D0, UART5_TX, EVENTOUT | UCPD1_CC1 | |
| 90/277 | N1 | 53 | 75 | J10 | 94 | N15 K11 | 35 | 36 | 53 | 75 | M13 | 94 | R14 | PB14 | I/O | FT_c | (6) | TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS/USART3_DE, UART4_RTS/UART4_DE, SDMMC2_D0, LPTIM3_ETR, EVENTOUT | UCPD1_CC2 |
| 90/277 | L1 | 54 | 76 | H10 | 95 | M14 M13 | 36 | 37 54 | 76 | J10 | 95 R15 | PB15 | I/O | FT_h | - | RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, USART11_CTS/USART11_NSS, UART4_CTS, SDMMC2_D1, OCTOSPI1_CLK, ETH_MII_TXD1/ETH_RMII_TXD1, DCMI_D2/PSSI_D2, UART5_RX, EVENTOUT | PVD_IN | ||
| 90/277 | - | 55 | 77 | J11 | 96 | M15 L12 | - | - | 55 | 77 | L12 | 96 P15 | PD8 | I/O | FT_h | - | USART3_TX, FMC_D13/FMC_AD13, EVENTOUT | - | |
| - | - | - | - | - | G12 - | - | - | - | - | - | - - | VSS | S | - | - | - | - | ||
| - | 56 | 78 | H9 | 97 | L13 P15 | - | - 56 | 78 | J9 | 97 | P14 | PD9 | I/O | FT_h | - | USART3_RX, FDCAN2_RX, FMC_D14/FMC_AD14, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
DS14258 Rev 6
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 SMPS | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - SMPS LQFP176 SMPS | Pin number (1)(2) - UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - LQFP176 UFBGA176+25 | Pin name (function after - reset) (3)(4) | Pin type | I/O structure Notes | Alternate functions | Additional functions | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | 57 | 79 | K13 | 98 | K12 | N14 | - | - | 57 | 79 | J11 98 | N15 | PD10 | I/O | FT_h | - | LPTIM2_CH2, USART3_CK, FMC_D15/FMC_AD15, EVENTOUT | - |
| - | 58 | 80 | H8 | 99 | L14 | N15 | - | 38 | 58 | 80 | H10 99 | N14 | PD11 | I/O | FT_h | - | SAI1_CK1, LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART3_NSS, UART4_RX, OCTOSPI1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT | - |
| - | 59 | 81 | H11 | 100 | K14 | M14 | - | 39 | 59 | 81 | K12 100 | N13 | PD12 | I/O | FT_fh | - | LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, I3C1_SCL, SAI1_D1, USART3_RTS/USART3_DE, UART4_TX, OCTOSPI1_IO1, SAI2_FS_A,FMC_A17/FMC_ALE, DCMI_D12/PSSI_D12, EVENTOUT | - |
| - | 60 | 82 | G8 | 101 | L15 | L13 | - | - | 60 | 82 | K13 101 | M15 | PD13 | I/O | FT_fh | - | LPTIM1_CH1, TIM4_CH2, LPTIM2_CH1, I2C4_SDA, I3C1_SDA, OCTOSPI1_IO3, SAI2_SCK_A, UART9_RTS/UART9_DE, FMC_A18, DCMI_D13/PSSI_D13, LPTIM4_IN1, EVENTOUT | - |
| - | - | 83 | J12 102 | - | - | - | - | - | 83 | H12 102 | H12 | VSS | S | - | - | - | - | |
| - | - | 84 | J13 103 | - | - | - | - | - | 84 | H13 103 | J13 | VDD | S | - | - | - | - | |
| K2 | 61 | 85 | H12 104 | K13 | J11 | - | - | 61 | 85 | H11 104 | M14 | PD14 | I/O | FT_h | - | TIM4_CH3, UART8_CTS, UART9_RX, FMC_D0/FMC_AD0, EVENTOUT | - |
| 92/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 SMPS TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin after reset) LQFP176 UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - name (function (3)(4) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin type | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - I/O structure Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 92/277 | J1 | 62 86 | G10 | 105 | J13 K12 | - | - | 62 | 86 H9 | 105 L14 | PD15 | I/O | FT_h | - | TIM4_CH4, UART8_RTS/UART8_DE, UART9_TX, FMC_D1/FMC_AD1, EVENTOUT | - | |||
| 92/277 | - | - | - | - | - | - - | - | - | - | - - | - - | VDD | S | - | - | - | - | ||
| 92/277 | - | - | - | - | - | - | - | - | - | - | - - | - - | VSS | S | - | - | - | - | |
| 92/277 | - | - | 87 | H13 | 106 | K15 | L15 | - | - - | 87 | J12 | 106 L15 | PG2 | I/O | FT_h | - | TIM8_BKIN, UART12_RX, FMC_A12, LPTIM6_ETR, EVENTOUT | - | |
| 92/277 | - | - | 88 | G9 | 107 | H14 | J12 | - | - - | 88 | G9 | 107 K15 | PG3 | I/O | FT_h | - | TIM8_BKIN2, UART12_TX, FMC_A13, LPTIM5_ETR, EVENTOUT | - | |
| 92/277 | - | - | 89 | G11 | 108 | J15 | K14 | - | - | - | 89 J13 | 108 K14 | PG4 | I/O | FT_h | - | TIM1_BKIN2, FMC_A14/FMC_BA0, LPTIM4_ETR, EVENTOUT | - | |
| 92/277 | - | - 90 | F8 | 109 | H15 | K15 | - | - - | 90 | G10 | 109 K13 | PG5 | I/O | FT_h | - | TIM1_ETR, FMC_A15/FMC_BA1, EVENTOUT | - | ||
| 92/277 | - | - | 91 | G12 | 110 | J14 | J13 | - | - - | 91 | G11 | 110 J15 | PG6 | I/O | FT_fh | - | TIM17_BKIN, I3C1_SDA, I2C4_SDA, SPI1_RDY, OCTOSPI1_NCS, UCPD1_FRSTX, FMC_NE3, DCMI_D12/PSSI_D12, EVENTOUT | - | |
| - | - | 92 | F9 | 111 | H13 H11 | - | - | - | 92 G8 | 111 J14 | PG7 | I/O | FT_fh | - | SAI1_CK2, I3C1_SCL, I2C4_SCL, SAI1_MCLK_A, USART6_CK, UCPD1_FRSTX, FMC_INT, DCMI_D13/PSSI_D13, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
DS14258 Rev 6
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 SMPS UFBGA169 | Pin number (1)(2) - SMPS LQFP176 SMPS | Pin number (1)(2) - UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 LQFP176 | Pin number (1)(2) - UFBGA176+25 | Pin number (1)(2) - Pin name (function after reset) (3)(4) | Pin number (1)(2) - Pin type | I/O structure | Notes | Alternate functions | Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | - | 93 G13 | 112 G15 | J14 | - | - | - | 93 | F11 112 | H14 | PG8 | I/O | FT_h | - | TIM8_ETR, SPI6_NSS, USART6_RTS/USART6_DE, ETH_PPS_OUT, FMC_SDCLK, EVENTOUT | - | |
| - | - | 94 - | 113 | - | - | - | - | - | 94 | - 113 | - | VSS | S | - | - | - | - |
| - | - | 95 | - 114 | - | - | - | - | - | 95 | - 114 | - | VDD | S | - | - | - | - |
| J3 | 63 | 96 | F10 115 | G14 | J15 | 37 | 40 | 63 | 96 | F9 115 | H15 | PC6 | I/O | FT_h | - | TIM3_CH1, TIM8_CH1, I2S2_MCK, SAI1_SCK_A, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, OCTOSPI1_IO5, SDMMC1_D6, DCMI_D0/PSSI_D0, EVENTOUT | - |
| K4 | 64 | 97 | F11 116 | G13 | H14 | 38 | 41 | 64 | 97 | F10 116 | G15 | PC7 | I/O | FT_h | - | TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, OCTOSPI1_IO6, SDMMC1_D7, DCMI_D1/PSSI_D1, EVENTOUT | - |
| J5 | 65 | 98 | E9 117 | F14 | H13 | 39 | 42 | 65 | 98 | G12 117 | G14 | PC8 | I/O | FT_h | - | TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS/UART5_DE, FMC_NE2/FMC_NCE, FMC_INT, FMC_ALE, SDMMC1_D0, DCMI_D2/PSSI_D2, EVENTOUT | - |
| F2 | 66 | 99 | F12 118 | F13 | G14 | 40 | 43 | 66 | 99 | G13 118 | F14 | PC9 | I/O | FT_fh | - | MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK, UART5_CTS, OCTOSPI1_IO0, FMC_CLE, SDMMC1_D1, DCMI_D3/PSSI_D3, EVENTOUT | UCPD1_DB2 |
| 94/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS UFBGA176+25 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin after reset) LQFP176 UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - name (function (3)(4) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin type | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - I/O structure Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 94/277 | - | - | - | - - | - - | - | - - | - | - | - G12 | VSS | S | - | - | - | - | |||
| 94/277 | - | - | - | - | - | - - | - | - | - | - - | - G13 | VDD | S | - | - | - | - | ||
| 94/277 | G3 | 67 | 100 | E10 | 119 | F15 G11 | 41 | 44 | 67 | 100 F12 | 119 F15 | PA8 | I/O | FT_fh | - | MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, SPI1_RDY, USART1_CK, USB_SOF, UART7_RX, FMC_NOE, DCMI_D3/PSSI_D3, EVENTOUT | - | ||
| 94/277 | H4 | 68 | 101 | F13 | 120 | E15 G13 | 42 | 45 | 68 101 | E11 | 120 E15 | PA9 | I/O | FT_d | - | TIM1_CH2, LPUART1_TX, I2C3_SMBA,SPI2_SCK/I2S2_CK, USART1_TX, ETH_MII_TX_ER, FMC_NWE, DCMI_D0/PSSI_D0, EVENTOUT | UCPD1_DB1 | ||
| 94/277 | G5 | 69 | 102 | E11 | 121 | E14 F13 | 43 | 46 | 69 102 | E10 | 121 D15 | PA10 | I/O | FT_h | - | TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX, FDCAN2_TX, SDMMC1_D0, DCMI_D1/PSSI_D1, EVENTOUT | - | ||
| 94/277 | E1 | 70 | 103 | C13 | 122 | D15 F15 | 44 | 47 | 70 103 | F13 | 122 C15 | PA11 | I/O | FT_u | - | TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS,UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX, USB_DM, EVENTOUT | - | ||
| 94/277 | C1 | 71 | 104 | B13 | 123 | C15 F14 | 45 48 | 71 | 104 E13 | 123 B15 | PA12 | I/O | FT_u | - | TIM1_ETR, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE, SAI2_FS_B, FDCAN1_TX, USB_DP, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| WLCSP80 | Pin number (1)(2) - SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 SMPS | Pin number (1)(2) - UFBGA169 SMPS | Pin number (1)(2) - LQFP176 SMPS UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - LQFP176 UFBGA176+25 | Pin number (1)(2) - Pin name (function after reset) (3)(4) | Pin number (1)(2) - Pin type | I/O structure Notes | Alternate functions | Additional functions | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| F4 | 72 | 105 | D12 | 124 | E13 | F12 | 46 | 49 | 72 | 105 | E12 | 124 A15 | PA13 (JTMS/SWDIO) | I/O | FT | (7) | JTMS/SWDIO, EVENTOUT | - |
| - | 74 | 107 | E12 | 126 D14 | - | 47 | 50 | 74 | 107 C12 | 126 F12 | VSS | S | - | - | - | - | ||
| - | 75 | 108 | D13 | 127 | E12 | - | 48 | 51 | 75 | 108 | C13 | 127 F13 | VDD | S | - | - | - | - |
| B2 | 73 | 106 | E13 | 125 F12 | F11 | - | - | 73 | 106 D13 | 125 H13 | VDDUSB | S | - | - | - | - | ||
| - | - | - | C12 | 128 B15 | E15 | - | - | - | - | D12 | 128 E12 | PH13 | I/O | FT_h | - | LPTIM1_IN2, TIM8_CH1N, UART8_TX, UART4_TX, FDCAN1_TX,DCMI_D3/PSSI_D3, EVENTOUT | - | |
| - | - | - | D11 | 129 D13 | E14 | - | - | - | - | D10 | 129 E13 | PH14 | I/O | FT_h | - | TIM8_CH2N, UART4_RX, FDCAN1_RX, DCMI_D4/PSSI_D4, EVENTOUT | - | |
| - | - | - | A13 | 130 C14 | E13 | - | - | - | - D11 | 130 D13 | PH15 | I/O | FT_h | - | TIM8_CH3N, DCMI_D11/PSSI_D11, EVENTOUT | - | ||
| - | - | - | B12 | 131 - | E12 | - | - | - | - | B13 | 131 E14 | PI0 | I/O | FT_h | - | TIM5_CH4, SPI2_NSS/I2S2_WS, DCMI_D13/PSSI_D13, EVENTOUT | - | |
| - | - | - | C11 | 132 A15 | D15 | - | - | - | - | B12 | 132 D14 | PI1 | I/O | FT_h | - | TIM8_BKIN2, SPI2_SCK/I2S2_CK, DCMI_D8/PSSI_D8, EVENTOUT | - | |
| - | - | - | D10 | 133 B14 | F10 | - | - | - | - A13 | 133 C14 | PI2 | I/O | FT_h | - | TIM8_CH4,SPI2_MISO/I2S2_SDI, DCMI_D9/PSSI_D9, EVENTOUT | - | ||
| - | - | - | A12 | 134 A14 | D14 | - | - | - | - C11 | 134 C13 | PI3 | I/O | FT_h | - | TIM8_ETR, SPI2_MOSI/I2S2_SDO, DCMI_D10/PSSI_D10, EVENTOUT | - |
| Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 SMPS TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 LQFP176 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin name (function after reset) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - I/O structure | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - (3)(4) Pin type Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | - - | B8 | 135 | D9 | - | - | - | - | - | B10 | 135 D9 | VSS | S | - | - | - | - | |
| - | - - | A8 | 136 | D8 - | - | - | - | - | A10 | 136 C9 | VDD | S | - | - | - | - | ||
| E3 | 76 | 109 | C10 | 137 | B13 C15 | 49 | 52 | 76 | 109 | A12 | A14 | 137 | PA14 (JTCK/SWCLK) | I/O | FT | (7) | JTCK/SWCLK, EVENTOUT | - |
| D4 | 77 | 110 | B10 | 138 | C13 C13 | 50 | 53 | 77 | 110 | B11 | 138 A13 | PA15(JTDI) | I/O | FT | (7) | JTDI, TIM2_CH1, LPTIM3_IN2, HDMI_CEC,SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS/UART4_DE, UART7_TX, FMC_NBL1, DCMI_D11/PSSI_D11,TIM2_ETR, EVENTOUT | - | |
| C3 | 78 | 111 | A10 | 139 | D12 D12 | 51 54 | 78 | 111 | C10 | 139 | B14 | PC10 | I/O | FT_h | - | LPTIM3_ETR, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1, ETH_MII_TXD0/ETH_RMII_TXD0, SDMMC1_D2, DCMI_D8/PSSI_D8, EVENTOUT | - | |
| E5 | 79 | 112 | A9 | 140 | C12 B14 | 52 | 55 79 | 112 | A11 | 140 | B13 | PC11 | I/O | FT_h | - | LPTIM3_IN1, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS, SDMMC1_D3, DCMI_D4/PSSI_D4, EVENTOUT | - | |
| F6 | 80 | 113 | D9 | 141 | C11 B15 | 53 | 56 | 80 | 113 | B9 | 141 A12 | PC12 | I/O | FT_h | - | TRACED3, TIM15_CH1, SPI6_SCK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| Pin number (1)(2) - WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 SMPS | Pin number (1)(2) - UFBGA169 SMPS | Pin number (1)(2) - LQFP176 SMPS UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - LQFP176 UFBGA176+25 | Pin number (1)(2) - Pin name (function after reset) (3)(4) | Pin number (1)(2) - Pin type | Pin number (1)(2) - I/O structure Notes | Alternate functions | Additional functions | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | - - | B11 | - | D11 | - - | - | - | - - | - - | VSS | S | - | - | - | - | |
| - | - | - | A11 | - D10 | - - | - - | - - | - - | VDD | S | - | - | - | - | ||
| A3 | 81 | 114 | C9 | 142 B12 | E10 - | - 81 | 114 | D9 | 142 B12 | PD0 | I/O | FT_h | - | TIM8_CH4N, UART4_RX, FDCAN1_RX, UART9_CTS, FMC_D2/FMC_AD2, EVENTOUT | - | |
| B4 | 82 | 115 | B9 | 143 A13 | C12 - | - 82 | 115 | E9 | 143 C12 | PD1 | I/O | FT_h | - | UART4_TX, FDCAN1_TX, FMC_D3/FMC_AD3, EVENTOUT | - | |
| A5 | 83 | 116 | E8 | 144 C10 | D11 | 54 | - | 83 116 | C9 | 144 D12 | PD2 | I/O | FT_h | - | TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD, DCMI_D11/PSSI_D11, LPTIM4_ETR, EVENTOUT | WKUP7 |
| - | 84 | 117 | C8 | 145 A12 | A14 | - | - | 84 | 117 A9 | 145 D11 | PD3 | I/O | FT_h | - | SPI2_SCK/I2S2_CK, USART2_CTS/USART2_NSS, FMC_CLK, DCMI_D5/PSSI_D5, EVENTOUT | WKUP8 |
| - | 85 | 118 | D8 | 146 B11 | B13 - | - | 85 | 118 F8 | 146 D10 | PD4 | I/O | FT_h | - | USART2_RTS/USART2_DE, OCTOSPI1_IO4, FMC_NOE, EVENTOUT | - | |
| - | 86 | 119 | A7 | 147 A11 | B12 - | - | 86 119 | D8 | 147 C11 | PD5 | I/O | FT_h | - | TIM1_CH4N, SPI2_RDY, USART2_TX, FDCAN1_TX, OCTOSPI1_IO5, FMC_NWE, EVENTOUT | - | |
| - | - | 120 | - | 148 - | - - | - | - | 120 B7 | 148 D8 | VSS | S | - | - | - | - | |
| - | - | 121 | A6 | 149 D7 | D7 | - | - | - | 121 A7 | 149 C8 | VDDIO2 | S | - | - | - | - |
| 98/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 SMPS TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin after reset) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - name (function (3)(4) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin type | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - I/O structure | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Notes Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 98/277 | - | 87 | 122 F7 | 150 | B10 A10 | - | - | 87 | 122 | E8 | 150 | B11 | PD6 | I/O | FT_sh | - | SAI1_D1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, OCTOSPI1_IO6, SDMMC2_CK, FMC_NWAIT, DCMI_D10/PSSI_D10, EVENTOUT | - | |
| 98/277 | - | 88 | 123 | B7 | 151 | A10 C9 | - | - 88 | 123 | B8 | 151 | A11 | PD7 | I/O | FT_sh | - | SPI1_MOSI/I2S1_SDO, USART2_CK, OCTOSPI1_IO7, SDMMC2_CMD, FMC_NE1/FMC_NCE, LPTIM4_OUT, EVENTOUT | - | |
| 98/277 | - | - | - | - | - | D6 - | - | - | - | - | - | - | - | VSS | S | - | - | - | - |
| 98/277 | - | - | 124 | E7 | 152 | B9 B9 | - | - | - | 124 | F7 | 152 C10 | PG9 | I/O | FT_sh | - | SPI1_MISO/I2S1_SDI, USART6_RX, OCTOSPI1_IO6, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, DCMI_VSYNC/PSSI_RDY, EVENTOUT | - | |
| 98/277 | - | - | 125 | C7 | 153 | A9 A9 | - - | - | 125 | A8 | 153 B10 | PG10 | I/O | FT_sh | - | SPI1_NSS/I2S1_WS,SAI2_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2/PSSI_D2, EVENTOUT | - | ||
| 98/277 | - | - | - | - | 154 | C9 D8 | - | - | - | 126 | E7 | B9 | 154 | PG11 | I/O | FT_sh | - | LPTIM1_IN2,SPI1_SCK/I2S1_CK, USART10_RX, USART11_RTS/USART11_DE, SDMMC2_D2, ETH_MII_TX_EN/ETH_RMII_TX_ EN, DCMI_D3/PSSI_D3, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| Pin number (1)(2) - WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 SMPS | Pin number (1)(2) - UFBGA169 SMPS | Pin number (1)(2) - LQFP176 SMPS UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - LQFP176 | Pin number (1)(2) - UFBGA176+25 | Pin number (1)(2) - Pin name (function after reset) | (3)(4) Pin type I/O structure Notes | Alternate functions | Additional functions | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| - | - 126 | D7 | 155 | B8 | C8 | - | - | - | 127 | C8 | 155 B8 | PG12 | I/O | FT_sh | - | LPTIM1_IN1, PSSI_D15, SPI6_MISO, USART10_TX, USART6_RTS/USART6_DE, SDMMC2_D3, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_NE4,DCMI_D11/PSSI_D11, LPTIM5_CH1, EVENTOUT | - | |
| - | - | 127 | - | 156 C8 | B8 | - | - | - | 128 | D7 | 156 A8 | PG13 | I/O | FT_sh | - | TRACED0, LPTIM1_CH1, SPI6_SCK, USART10_CTS/USART10_NSS, USART6_CTS/USART6_NSS, SDMMC2_D6, ETH_MII_TXD0/ETH_RMII_TXD0, FMC_A24, LPTIM5_CH2, EVENTOUT | - | |
| - | - | 128 | - | 157 A8 | A8 | - | - | - | 129 | C7 | 157 A7 | PG14 | I/O | FT_sh | - | TRACED1, LPTIM1_ETR, LPTIM1_CH2, SPI6_MOSI, USART10_RTS/USART10_DE, USART6_TX, OCTOSPI1_IO7, SDMMC2_D7, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_A25, LPTIM5_IN1, EVENTOUT | - | |
| - | - | 129 | B4 | 158 - | - | - | - | - | 130 | - | 158 D7 | VSS | S | - | - | - | - | |
| - | - | 130 | A3 | 159 - | - | - | - | - | 131 | - | 159 C7 | VDD | S | - | - | - | - | |
| - | - | 131 | B6 | 160 A7 | A7 | - | - | - | 132 | B6 | 160 B7 | PG15 | I/O | FT_h | - | SPI4_RDY, USART10_CK, USART6_CTS/USART6_NSS, FMC_NCAS, DCMI_D13/PSSI_D13, EVENTOUT | - |
| 100/277 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - WLCSP80 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP176 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 SMPS TFBGA225 SMPS | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP64 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - VFQFPN68 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP100 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - LQFP144 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA169 LQFP176 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - UFBGA176+25 | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin name (function after reset) (3)(4) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Pin type | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Notes | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - I/O structure | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Alternate functions | Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) - Additional functions |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 100/277 | C5 | 89 | 132 | F6 | 161 B7 | B7 | 55 | 57 | 89 | 133 | E6 161 | A10 | PB3(JTDO/ TRACESWO) | I/O | FT_fh | - | JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, UART12_CTS/UART12_NSS, SPI6_SCK, SDMMC2_D2, CRS_SYNC, UART7_RX, LPTIM6_ETR, EVENTOUT | - | |
| 100/277 | B6 | 90 | 133 | A5 | 162 | C7 C7 | 56 | 58 | 90 | 134 | A6 | 162 A9 | PB4(NJTRST) | I/O | FT_h | - | NJTRST, TIM16_BKIN, TIM3_CH1, OCTOSPI1_CLK, LPTIM1_CH2, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS,SPI6_MISO, SDMMC2_D3, UART7_TX, DCMI_D7/PSSI_D7, EVENTOUT | - | |
| 100/277 | D6 | 91 | 134 | E6 | 163 | A6 | E7 | 57 | 59 91 | 135 | C6 | 163 A6 | PB5 | I/O | FT_h | - | TIM17_BKIN, TIM3_CH2, OCTOSPI1_NCLK, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10/PSSI_D10, UART5_RX, EVENTOUT | - | |
| 100/277 | E7 | 92 | 135 | C6 | 164 | B6 E8 | 58 | 60 | 92 | 136 | A5 | 164 B6 | PB6 | I/O | FT_f | - | TIM16_CH1N, TIM4_CH1, I3C1_SCL, I2C1_SCL, HDMI_CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPI1_NCS, FMC_SDNE1, DCMI_D5/PSSI_D5, UART5_TX, EVENTOUT | - |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
| WLCSP80 SMPS | Pin number (1)(2) - LQFP100 SMPS | Pin number (1)(2) - LQFP144 SMPS | Pin number (1)(2) - UFBGA169 SMPS | Pin number (1)(2) - LQFP176 SMPS | Pin number (1)(2) - UFBGA176+25 SMPS | Pin number (1)(2) - TFBGA225 SMPS | Pin number (1)(2) - LQFP64 | Pin number (1)(2) - VFQFPN68 | Pin number (1)(2) - LQFP100 | Pin number (1)(2) - LQFP144 | Pin number (1)(2) - UFBGA169 | Pin number (1)(2) - LQFP176 UFBGA176+25 | Pin number (1)(2) - Pin name (function after reset) (3)(4) | Pin type | I/O structure Notes | Alternate functions | Additional functions | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| C7 | 93 | 136 | D6 | 165 | C6 | A6 | 59 | 61 | 93 | 137 | D6 | 165 B5 | PB7 | I/O | FT_fa | - | TIM17_CH1N, TIM4_CH2, I3C1_SDA, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, FDCAN1_TX, SDMMC2_D5, SDMMC2_CKIN, FMC_NL, DCMI_VSYNC/PSSI_RDY, EVENTOUT | WKUP5 |
| D8 94 | 137 | B5 | 166 A5 | B6 | 60 | 62 | 94 | 138 | B5 | 166 D6 | BOOT0 | I | B | - | - | - | ||
| E9 95 | 138 | F5 | 167 B5 | C6 | 61 | 63 | 95 | 139 | E5 | 167 A5 | PB8 | I/O | FT_fhs | - | TIM16_CH1, TIM4_CH3, I3C1_SCL, I2C1_SCL, SPI4_RDY, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6/PSSI_D6, EVENTOUT | - | ||
| - | 96 | 139 | E5 | 168 A4 | A5 | - | 64 | 96 | 140 | A4 | 168 B4 | PB9 | I/O | FT_fhs | - | TIM17_CH1, TIM4_CH4, I3C1_SDA, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, SDMMC2_CKIN, SDMMC1_D5, DCMI_D7/PSSI_D7, EVENTOUT | - | |
| - | 97 | 140 | D5 | 169 C5 | D6 | - | 65 | 97 | 141 | C5 | 169 A4 | PE0 | I/O | FT_h | - | LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2, LPTIM2_ETR, SPI3_RDY, UART8_RX, FDCAN1_RX, SAI2_MCLK_A, FMC_NBL0, DCMI_D2/PSSI_D2, EVENTOUT | - |
| Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2) | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Pin | WLCSP80 SMPS LQFP100 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP176 SMPS UFBGA176+25 SMPS | TFBGA225 SMPS | LQFP64 | VFQFPN68 | LQFP100 | LQFP144 UFBGA169 | LQFP176 | Pin name (function after reset) UFBGA176+25 | Pin type | I/O structure Notes | Alternate functions | Additional functions | (3)(4) | ||||
| - | - | 141 | C5 | 170 | B4 B5 | - | - | - | - | D5 | 170 A3 | PE1 | I/O | FT_h | - | LPTIM1_IN2, UART8_TX, FDCAN1_TX, FMC_NBL1, DCMI_D3/PSSI_D3, EVENTOUT | - | |||
| A3 | A9 98 | 142 | A4 | 171 | E6 | 62 | 66 | 98 | 142 | B4 | 171 C6 | VCAP | - - | - | - | |||||
| - 99 | 143 | - | - | - | - | 63 | 67 | 99 | 143 B3 | - | - | VSS | S S | - | - | - | - | |||
| - | - 100 | 144 | - | 172 | - | 64 | 68 100 | 144 | A3 | 172 - | VDD | S | - | - | - | - | ||||
| B3 | - - - | - | C4 B3 | 173 174 | C5 | - | - | - | - | C4 | 173 | D4 | PI4 | I/O I/O | FT_h | - - | TIM8_BKIN, SPI2_RDY, SAI2_MCLK_A, DCMI_D5/PSSI_D5, EVENTOUT TIM8_CH1, SAI2_SCK_A, DCMI_VSYNC/PSSI_RDY, EVENTOUT | - | ||
| - | - | A2 | A4 | - | - - | - | - | 174 C4 | PI5 | FT_h | - | |||||||||
| - | - | - | A2 | 175 | C4 | A3 | - | - - | - | C3 | 175 C3 | PI6 | I/O | FT_h | - | TIM8_CH2, SAI2_SD_A, DCMI_D6/PSSI_D6, EVENTOUT | - | |||
| - | - | - | A1 | 176 | A1 | B4 | - | - | - | - | A2 176 | C2 | PI7 | I/O | FT_h | - | TIM8_CH3, SAI2_FS_A, DCMI_D7/PSSI_D7, EVENTOUT | - | ||
| - - | - | - | - | F6 | L11 | - | - | - | - | - | - F6 | VSS | S | - | - | - | - | |||
| - - - | - | - - | - - | F7 F8 | R1 | - - | - | - - | - | - | - F7 | VSS | S | - | - | - | - | |||
| - | - | A15 | - | - | - | - F8 | VSS | S | - - | - | - | |||||||||
| - - | - | - | - | F9 | E11 | - | - | - | - | - | - | F9 | VSS | S | - | - | - | - | ||
| - - | - | - | - | F10 | G12 | - | - | - | - | - | - | F10 | VSS | S | - | - | - | - | ||
| - - | - | - | - | G6 | H10 | - | - | - | - | - | - | G6 | VSS | S | - | - | - | - | ||
| G7 | - - | - | - | - | G15 | - | - | - | - | - | - | G7 | VSS | - | S - | - | - | |||
| - | - | - | - | - | - | - | VSS | S | - | - | - | - | ||||||||
| G8 | - | - | A2 | - | - | G8 |
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
DS14258 Rev 6
STM32H563AI/G Electrical Characteristics
Unless otherwise specified, the parameters given in Table 95 are derived from tests performed under the ambient temperature, f HCLK frequency, and V DDA supply voltage conditions summarized in Table 20 .
Table 95. 12-bit ADC characteristics (1)(2)
| Symbol | Parameter | Conditions | Conditions | Conditions | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|---|---|---|
| V DDA | Analog supply voltage for ADC ON | - | - | - | - | 1.62 | - | 3.6 | |
| V REF+ | Positive reference voltage | - | - | - | - | 1.62 | - | V DDA | V |
| V REF- | Negative reference voltage | - | - | - | - | V SSA | V SSA | V SSA | |
| f adc_ker_ck (3) | Clock frequency | 1.62 V ≤ V DDA ≤ 3.6 V | 1.62 V ≤ V DDA ≤ 3.6 V | 1.62 V ≤ V DDA ≤ 3.6 V | 1.62 V ≤ V DDA ≤ 3.6 V | 1.5 | - | 75 | MHz |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 12 bits | Continuous mode | 1.8V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 75 MHz 70 | - | 5.00 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 12 bits | Continuous mode | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = MHz | - | 4.66 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 12 bits | Single or Discontinuous mode | 2.4V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 60 MHz | - | 4.00 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 12 bits | Single or Discontinuous mode | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 50 MHz | - | 3.33 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Sampling rate for fast channels (VIN[0:5]) | Resolution = 10 bits | Continuous mode | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 75 MHz | - | 5.77 | - | MSPS |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 10 bits | Single or Discontinuous mode | 2.4V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 75 MHz | - | 5.77 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 10 bits | Single or Discontinuous mode | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 65 MHz | - | 5.00 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 8 bits | All modes | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 75 MHz | - | 6.82 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Resolution = 6 bits | All modes | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 75 MHz | - | 8.33 | - | MSPS | |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Sampling rate for slow channels | Resolution = 12 bits | All modes (5) | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 35 MHz | - | 2.30 | - | MSPS |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Sampling rate for slow channels | Resolution = 10 bits | All modes (5) | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 35 MHz | - | 2.70 | - | MSPS |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Sampling rate for slow channels | Resolution = 8 bits | All modes (5) | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 50 MHz | - | 4.50 | - | MSPS |
| f S (4) with R AIN = 47 Ω and C PCB = 22 pF | Sampling rate for slow channels | Resolution = 6 bits | All modes (5) | 1.6V ≤ V DDA ≤ 3.6V | f adc_ker_ck = 50 MHz | - | 5.50 | - | MSPS |
| t TRIG | Externaltrigger period | Resolution = 12 bits | Resolution = 12 bits | Resolution = 12 bits | Resolution = 12 bits | - | - | 15 | 1/f adc_ker_ck |
| V AIN (2) | Conversion voltage range | - | - | - | - | 0 | - | V REF+ | V |
| V CMIV | Common mode input voltage | - | - | - | - | V REF / 2 - 10% | V REF / 2 | V REF / 2 + 10% | V |
Table 95. 12-bit ADC characteristics (1)(2)
Table 95. 12-bit ADC characteristics (1)(2) (continued)
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Resolution = 12 bits, T J = 130°C (tolerance 4 LSBs) | - | - | 321 | Ω | ||
| Resolution = 12 bits, T J = 125°C | - | - | 220 | Ω | ||
| Resolution = 10 bits, T J = 130°C | - | - | 1039 | Ω | ||
| (6) | External input | Resolution = 10 bits, T J = 125°C | - | - | 2100 | Ω |
| R AIN | impedance | Resolution = 8 bits, T J = 130°C | - | - | 6327 | Ω |
| Resolution = 8 bits, T J = 125°C | - | - | 12000 | Ω | ||
| Resolution = 6 bits, T J = 130°C | - | - | 47620 | Ω | ||
| Resolution = 6 bits, T J = 125°C | - | - | 80000 | Ω | ||
| C ADC | Internal sample and hold capacitor | - | - | 3 | - | pF |
| t ADCVREG_ STUP | LDO startup time | - | - | 5 | 10 | μs |
| t STAB | Power-up time | LDO already started | 1 | - | - | Conversion cycle |
| t OFF_CAL | Offset calibration time | - | 1335 | 1335 | 1335 | |
| t LATR | Trigger conversion | CKMODE = 00 | 1.5 | 2 | 2.5 | |
| t LATR | latency for regular and | CKMODE = 01 | - | - | 2.5 | |
| t LATR | injected channels without | CKMODE = 10 | - | - | 2.5 | |
| t LATR | aborting the conversion | CKMODE = 11 | - | - | 2.25 | |
| t LATRINJ | Trigger conversion | CKMODE = 00 | 2.5 | 3 | 3.5 | 1/f adc_ker_ck |
| t LATRINJ | latency for regular and | CKMODE = 01 | - | - | 3.5 | |
| t LATRINJ | injected channelswhen a regular | CKMODE = 10 | - | - | 3.5 | |
| t S | conversion is aborted Sampling time | CKMODE = 11 - | - 2.5 | - - | 3.25 640.5 | |
| t CONV | Total conversion time (including sampling) | N-bits resolution | t S + 0.5 + N | - | - | |
| I DDA_D(ADC) | Consumption on V and | fs = 5 MSPS | - | 600 | - | |
| I DDA_D(ADC) | DDA V REF , | fs = 1 MSPS | - | 190 | - | |
| I DDA_SE(ADC) | differential mode | fs = 0.1 MSPS | - | 50 | - | |
| I DDA_SE(ADC) | Consumption on V DDA and V , single- | fs = 5 MSPS | - | 500 | - | |
| I DDA_SE(ADC) | fs = 1 MSPS | - | 150 | - | ||
| REF ended mode | fs = 0.1 MSPS | - | 50 | - | ||
| I DD(ADC) | f adc_ker_ck = 75 MHz f adc_ker_ck = 50 MHz | - | 265 175 | - - | μA | |
| Consumption | f adc_ker_ck = 25 MHz | - | 90 | - | ||
| on V DD | f adc_ker_ck = 12.5 MHz f adc_ker_ck = 6.25 MHz | - - | 45 22 | - - | ||
| f adc_ker_ck = 3.125 MHz | - | 11 | - |
241
- This frequency is the analog ADC specification, it must respect the value in Table 21 .
- These values are valid on BGA packages.
- Depending upon the package, V REF+ can be internally connected to V DDA , and V REF- to V SSA .
- The tolerance is two LSBs for 12-, 10-, and 8-bit resolutions, if not otherwise specified.
Table 96. Minimum sampling time versus R AIN (1)(2)
| Resolution | R ( Ω ) - AIN | Minimum sampling time (s) - Fast channel | Minimum sampling time (s) - Slow channel (3) |
|---|---|---|---|
| 12 bits | 47 | 3.75E-08 | 6.12E-08 |
| 12 bits | 68 | 3.94E-08 | 6.25E-08 |
| 12 bits | 100 | 4.36E-08 | 6.51E-08 |
| 12 bits | 150 | 5.11E-08 | 7.00E-08 |
| 12 bits | 220 | 6.54E-08 | 7.86E-08 |
| 12 bits | 330 | 8.80E-08 | 9.57E-08 |
| 12 bits | 470 | 1.17E-07 | 1.23E-07 |
| 12 bits | 680 | 1.60E-07 | 1.65E-07 |
| 10 bits | 47 | 3.19E-08 | 5.17E-08 |
| 10 bits | 68 | 3.35E-08 | 5.28E-08 |
| 10 bits | 100 | 3.66E-08 | 5.45E-08 |
| 10 bits | 150 | 4.35E-08 | 5.83E-08 |
| 10 bits | 220 | 5.43E-08 | 6.50E-08 |
| 10 bits | 330 | 7.18E-08 | 7.89E-08 |
| 10 bits | 470 | 9.46E-08 | 1.00E-07 |
| 10 bits | 680 | 1.28E-07 | 1.33E-07 |
| 10 bits | 1000 | 1.81E-07 | 1.83E-07 |
| 10 bits | 1500 | 2.63E-07 | 2.63E-07 |
| 10 bits | 2200 | 3.79E-07 | 3.76E-07 |
| 10 bits | 3300 | 5.57E-07 | 5.52E-07 |
Table 96. Minimum sampling time versus R AIN (1)(2)
Table 96. Minimum sampling time versus R AIN (1)(2) (continued)
- Resolution R AIN ( Ω ) Minimum sampling time (s) - Fast channel Minimum sampling time (s) - Slow channel (3)
- 47 2.64E-08 4.17E-08
- 68 2.76E-08 4.24E-08
- 100 3.02E-08 4.39E-08
- 150 3.51E-08 4.66E-08
- 220 4.27E-08 5.13E-08
- 330 5.52E-08 6.19E-08
- 470 7.17E-08 7.72E-08
- 680 9.68E-08 1.00E-07
- 1000 1.34E-07 1.37E-07
- 1500 1.93E-07 1.94E-07
- 2200 2.76E-07 2.74E-07
- 3300 4.06E-07 4.01E-07
- 4700 5.73E-07 5.62E-07
- 6800 8.21E-07 7.99E-07
- 10000 1.20E-06 1.17E-06
- 15000 1.79E-06 1.74E-06
- 47 2.14E-08 3.16E-08
- 68 2.23E-08 3.21E-08
- 100 2.40E-08 3.31E-08
- 150 2.68E-08 3.52E-08
- 220 3.13E-08 3.87E-08
- 330 3.89E-08 4.51E-08
- 470 4.88E-08 5.39E-08
- 680 6.38E-08 6.79E-08
- 1000 8.70E-08 8.97E-08
- 1500 1.23E-07 1.24E-07
- 2200 1.73E-07 1.73E-07
- 3300 2.53E-07 2.49E-07
- 4700 3.53E-07 3.45E-07
- 6800 5.04E-07 4.90E-07
- 10000 7.34E-07 7.11E-07
- 15000 1.09E-06 1.05E-06
241
- Slow channels correspond to all ADC inputs except for the fast channels.
Figure 56. ADC conversion timing diagram
STM32H563AI/G Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 17 , Table 18 , and Table 19 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.
Table 17. Voltage characteristics (1)
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DDx - V SS | External main supply voltage (including V DDSMPS (2) , V DDA , V DDUSB , V DDIO2 (2)(3)(4) , V BAT , and V REF+ ) | -0.3 | 4.0 | V |
| V DDIOx (4) - V SS | I/O supply when HSLV (2) = 0 | -0.3 | 4.0 | V |
| V DDIOx (4) - V SS | I/O supply when HSLV (2) = 1 | -0.3 | 2.75 | V |
| V IN (5) | Input voltage on FT_xxx pins except FT_c pins | V SS - 0.3 | min (min(V DD , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0 V) (6)(7) | V |
| V IN (5) | Input voltage on FT_t in V BAT mode | V SS - 0.3 | min (min(V BAT ,V DDA ,V DDUSB , V DDIO2 ) + 4.0V, 6.0 V) | V |
| V IN (5) | Input voltage on TT_xx pins | V SS - 0.3 | 4.0 | V |
| V IN (5) | Input voltage on BOOT0 pin | V SS | min (min(V DD , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0 V) (6) | V |
| V IN (5) | Input voltage on FT_c pins | V SS - 0.3 | 5.5 | V |
| V IN (5) | Input voltage on any other pins | V SS - 0.3 | 4.0 | V |
| V REF+ - V DDA | Allowed voltage difference for V REF+ > V DDA | - | 0.4 | V |
| | ∆ V DDx | | Variations between different V DDX power pins of the same domain | - | 50.0 | mV |
| |V SSx -V SS | | Variations between all the different ground pins | - | 50.0 | mV |
- HSLV = High-speed low-voltage mode. Refer to General purpose I/Os (GPIO) section of RM0481.
- If HSLV = 0.
- VDDIO1 or V DDIO2 . V DDIO1 = V DD .
- VIN maximum must always be respected. Refer to the maximum allowed injected current values.
- To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
- This formula must be applied on power supplies related to the I/O structure described by the pin definition table.
241
Table 18. Current characteristics
| Symbol | Ratings | Max | Unit |
|---|---|---|---|
| ∑ IV DD | Total current into sum of all V DD power lines (source) (1) | 350 | mA |
| ∑ IV SS | Total current out of sum of all V SS ground lines (sink) (1) | 350 | mA |
| IV DD | Maximum current into each V DD power pin (source) (1) | 100 | mA |
| IV SS | Maximum current out of each V SS ground pin (sink) (1) | 100 | mA |
| I IO(PIN) | Output current sunk/sourced by any I/O and control pin | 20 | mA |
| ∑ I IO(PIN) | Total output current sunk by sum of all I/Os and control pins (2) | 140 | mA |
| ∑ I IO(PIN) | Total output current sourced by sum of all I/Os and control pins (2) | 140 | mA |
| I INJ(PIN) (3)(4) | Injected current on FT_xxx, TT_xx, NRST pins | -5 / 0 | mA |
| ∑ |I INJ(PIN) | | Total injected current (sum of all I/Os and control pins) (5) | ±25 | mA |
- This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
- Positive injection (when V IN > V DDIOx ) is not possible on these I/Os, and does not occur for input voltages lower than the specified maximum value.
- A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer to Table 17 for the minimum allowed input voltage values.
- When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).
Table 19. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 130 (1) | °C |
STM32H563AI/G Thermal Information
The maximum chip-junction temperature, T Jmax in degrees Celsius, can be calculated using the following equation:
$$T_{Jmax} = T_{Amax} + (P_{Dmax} \times \Theta_{JA})$$
STM32H563AI/G Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.
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