Overview

Part: STM32U575xx

Type: Ultra-low-power Arm Cortex-M33 32-bit MCU

Key Specs:

Core: Arm 32-bit Cortex-M33 CPU with TrustZone, MPU, DSP, and FPU
Max CPU Frequency: 160 MHz
Performance: 240 DMIPS
Flash Memory: Up to 2 MB
SRAM: 786 KB (ECC OFF) or 722 KB (ECC ON)
Power Supply: 1.71 V to 3.6 V
Temperature Range: –40 °C to +85/125 °C
Run Mode Current: 19.5 μA/MHz @ 3.3 V
Shutdown Mode Current: 160 nA

Features:

Ultra-low-power with FlexPowerControl, including LPBAM and VBAT mode
Arm TrustZone security with securable I/Os, memories, and peripherals
ART Accelerator with 8-Kbyte instruction cache and 4-Kbyte data cache
Embedded regulator (LDO) and SMPS step-down converter
Up to 136 fast I/Os with interrupt capability
Up to 17 timers and 2 watchdogs
Up to 22 communication peripherals including USB Type-C/PD, USB OTG 2.0, I2C, U(S)ART, SPI, CAN FD, SDMMC
Graphic features: Chrom-ART Accelerator (DMA2D) and digital camera interface
Mathematical coprocessor (CORDIC, FMAC)
Rich analog peripherals: 14-bit ADC, 12-bit ADC, 2 12-bit DACs, 2 operational amplifiers, 2 ultra-low-power comparators

Applications:

null

Package:

null

Features

Includes ST state-of-the-art patented technology

Ultra-low-power with FlexPowerControl

1.71 V to 3.6 V power supply
–40 °C to +85/125 °C temperature range
Low-power background autonomous mode (LPBAM): autonomous peripherals with DMA, functional down to Stop 2 mode
VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM
160 nA Shutdown mode (24 wake-up pins)
210 nA Standby mode (24 wake-up pins)
530 nA Standby mode with RTC
1.9 μA Stop 3 mode with 16-Kbyte SRAM
4.3 µA Stop 3 mode with full SRAM
4.0 µA Stop 2 mode with 16-Kbyte SRAM
8.95 µA Stop 2 mode with full SRAM
19.5 μA/MHz Run mode @ 3.3 V

Core

• Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU

ART Accelerator

8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories: up to 160 MHz, 240 DMIPS
4-Kbyte data cache for external memories

Power management

• Embedded regulator (LDO) and SMPS step-down converter supporting switch on-the-fly and voltage scaling

Benchmarks

• 1.5 DMIPS/MHz (Drystone 2.1)

651 CoreMark® (4.07 CoreMark®/MHz)
450 ULPMark™-CP
109 ULPMark™-PP
51.5 ULPMark™-CM
133000 SecureMark™-TLS

Memories

2-Mbyte flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles
786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON
External memory interface supporting SRAM, PSRAM, NOR, NAND, and FRAM memories
2 Octo-SPI memory interfaces

Security

Arm® TrustZone® and securable I/Os, memories, and peripherals
Flexible life cycle scheme with RDP and password protected debug
Root of trust thanks to unique boot entry and secure hide protection area (HDP)

Secure firmware installation (SFI) thanks to embedded root secure services (RSS)
Secure firmware upgrade support with TF-M
HASH hardware accelerator
True random number generator, NIST SP800-90B compliant
96-bit unique ID
512-byte OTP (one-time programmable)
Active tampers

Clock management

4 to 50 MHz crystal oscillator
32 kHz crystal oscillator for RTC (LSE)
Internal 16 MHz factory-trimmed RC (±1%)
Internal low-power 32 kHz RC (±5%)
2 internal multispeed 100 kHz to 48 MHz oscillators, including one autotrimmed by LSE (better than ±0.25% accuracy)
Internal 48 MHz with clock recovery
3 PLLs for system clock, USB, audio, ADC

General-purpose input/outputs

• Up to 136 fast I/Os with interrupt capability most 5V-tolerant and up to 14 I/Os with independent supply down to 1.08 V

Up to 17 timers and 2 watchdogs

2 16-bit advanced motor-control, 4 32-bit, 5 16-bit, 4 low-power 16-bit (available in Stop mode), 2 SysTick timers and 2 watchdogs
RTC with hardware calendar and calibration

Up to 22 communication peripherals

1 USB Type-C®/USB power delivery controller
1 USB OTG 2.0 full-speed controller
2 SAIs (serial audio interface)
4 I2C FM+(1 Mbit/s), SMBus/PMBus®
6 U(S)ART (SPI, ISO 7816, LIN, IrDA, modem)
3 SPI (+2 with OCTOSPI +3 with USART)
1 CAN FD controller
2 SDMMC interfaces
1 multifunction digital filter (6 filters) + 1 audio digital filter with sound-activity detection
Parallel synchronous slave interface

16- and 4-channel DMA controllers, functional in Stop mode

Graphic features

Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
1 digital camera interface

Mathematical coprocessor

CORDIC for trigonometric functions acceleration
Filter mathematical accelerator (FMAC)

Up to 22 capacitive sensing channels

• Support touch key, linear, and rotary touch sensors

Rich analog peripherals (independent supply)

14-bit ADC 2.5-Msps with hardware oversampling
12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
2 12-bit DAC, low-power sample and hold
2 operational amplifiers with built-in PGA
2 ultra-low-power comparators

CRC calculation unit

Debug

• Development support: serial-wire debug (SWD), JTAG, Embedded Trace Macrocell™ (ETM)

ECOPACK2 compliant packages Table 1. Device summary

| Reference
Part numbers | |---------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | STM32U575xx | STM32U575AG, STM32U575AI,
STM32U575CG, STM32U575CI,
STM32U575OG, STM32U575OI,
STM32U575QG, STM32U575QI,
STM32U575RG, STM32U575RI,
STM32U575VG, STM32U575VI,
STM32U575ZG, STM32U575ZI |

STM32U575xx Contents

Pin Configuration

Table 25. Legend/abbreviations used in the pinout table

| | Name |-----------|-------------------------|--- | | Pin name | | | | S | | Pin type | I | | | I/O | | | FT | | | TT | | | RST | | | | | | _a | | | _c | | I/O structure | _d | | | _f | | | _h | | | _o | | | _s | | | _t | | | _u | | | _v | | Notes | reset. | Pin | Alternate
functions | functions | Additional
functions | ^1. The related I/O structures | Abbreviation | Definition | ---------------------------------------------|------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--| | Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name | | Supply pin | | Input only pin | | Input/output pin | | 5V-tolerant I/O | | 3.6V-tolerant I/O | | Bidirectional reset pin with embedded weak pull-up
resistor | | Option for TT or FT I/Os(1) | | I/O, with analog switch function supplied by VDDA | | I/O with USB Type-C power delivery function | | I/O with USB Type-C power delivery dead battery function | | I/O, Fm+ capable | | I/O with high-speed low-voltage mode | | I/O with OSC32_IN/OSC32_OUT capability | | I/O supplied only by VDDIO2 | | I/O with a function supplied by VSW | | I/O, with USB function supplied by VDDUSB | | I/O very high-speed capable | | Unless otherwise specified by a note, all I/Os are set as analog inputs during and after | | Functions selected through GPIOx_AFR registers | | Functions directly selected/enabled through peripheral registers | in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.

Pinout, pin description and alternate functions

| | Pin number | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|----------|---------------|-------|-----------------------------------------------------------------------------------------------------------|--------------------------------------| | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | 1 | BЗ | 1 | A1 | - | - | 1 | B3 | 1 | A1 | PE2 | I/O | FT_ha | 1 | TRACECLK, TIM3_ETR, SAI1_CK1, TSC_G7_IO1, LPGPIO1_P14, FMC_A23, SAI1_MCLK_A, EVENTOUT | - | | - | - | C15 | 2 | A2 | 2 | D3 | - | - | 2 | A2 | 2 | D3 | PE3 | I/O | FT_
hat | 1 | TRACED0, TIM3_CH1, OCTOSPIM_P1_DQS, TSC_G7_IO2, LPGPIO1_P15, FMC_A19, SAI1_SD_B, EVENTOUT | TAMP_IN6/
TAMP_
OUT3 | | - | - | D14 | 3 | B2 | 3 | C2 | 1 | - | 3 | B2 | 3 | C2 | PE4 | I/O | FT_
hat | 1 | TRACED1, TIM3_CH2, SAI1_D2,
MDF1_SDI3, TSC_G7_IO3,
DCMI_D4/PSSI_D4, FMC_A20,
SAI1_FS_A, EVENTOUT | WKUP1,
TAMP_IN7/
TAMP_
OUT8 | | - | - | E13 | 4 | A1 | 4 | D2 | 1 | - | 4 | A1 | 4 | D2 | PE5 | I/O | FT_
hat | 1 | TRACED2, TIM3_CH3, SAI1_CK2, MDF1_CKI3, TSC_G7_IO4, DCMI_D6/PSSI_D6, FMC_A21, SAI1_SCK_A, EVENTOUT | WKUP2,
TAMP_IN8/
TAMP_
OUT7 | | - | - | D16 | 5 | C2 | 5 | E4 | - | - | 5 | C2 | 5 | E4 | PE6 | I/O | FT_ht | - | TRACED3, TIM3_CH4, SAI1_D1,
DCMI_D7/PSSI_D7, FMC_A22,
SAI1_SD_A, EVENTOUT | WKUP3,
TAMP_IN3/
TAMP_
OUT6 | | 1 | 1 | C17 | 6 | B1 | 6 | C1 | 1 | 1 | 6 | B1 | 6 | C1 | VBAT | S | - | - | - | - | | - | - | - | - | - | - | F2 | - | - | - | - | - | F2 | VSS | s | - | 1 | - | - |

| 1 | |----------|--| Table 26. STM32U575xx pin definitions(1) (continued)

| P
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| | | | | | | | | Tab | le 26 | . STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | uec | 1) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|------------------------------------------------------------------------------------------------|-------------------------| | | | | | | Pir | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | 1 | - | - | F2 | 15 | G4 | - | - | - | F2 | 15 | G4 | PF5 | I/O | FT_hv | ı | LPTIM3_CH1, OCTOSPIM_P2_NCLK,FMC_A5, EVENTOUT | - | | - | | - | 10 | F6 | 16 | H2 | 1 | - | 10 | F6 | 16 | H2 | VSS | S | - | - | - | - | | - | - | - | 11 | F7 | 17 | G1 | - | - | 11 | F7 | 17 | G1 | VDD | S | - | - | - | - | | - | 1 | - | - | - | 18 | H6 | - | - | - | - | 18 | H6 | PF6 | I/O | FT_h | - | TIM5_ETR, TIM5_CH1, DCMI_D12/PSSI_D12, OCTOSPIM_P2_NCS, OCTOSPIM_P1_IO3, SAI1_SD_B, EVENTOUT | 1 | | - | 1 | - | - | 1 | 19 | G2 | - | - | - | - | 19 | G2 | PF7 | I/O | FT_h | - | TIM5_CH2, FDCAN1_RX,
OCTOSPIM_P1_IO2,
SAI1_MCLK_B, EVENTOUT | - | | - | 1 | - | - | - | 20 | F1 | - | - | - | - | 20 | F1 | PF8 | I/O | FT_h | ı | TIM5_CH3, PSSI_D14,
FDCAN1_TX,
OCTOSPIM_P1_IO0,
SAI1_SCK_B, EVENTOUT | - | | - | - | - | - | - | 21 | G3 | - | - | - | - | 21 | G3 | PF9 | I/O | FT_h | I | TIM5_CH4, PSSI_D15,
OCTOSPIM_P1_IO1,
SAI1_FS_B, TIM15_CH1,
EVENTOUT | - | | - | - | - | - | - | 22 | H4 | ı | - | - | - | 22 | H4 | PF10 | I/O | FT_hv | ı | OCTOSPIM_P1_CLK, PSSI_D15,
MDF1_CCK1,
DCMI_D11/PSSI_D11, SAI1_D3,
TIM15_CH2, EVENTOUT | - |

| 3 | 15 |

---	----	--

								Tab	le 26	. STN	132U	575x	x pin definition	s ⁽¹⁾	(contin	ued	I)	,
					Pir	num	ber
LQFP48 SMPS UFQFPN48 SMPS	LQFP64 SMPS	WLCSP90 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	UFBGA169 SMPS	LQFP48 UFQFPN48	LQFP64	LQFP100	UFBGA132	LQFP144	UFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
5	5	F18	12	F1	23	H1	5	5	12	F1	23	H1	PH0-OSC_IN (PH0)	I/O	FT	-	EVENTOUT	OSC_IN
6	6	F16	13	G1	24	J1	6	6	13	G1	24	J1	PH1-OSC_OUT (PH1)	I/O	FT		EVENTOUT	OSC_OUT
7	7	G17	14	G2	25	HЗ	7	7	14	G2	25	HЗ	NRST	I/O	RST	-	-	-
-	8	F14	15	H2	26	J2	1	8	15	H2	26	J2	PC0	I/O	FT_ fha	ı	LPTIM1_IN1, OCTOSPIM_P1_IO7, I2C3_SCL(boot), SPI2_RDY, MDF1_SDI4, LPUART1_RX, SDMMC1_D5, SAI2_FS_A, LPTIM2_IN1, EVENTOUT	ADC1_IN1, ADC4_IN1
-	9	G15	16	G3	27	J3	-	9	16	G3	27	J3	PC1	I/O	FT_ fhav	1	TRACED0, LPTIM1_CH1, SPI2_MOSI, I2C3_SDA(boot), MDF1_CKI4, LPUART1_TX, OCTOSPIM_P1_IO4, SDMMC2_CK, SAI1_SD_A, EVENTOUT	ADC1_IN2, ADC4_IN2
-	10	F12	17	F3	28	J4	-	10	17	F3	28	J4	PC2	I/O	FT_ha	1	LPTIM1_IN2, SPI2_MISO, MDF1_CCK1, OCTOSPIM_P1_IO5, LPGPIO1_P5, EVENTOUT	ADC1_IN3, ADC4_IN3
-	11	G13	18	F4	29	K1	-	11	18	F4	29	K1	PC3	I/O	FT_ha	ı	LPTIM1_ETR, LPTIM3_CH1, SAI1_D1, SPI2_MOSI, OCTOSPIM_P1_IO6, SAI1_SD_A, LPTIM2_ETR, EVENTOUT	ADC1_IN4, ADC4_IN4
8	12	H18	19	H1	30	K2	8	12	19	H1	30	K2	VSSA	S	-	-	-	-

| | Table 26. STM3 | | | | | | | | | | | | x pin definition | s ⁽¹⁾ | (contin | ued | 1) | |------------------------------|----------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|----------------------------------------------------------------------------------------------------------------------------------------|-----------------------------------------------------------------------| | | | | | | Pin | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | - | - | - | - | - | - | 20 | - | 31 | - | VREF- | S | - | 1 | - | - | | - | - | H16 | 20 | J1 | 31 | L1 | 1 | 1 | 21 | J1 | 32 | L1 | VREF+ | S | - | 1 | - | VREFBUF_
OUT | | 9 | 13 | J17 | 21 | K1 | 32 | L2 | 9 | 13 | 22 | K1 | 33 | L2 | VDDA | S | - | - | - | - | | 10 | 14 | G11 | 22 | J2 | 33 | KЗ | 10 | 14 | 23 | J2 | 34 | KЗ | PA0 | I/O | FT_
hat | 1 | TIM2_CH1, TIM5_CH1, TIM8_ETR, SPI3_RDY, USART2_CTS, UART4_TX, OCTOSPIM_P2_NCS, SDMMC2_CMD, AUDIOCLK, TIM2_ETR, EVENTOUT | OPAMP1_
VINP,
ADC1_IN5,
WKUP1,
TAMP_IN2/
TAMP_
OUT1 | | - | - | - | - | HЗ | - | M1 | - | ı | - | HЗ | - | M1 | OPAMP1_
VINM | I | TT | - | - | - | | 11 | 15 | J13 | 23 | G4 | 34 | L3 | 11 | 15 | 24 | G4 | 35 | L3 | PA1 | I/O | FT_
hat | 1 | LPTIM1_CH2, TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS/USART2_DE, UART4_RX, OCTOSPIM_P1_DQS, LPGPIO1_P0, TIM15_CH1N, EVENTOUT | OPAMP1_
VINM,
ADC1_IN6,
WKUP3,
TAMP_IN5/
TAMP_
OUT4 | | 12 | 16 | J15 | 24 | K2 | 35 | M2 | 12 | 16 | 25 | K2 | 36 | M2 | PA2 | I/O | FT_ha | - | TIM2_CH3, TIM5_CH3, SPI1_RDY, USART2_TX(boot), | COMP1_
INP3,
ADC1_IN7,
WKUP4/
LSCO |

| 1 | |----------|--| | | | | | | | | | Tabl | le 26. | STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | uec | 1) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|-----------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------------------| | | | | | | Pin | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | 13 | 17 | H10 | 25 | L1 | 36 | N2 | 13 | 17 | 26 | L1 | 37 | N2 | PA3 | I/O | TT_
hav | 1 | TIM2_CH4, TIM5_CH4, SAI1_CK1, USART2_RX(boot), | OPAMP1_
VOUT,
ADC1_IN8,
WKUP5 | | - | 18 | K18 | 26 | G7 | 37 | M3 | - | 18 | 27 | G7 | 38 | M3 | VSS | S | - | - | - | - | | - | 19 | K16 | 27 | G6 | 38 | N3 | - | 19 | 28 | G6 | 39 | N3 | VDD | S | - | - | - | - | | 14 | 20 | H14 | 28 | L3 | 39 | N1 | 14 | 20 | 29 | L3 | 40 | N1 | PA4 | I/O | TT_ha | 1 | OCTOSPIM_P1_NCS, SPI1_NSS(boot), SPI3_NSS, USART2_CK, DCMI_HSYNC/PSSI_DE, SAI1_FS_B, LPTIM2_CH1, EVENTOUT | ADC1_IN9,
ADC4_IN9,
DAC1_
OUT1,
WKUP2 | | 15 | 21 | H12 | 29 | M1 | 40 | K4 | 15 | 21 | 30 | M1 | 41 | K4 | PA5 | I/O | TT_a | 1 | CSLEEP, TIM2_CH1, TIM2_ETR,
TIM8_CH1N, PSSI_D14,
SPI1_SCK(boot), USART3_RX,
LPTIM2_ETR, EVENTOUT | ADC1_IN10,
ADC4_IN10,
DAC1_
OUT2,
WKUP6 | | 16 | 22 | F10 | 30 | L2 | 41 | N4 | 16 | 22 | 31 | L2 | 42 | N4 | PA6 | I/O | FT_ha | - | CDSTOP, TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK/PSSI_PDCK, SPI1_MISO(boot), USART3_CTS, LPUART1_CTS, OCTOSPIM_P1_IO3, LPGPIO1_P2, TIM16_CH1, EVENTOUT | OPAMP2_
VINP,
ADC1_IN11,
ADC4_IN11,
WKUP7 |

| | | | | | | | | Tab | le 26 | STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | ued | ) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|--------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------------------------------------------------------| | | | | | | Pin | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | SAMS 064SDTM | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | | | - | M2 | - | H5 | - | - | - | M2 | - | H5 | OPAMP2_VINM | I | TT | - | - | - | | 17 | 23 | K14 | 31 | KЗ | 42 | J5 | 17 | 23 | 32 | KЗ | 43 | J5 | PA7 | I/O | FT_
fha | - | SRDSTOP, TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, SPI1_MOSI(boot), USART3_TX, OCTOSPIM_P1_IO2, LPTIM2_CH2, TIM17_CH1, EVENTOUT | OPAMP2_
VINM,
ADC1_IN12,
ADC4_IN20,
WKUP8 | | - | - | - | - | MЗ | - | L4 | - | 24 | 33 | MЗ | 44 | L4 | PC4 | I/O | FT_ha | - | USART3_TX,
OCTOSPIM_P1_IO7,
EVENTOUT | COMP1_
INM2,
ADC1_IN13,
ADC4_IN22 | | - | - | G9 | - | J3 | - | M4 | - | 25 | 34 | J3 | 45 | M4 | PC5 | I/O | FT_at | - | TIM1_CH4N, SAI1_D3,
PSSI_D15, USART3_RX,
EVENTOUT | COMP1_
INP1,
ADC1_IN14,
ADC4_IN23,
WKUP5,
TAMP_IN4/
TAMP_
OUT5 | | 18 | 24 | K12 | 32 | M4 | 43 | K5 | 18 | 26 | 35 | M4 | 46 | K5 | PB0 | I/O | TT_ha | - | TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LPTIM3_CH1,
SPI1_NSS, USART3_CK,
OCTOSPIM_P1_IO1,
LPGPIO1_P9, COMP1_OUT,
AUDIOCLK, EVENTOUT | OPAMP2_
VOUT,
ADC1_IN15,
ADC4_IN18 |

Table 26. STM32U575xx pin definitions⁽¹⁾ (continued)

| | | | | | Pin | num | ber | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|----------|---------------|-------|--------------------------------------------------------------------------------------------------------------------------------------------------------|------------------------------------------------------| | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | 19 | 25 | J11 | 33 | L4 | 44 | N5 | 19 | 27 | 36 | L4 | 47 | N5 | PB1 | I/O | FT_ha | 1 | TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LPTIM3_CH2, MDF1_SDI0, USART3_RTS/USART3_DE, LPUART1_RTS/LPUART1_DE, OCTOSPIM_P1_IO0, LPGPIO1_P3, LPTIM2_IN1, EVENTOUT | COMP1_
INM1,
ADC1_IN16,
ADC4_IN19,
WKUP4 | | - | 26 | K10 | 34 | K4 | 45 | L5 | 20 | 28 | 37 | K4 | 48 | L5 | PB2 | I/O | FT_
hat | 1 | LPTIM1_CH1, TIM8_CH4N, I2C3_SMBA, SPI1_RDY, MDF1_CKI0, OCTOSPIM_P1_DQS, UCPD1_FRSTX1, EVENTOUT | COMP1_
INP2,
ADC1_IN17,
WKUP1,
RTC_OUT2 | | - | - | - | - | K5 | 46 | M5 | 1 | - | 1 | K5 | 49 | M5 | PF11 | I/O | FT_hv | 1 | OCTOSPIM_P1_NCLK,
DCMI_D12/PSSI_D12,
LPTIM4_IN1, EVENTOUT | - | | - | - | - | - | L5 | 47 | K6 | ı | - | 1 | L5 | 50 | K6 | PF12 | I/O | FT_h | 1 | OCTOSPIM_P2_DQS, FMC_A6,
LPTIM4_ETR, EVENTOUT | - | | - | - | - | - | - | 48 | M7 | - | - | - | - | 51 | M7 | VSS | S | - | - | - | - | | - | - | - | - | - | 49 | N7 | - | - | - | - | 52 | N7 | VDD | S | - | - | - | - | | - | - | - | ı | M5 | 50 | M6 | - | - | ı | M5 | 53 | M6 | PF13 | I/O | FT_h | 1 | I2C4_SMBA, UCPD1_FRSTX2,
FMC_A7, LPTIM4_OUT,
EVENTOUT | - | | - | - | - | - | J5 | 51 | L6 | - | - | - | J5 | 54 | L6 | PF14 | I/O | FT_
fha | - | I2C4_SCL, TSC_G8_IO1,
FMC_A8, EVENTOUT | ADC4_IN5 |

| | | | | | | | | Tab | le 26. | STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | uec | i) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|-----------------------------------------------------------------------------------------------------------------|----------------------| | | | | | | Pir | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | - | L6 | 52 | N6 | - | - | - | L6 | 55 | N6 | PF15 | I/O | FT_
fha | - | I2C4_SDA, TSC_G8_IO2,
FMC_A9, EVENTOUT | ADC4_IN6 | | - | - | - | - | M6 | 53 | J6 | 1 | - | - | M6 | 56 | J6 | PG0 | I/O | FT_ha | - | OCTOSPIM_P2_IO4,
TSC_G8_IO3, FMC_A10,
EVENTOUT | ADC4_IN7 | | - | - | - | - | K6 | 54 | H7 | - | - | - | K6 | 57 | H7 | PG1 | I/O | FT_ha | - | OCTOSPIM_P2_IO5,
TSC_G8_IO4, FMC_A11,
EVENTOUT | ADC4_IN8 | | - | - | H8 | 35 | K7 | 55 | L7 | 1 | - | 38 | K7 | 58 | L7 | PE7 | I/O | FT_h | - | TIM1_ETR, MDF1_SDI2,
FMC_D4/FMC_AD4, SAI1_SD_B,
EVENTOUT | WKUP6 | | - | - | J9 | 36 | J6 | 56 | K7 | 1 | - | 39 | J6 | 59 | K7 | PE8 | I/O | FT_h | - | TIM1_CH1N, MDF1_CKI2,
FMC_D5/FMC_AD5,
SAI1_SCK_B, EVENTOUT | WKUP7 | | - | - | K8 | 37 | M7 | 57 | J7 | - | - | 40 | M7 | 60 | J7 | PE9 | I/O | FT_hv | - | TIM1_CH1, ADF1_CCK0, | - | | - | - | - | - | - | 58 | - | - | ı | - | 1 | 61 | ı | VSS | S | - | - | - | - | | - | - | - | - | J4 | 59 | - | - | - | - | J4 | 62 | - | VDD | S | - | - | - | - | | - | - | J7 | 38 | J7 | 60 | H8 | - | - | 41 | J7 | 63 | H8 | PE10 | I/O | FT_
hav | - | TIM1_CH2N, ADF1_SDI0,
MDF1_SDI4, TSC_G5_IO1,
OCTOSPIM_P1_CLK,
FMC_D7/FMC_AD7,
SAI1_MCLK_B, EVENTOUT | - |

Table 26. STM32U575xx pin definitions(1) (continued)

| | | | | | P
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Pinout, pin description and alternate functions

| | | | | | | | | Tab | le 26. | STN | 132U | 575xx | x pin definition | s ⁽¹⁾ | (contin | ued | l) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|---------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------| | | | | | | Pir | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | SAMS 064SDTM | Sdws 001ddd7 | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | 27 | H6 | 44 | K9 | 66 | K9 | 21 | 29 | 47 | K9 | 69 | K9 | PB10 | I/O | FT_
fhv | - | TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL(boot), SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, OCTOSPIM_P1_CLK, LPGPIO1_P4, COMP1_OUT, SAI1_SCK_A, EVENTOUT | WKUP8 | | - | 1 | 1 | 45 | L9 | 67 | L9 | - | 1 | - | L9 | 1 | L9 | PB11 | I/O | FT_fh | - | TIM2_CH4, I2C4_SDA, I2C2_SDA(boot), SPI2_RDY, USART3_RX, LPUART1_TX, OCTOSPIM_P1_NCS, COMP2_OUT, EVENTOUT | - | | 20 | 28 | K6 | 46 | M10 | 68 | N9 | - | ı | - | - | - | - | VLXSMPS | S | - | - | - | - | | 21 | 29 | K4 | 47 | M9 | 69 | N10 | - | - | - | - | - | - | VDDSMPS | S | - | - | - | - | | 22 | 30 | J5 | 48 | L10 | 70 | M10 | - | ı | - | - | - | - | VSSSMPS | S | - | - | - | - | | _ | - | - | - | - | - | - | 22 | 30 | 48 | L10 | 70 | N11 | VCAP | S | - | - | - | - | | 23 | 31 | K2 | 49 | M11 | 71 | N11 | - | - | - | - | - | - | VDD11 | S | - | - | - | - | | 24 | 32 | J3 | 50 | E9 | 72 | M11 | 23 | 31 | 49 | E9 | 71 | M11 | VSS | S | - | - | - | - | | 25 | 33 | J1 | 51 | D4 | 73 | N12 | 24 | 32 | 50 | D4 | 72 | N12 | VDD | S | - | - | - | - |

Pin number structure LQFP48 SMPS UFQFPN48 SMPS UFBGA132 SMPS UFBGA169 SMPS SMPS LQFP100 SMPS LQFP144 SMPS LQFP64 SMPS Pin type LQFP48 UFQFPN48 Pin name Notes UFBGA132 UFBGA169 LQFP100 LQFP144 Additional LQFP64 (function after Alternate functions functions WLCSP90 reset) 0 TIM1 BKIN, I2C2 SMBA, SPI2 NSS(boot), MDF1 SDI1, USART3 CK, FT_ LPUART1 RTS/LPUART1 DE. L11 L10 25 33 51 73 L10 PB12 I/O L11 TSC G1 IO1, hav OCTOSPIM P1 NCLK, SAI2 FS A, TIM15 BKIN, EVENTOUT TIM1 CH1N, LPTIM3 IN1, I2C2 SCL, SPI2 SCK(boot), MDF1 CKI1, USART3 CTS, I/O FT_fa 52 K10 74 N13 26 34 52 K10 74 N13 PB13 LPUART1 CTS, TSC G1 IO2, SAI2 SCK A, TIM15 CH1N, EVENTOUT TIM1 CH2N, LPTIM3 ETR, TIM8 CH2N, I2C2 SDA, SPI2 MISO(boot), MDF1 SDI2, $FT_{-}$ UCPD1 USART3 RTS/USART3 DE, K11 75 M12 27 35 K11 75 M12 PB14 I/O 35 H4 53 fda DBCC2 TSC G1 IO3, SDMMC2 D0, SAI2_MCLK_A, TIM15_CH1, EVENTOUT RTC REFIN, TIM1 CH3N, LPTIM2 IN2, TIM8 CH3N, UCPD1 SPI2 MOSI(boot), MDF1 CKI2, FT_c G5 K12 76 L11 36 54 K12 76 L11 PB15 I/O CC2, FMC NBL1, SDMMC2 D1, WKUP7 SAI2_SD_A, TIM15_CH2, EVENTOUT

Table 26. STM32U575xx pin definitions⁽¹⁾ (continued)

| | | | | | | | | Tab | le 26. | STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | ued | ) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|--------------------------------------------------------------------------------------------------------|-------------------------| | | I | I | I | ı | Pir | num | ber | | | | | 1 | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | - | 55 | L12 | 77 | L12 | 1 | ı | 55 | L12 | 77 | L12 | PD8 | I/O | FT_h | 1 | USART3_TX,
DCMI_HSYNC/PSSI_DE,
FMC_D13/FMC_AD13,
EVENTOUT | - | | - | - | - | 56 | J10 | 78 | L13 | 1 | 1 | 56 | J10 | 78 | L13 | PD9 | I/O | FT_h | 1 | LPTIM2_IN2, USART3_RX, DCMI_PIXCLK/PSSI_PDCK, FMC_D14/FMC_AD14, SAI2_MCLK_A, LPTIM3_IN1, EVENTOUT | - | | - | - | - | 57 | M12 | 79 | K11 | 1 | 1 | 57 | M12 | 79 | K11 | PD10 | I/O | FT_ha | - | LPTIM2_CH2, USART3_CK,
TSC_G6_IO1,
FMC_D15/FMC_AD15,
SAI2_SCK_A, LPTIM3_ETR,
EVENTOUT | - | | - | - | - | 58 | J11 | 80 | M13 | - | 1 | 58 | J11 | 80 | M13 | PD11 | I/O | FT_ha | - | I2C4_SMBA, USART3_CTS,
TSC_G6_IO2,
FMC_CLE/FMC_A16,
SAI2_SD_A, LPTIM2_ETR,
EVENTOUT | ADC4_IN15 | | - | - | - | 59 | J12 | 81 | K10 | - | - | 59 | J12 | 81 | K10 | PD12 | I/O | FT_
fha | - | TIM4_CH1, I2C4_SCL, USART3_RTS/USART3_DE, TSC_G6_IO3, FMC_ALE/FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT | ADC4_IN16 |

Table 26. STM32U575xx pin definitions⁽¹⁾ (continued)

| | | | | | Pir | num | ber | |-------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|----------|---------------|-------|------------------------------------------------------------------------------------------------|-------------------------| | LQFP48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | - | 60 | H11 | 82 | K12 | - | - | 60 | H11 | 82 | K12 | PD13 | I/O | FT_
fha | - | TIM4_CH2, I2C4_SDA,
TSC_G6_IO4, LPGPIO1_P6,
FMC_A18, LPTIM4_IN1,
LPTIM2_CH1, EVENTOUT | ADC4_IN17 | | - | - | - | - | - | 83 | J12 | - | - | - | - | 83 | J12 | VSS | S | - | - | - | - | | - | - | - | - | - | 84 | J13 | - | - | - | - | 84 | J13 | VDD | S | - | - | - | - | | - | - | G1 | 61 | H10 | 85 | J10 | 1 | - | 61 | H10 | 85 | J10 | PD14 | I/O | FT_h | - | TIM4_CH3, FMC_D0/FMC_AD0,
LPTIM3_CH1, EVENTOUT | - | | - | - | G3 | 62 | H12 | 86 | J11 | - | - | 62 | H12 | 86 | J11 | PD15 | I/O | FT_h | - | TIM4_CH4, FMC_D1/FMC_AD1,
LPTIM3_CH2, EVENTOUT | - | | - | - | - | - | G10 | 87 | K13 | - | - | - | G10 | 87 | K13 | PG2 | I/O | FT_hs | - | SPI1_SCK, FMC_A12,
SAI2_SCK_B, EVENTOUT | - | | - | - | - | - | G11 | 88 | J8 | - | - | - | G11 | 88 | J8 | PG3 | I/O | FT_hs | - | SPI1_MISO, FMC_A13,
SAI2_FS_B, EVENTOUT | - | | - | - | - | - | G9 | 89 | H11 | - | - | - | G9 | 89 | H11 | PG4 | I/O | FT_hs | - | SPI1_MOSI, FMC_A14,
SAI2_MCLK_B, EVENTOUT | - | | - | - | - | - | G12 | 90 | J9 | - | - | - | G12 | 90 | J9 | PG5 | I/O | FT_hs | - | SPI1_NSS, LPUART1_CTS,
FMC_A15, SAI2_SD_B,
EVENTOUT | - | | - | - | - | - | F9 | 91 | H10 | - | - | - | F9 | 91 | H10 | PG6 | I/O | FT_hs | - | OCTOSPIM_P1_DQS,
I2C3_SMBA, SPI1_RDY,
LPUART1_RTS/LPUART1_DE,
UCPD1_FRSTX1, EVENTOUT | - |

Pinout, pin description and alternate functions

| | | | | | | | | Tab | le 26 | STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | uec | i) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|---------------------------------------------------------------------------------------------------------------------------------------------|-------------------------| | | ı | ı | | 1 | Pir | num | ber | | ı | | | ı | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | - | - | F10 | 92 | G8 | 1 | - | - | F10 | 92 | G8 | PG7 | I/O | FT_fhs | - | SAI1_CK1, I2C3_SCL, OCTOSPIM_P2_DQS, MDF1_CCK0, LPUART1_TX, UCPD1_FRSTX2, FMC_INT, SAI1_MCLK_A, EVENTOUT | , | | - | - | - | - | F12 | 93 | H9 | 1 | - | - | F12 | 93 | H9 | PG8 | I/O | FT_fs | ı | I2C3_SDA, LPUART1_RX,
EVENTOUT | - | | - | - | - | - | - | 94 | - | - | - | - | - | 94 | - | VSS | S | - | - | - | - | | - | - | - | - | - | 95 | H12 | - | - | - | - | 95 | H12 | VDDIO2 | S | - | 1 | - | - | | - | 37 | G7 | 63 | F11 | 96 | H13 | 1 | 37 | 63 | F11 | 96 | H13 | PC6 | I/O | FT_a | - | CSLEEP, TIM3_CH1, TIM8_CH1, MDF1_CKI3, SDMMC1_D0DIR, | - | | - | 38 | F4 | 64 | E10 | 97 | G12 | 1 | 38 | 64 | E10 | 97 | G12 | PC7 | I/O | FT_a | 1 | CDSTOP, TIM3_CH2, TIM8_CH2, MDF1_SDI3, SDMMC1_D123DIR, TSC_G4_IO2, DCMI_D1/PSSI_D1, SDMMC2_D7, SDMMC1_D7, SAI2_MCLK_B, LPTIM2_CH2, EVENTOUT | - |

Table 26. STM32U575xx pin definitions(1) (continued)

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								Tab	le 26	. STN	132U	575x	x pin definition	s ⁽¹⁾	(contin	ued	)	,
					Pin	num	ber
LQFP48 SMPS UFQFPN48 SMPS	LQFP64 SMPS	WLCSP90 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	UFBGA169 SMPS	LQFP48 UFQFPN48	LQFP64	00FP100	UFBGA132	LQFP144	UFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
32	44	E3	70	C12	103	G13	32	44	70	C12	103	G13	PA11	I/O	FT_u	1	TIM1_CH4, TIM1_BKIN2, SPI1_MISO, USART1_CTS, FDCAN1_RX, EVENTOUT	OTG_FS_ DM(boot)
33	45	D2	71	B12	104	F13	33	45	71	B12	104	F13	PA12	I/O	FT_u	-	TIM1_ETR, SPI1_MOSI, OCTOSPIM_P2_NCS, USART1_RTS/USART1_DE, FDCAN1_TX, EVENTOUT	OTG_FS_ DP(boot)
34	46	D4	72	C10	105	F12	34	46	72	C10	105	F12	PA13 (JTMS/ SWDIO)	I/O	FT	(5)	JTMS/SWDIO, IR_OUT, OTG_FS_NOE, SAI1_SD_B, EVENTOUT	-
-	47	-	-	-	1	-	ı	47	1	-	1	-	VSS	S	ı	ı	-	-
-	48	C1	73	A12	106	E13	-	48	73	A12	106	E13	VDDUSB	S	ı	ı	-	-
35	-	B2	74	H4	107	E12	35	ı	74	H4	107	E12	VSS	S	-	ı	-	-
36	-	A1	75	D9	108	D13	36	ı	75	D9	108	D13	VDD	S	ı	ı	-	-
37	49	C3	76	C11	109	C10	37	49	76	C11	109	C10	PA14 (JTCK/ SWCLK)	I/O	FT	(5)	JTCK/SWCLK, LPTIM1_CH1, I2C1_SMBA, I2C4_SMBA, OTG_FS_SOF, SAI1_FS_B, EVENTOUT	-
38	50	E5	77	A11	110	A10	38	50	77	A11	110	A10	PA15 (JTDI)	I/O	FT_c	(4) (5)	JTDI, TIM2_CH1, TIM2_ETR, USART2_RX, SPI1_NSS, SPI3_NSS, USART3_RTS/USART3_DE, UART4_RTS/UART4_DE, SAI2_FS_B, EVENTOUT	UCPD1_ CC1

DS13737 Rev 10

777

Table 26. STM32U575xx pin definitions⁽¹⁾ (continued) Pin number structure LQFP48 SMPS UFQFPN48 SMPS UFBGA132 SMPS UFBGA169 SMPS SMPS LQFP100 SMPS LQFP144 SMPS LQFP64 SMPS Pin type LQFP48 UFQFPN48 Pin name Notes UFBGA132 UFBGA169 LQFP100 LQFP144 Additional LQFP64 (function after Alternate functions functions WLCSP90 reset) 0 TRACED1, LPTIM3 ETR, ADF1 CCK1, SPI3 SCK, USART3 TX(boot), UART4 TX, TSC G3 IO2. E7 78 B11 111 C9 51 78 B11 111 C9 PC10 I/O FT_a DCMI D8/PSSI D8, LPGPIO1 P8, SDMMC1 D2, SAI2 SCK B, EVENTOUT LPTIM3 IN1, ADF1 SDI0, DCMI D2/PSSI D2. OCTOSPIM P1 NCS. SPI3 MISO, USART3 RX(boot), I/O FT_ha 79 A10 112 Α9 52 79 A10 112 A9 PC11 UART4 RX, TSC G3 IO3, DCMI D4/PSSI D4. UCPD1 FRSTX2, SDMMC1 D3, SAI2 MCLK B, EVENTOUT TRACED3, SPI3 MOSI, USART3 CK, UART5 TX, FT_ TSC G3 IO4, B10 B10 113 E8 53 80 113 PC12 I/O DCMI D9/PSSI D9. hav LPGPIO1 P10, SDMMC1 CK, SAI2 SD B, EVENTOUT TIM8 CH4N, SPI2 NSS, FDCAN1 RX, C9 PD0 I/O FT h C5 81 114 B9 81 C9 114 B9 FMC D2/FMC AD2, EVENTOUT SPI2 SCK, FDCAN1 TX, 82 B9 115 F6 B9 115 I/O D6 82 F6 PD1 $FT_h$ FMC D3/FMC AD3, EVENTOUT

| | | | | | | | | Tab | le 26. | STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | uec | 1) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|----------------------------------------------------------------------------------------------------------------------------------------|----------------------| | | | | | | Pin | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | 54 | A5 | 83 | A9 | 116 | F7 | ı | 54 | 83 | A9 | 116 | F7 | PD2 | I/O | FT | 1 | TRACED2, TIM3_ETR, USART3_RTS/USART3_DE, UART5_RX, TSC_SYNC, DCMI_D11/PSSI_D11, LPGPIO1_P7, SDMMC1_CMD, LPTIM4_ETR, EVENTOUT | - | | - | - | - | 84 | C8 | 117 | D8 | 1 | 1 | 84 | C8 | 117 | D8 | PD3 | I/O | FT_hv | 1 | SPI2_SCK, DCMI_D5/PSSI_D5,
SPI2_MISO, MDF1_SDI0,
USART2_CTS,
OCTOSPIM_P2_NCS,
FMC_CLK, EVENTOUT | - | | - | - | D8 | 85 | B8 | 118 | C8 | - | - | 85 | B8 | 118 | C8 | PD4 | I/O | FT_h | - | SPI2_MOSI, MDF1_CKI0,
USART2_RTS/USART2_DE,
OCTOSPIM_P1_IO4, FMC_NOE,
EVENTOUT | - | | - | - | B6 | 86 | A8 | 119 | E7 | 1 | - | 86 | A8 | 119 | E7 | PD5 | I/O | FT_h | - | SPI2_RDY, USART2_TX,
OCTOSPIM_P1_IO5, FMC_NWE,
EVENTOUT | - | | - | - | - | - | - | 120 | B8 | - | - | - | - | 120 | B8 | VSS | S | - | - | - | - | | - | - | - | - | - | 121 | A8 | - | ı | ı | - | 121 | A8 | VDD | S | - | - | - | | - | - | - | 87 | A7 | 122 | B7 | - | - | 87 | A7 | 122 | B7 | PD6 | I/O | FT_hv | - | SAI1_D1, DCMI_D10/PSSI_D10,
SPI3_MOSI, MDF1_SDI1,
USART2_RX,
OCTOSPIM_P1_IO6,
SDMMC2_CK, FMC_NWAIT,
SAI1_SD_A, EVENTOUT | - |

1
---

- - 88 D7 123 D7 - - 88 D7 123 D7 PD7 I/O FT_h - MDF1_CKI1, USART2_CK, OCTOSPIM_P1_IO7, SDMMC2_CMD, FMC_NCE/FMC_NE1, LPTIM4_OUT, EVENTOUT - C7 - B7 124 A7 - - - B7 124 A7 PG9 I/O FT_hs - OCTOSPIM_P2_IO6, SPI3_SCK(boot), USART1_TX, FMC_NCE/FMC_NE2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT - A7 - C7 125 C7 - - - C7 125 C7 PG10 I/O FT_hs - LPTIM1_IN1, OCTOSPIM_P2_IO7, SPI3_MISO(boot), USART1_RX, FMC_NE3, SAI2_FS_A, TIM15_CH1, EVENTOUT - E9 - - - - - - - M11 126 M10 PG11 I/O FT_hs - LPTIM1_IN2, OCTOSPIM_P1_IO5, SPI3_MOSI, USART1_CTS, SAI2_MCLK_A, TIM15_CH2, EVENTOUT - B8 - A6 126 E6 - - - A6 127 E6 PG12 I/O FT_hs - LPTIM1_ETR, OCTOSPIM_P2_NCS, SPI3_NSS(boot), USART1_RTS/USART1_DE, FMC_NE4, SAI2_SD_A, EVENTOUTTable 26. STM32U575xx pin definitions(1) (continued) Pin numberPin name (function after reset) Pin type I/O structure Notes Alternate functions Additional functions LQFP48 SMPS UFQFPN48 SMPS LQFP64 SMPS WLCSP90 SMPS LQFP100 SMPS UFBGA132 SMPS LQFP144 SMPS UFBGA169 SMPS LQFP48 UFQFPN48 LQFP64 LQFP100 UFBGA132 LQFP144 UFBGA169

| | Table 26. STM3 | | | | | | | | | | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | uec | 1) | |------------------------------|----------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------| | | | | | | Pin | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | C9 | - | - | 127 | - | ı | - | - | M10 | 128 | N10 | PG13 | I/O | FT_fhs | - | I2C1_SDA, SPI3_RDY,
USART1_CK, FMC_A24,
EVENTOUT | - | | - | - | A9 | - | - | 128 | - | ı | - | - | M9 | 129 | N9 | PG14 | I/O | FT_fhs | - | LPTIM1_CH2, I2C1_SCL,
FMC_A25, EVENTOUT | - | | - | - | B10 | - | H9 | 129 | - | - | - | - | H9 | 130 | - | VSS | S | - | - | - | - | | - | - | A11 | - | D8 | 130 | A6 | - | - | - | D8 | 131 | A6 | VDDIO2 | S | - | - | - | - | | - | - | - | - | - | 131 | A5 | - | - | - | B4 | 132 | A5 | PG15 | I/O | FT_hs | - | LPTIM1_CH1, I2C1_SMBA,
OCTOSPIM_P2_DQS,
DCMI_D13/PSSI_D13,
EVENTOUT | - | | 39 | 55 | D10 | 89 | C6 | 132 | D6 | 39 | 55 | 89 | C6 | 133 | D6 | PB3
(JTDO/TRACES
WO) | I/O | FT_fa | - | JTDO/TRACESWO, TIM2_CH2,
LPTIM1_CH1, ADF1_CCK0,
I2C1_SDA, SPI1_SCK,
SPI3_SCK,
USART1_RTS/USART1_DE,
CRS_SYNC, LPGPIO1_P11,
SDMMC2_D2, SAI1_SCK_B,
EVENTOUT | COMP2_
INM2 |

Table 26. STM32U575xx pin definitions⁽¹⁾ (continued) Pin number structure LQFP48 SMPS UFQFPN48 SMPS UFBGA132 SMPS UFBGA169 SMPS WLCSP90 SMPS LQFP100 SMPS LQFP144 SMPS LQFP64 SMPS Pin type LQFP48 UFQFPN48 Pin name Notes UFBGA132 UFBGA169 LQFP100 LQFP144 Additional LQFP64 (function after Alternate functions functions reset) 0 NJTRST, LPTIM1 CH2, TIM3 CH1, ADF1 SDI0, I2C3 SDA, SPI1 MISO, SPI3 MISO, USART1 CTS, UART5 RTS/UART5 DE, COMP2 C11 90 133 B6 40 56 90 B6 134 B6 PB4 (NJTRST) I/O FT fa TSC G2 IO1. INP1 DCMI D12/PSSI D12, LPGPIO1 P12. SDMMC2 D3. SAI1 MCLK B, TIM17 BKIN, EVENTOUT LPTIM1 IN1, TIM3 CH2, OCTOSPIM P1 NCLK, I2C1 SMBA, SPI1 MOSI, UCPD1 SPI3 MOSI(boot), USART1 CK, FT_ I/O DBCC1. D12 91 D6 134 C6 91 D6 135 C6 PB5 41 57 41 57 havd UART5 CTS, TSC G2 IO2, WKUP6 DCMI D10/PSSI D10, COMP2 OUT, SAI1 SD B, TIM16 BKIN, EVENTOUT LPTIM1 ETR, TIM4 CH1, TIM8 BKIN2, I2C1 SCL(boot), COMP2 I2C4 SCL, MDF1 SDI5, A13 92 A5 135 B5 42 58 92 136 B5 PB6 I/O FT fa INP2, A5 USART1 TX, TSC G2 IO3, WKUP3 DCMI D5/PSSI D5, SAI1 FS B, TIM16_CH1N, EVENTOUT

| | | | | | | | | Tabl | le 26. | STN | 132U | 575x | x pin definition | s ⁽¹⁾ | (contin | ued | I) | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|-----------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------------------| | | | | | | Pin | num | ber | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | 43 | 59 | B12 | 93 | D5 | 136 | F5 | 43 | 59 | 93 | D5 | 137 | F5 | PB7 | I/O | FT_
fhav | - | LPTIM1_IN2, TIM4_CH2, TIM8_BKIN, I2C1_SDA(boot), I2C4_SDA, MDF1_CKI5, USART1_RX, UART4_CTS, TSC_G2_IO4, DCMI_VSYNC/PSSI_RDY, FMC_NL, TIM17_CH1N, EVENTOUT | COMP2_
INM1,
PVD_IN,
WKUP4 | | 44 | 60 | C13 | 94 | B5 | 137 | C5 | 44 | 60 | 94 | B5 | 138 | C5 | PH3-BOOT0 | I/O | FT | - | EVENTOUT | - | | 45 | 61 | B14 | 95 | C5 | 138 | E5 | 45 | 61 | 95 | C5 | 139 | E5 | PB8 | I/O | FT_f | 1 | TIM4_CH3, SAI1_CK1, I2C1_SCL, MDF1_CCK0, SPI3_RDY, SDMMC1_CKIN, FDCAN1_RX(boot), DCMI_D6/PSSI_D6, SDMMC2_D4, SDMMC1_D4, SAI1_MCLK_A, TIM16_CH1, EVENTOUT | WKUP5 | | - | - | A15 | 96 | A4 | 139 | D5 | 46 | 62 | 96 | A4 | 140 | D5 | PB9 | I/O | FT_f | - | IR_OUT, TIM4_CH4, SAI1_D2, I2C1_SDA, SPI2_NSS, SDMMC1_CDIR, FDCAN1_TX(boot), DCMI_D7/PSSI_D7, SDMMC2_D5, SDMMC1_D5, SAI1_FS_A, TIM17_CH1, EVENTOUT | - | | - | - | - | 97 | C4 | 140 | D4 | - | - | 97 | C4 | 141 | D4 | PE0 | I/O | FT_h | - | TIM4_ETR, DCMI_D2/PSSI_D2,
LPGPIO1_P13, FMC_NBL0,
TIM16_CH1, EVENTOUT | - |

Table 26. STM32U575xx pin definitions⁽¹⁾ (continued)

| | | | | | Pir | num | ber | |------------------------------|-------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|----------|---------------|-------|---------------------------------------------------------------|----------------------| | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | ı | A3 | 141 | C4 | 1 | - | 98 | A3 | 142 | C4 | PE1 | I/O | FT_h | - | DCMI_D3/PSSI_D3, FMC_NBL1,
TIM17_CH1, EVENTOUT | - | | - | - | - | - | - | - | - | - | ı | - | ı | - | A4 | VCAP | S | - | - | - | - | | 46 | 62 | A17 | 98 | B4 | 142 | A4 | ı | ı | ı | ı | - | - | VDD11 | S | ı | ı | - | - | | 47 | 63 | B16 | 99 | E4 | 143 | B4 | 47 | 63 | 99 | E4 | 143 | B4 | VSS | S | - | - | - | - | | 48 | 64 | B18 | 100 | J9 | 144 | A3 | 48 | 64 | 100 | J9 | 144 | A3 | VDD | S | - | - | - | - | | - | - | - | - | - | - | B11 | - | - | - | - | - | B11 | VSS | S | - | - | - | - | | - | - | - | - | - | - | F10 | - | - | - | - | - | F10 | PH2 | I/O | FT_h | - | OCTOSPIM_P1_IO4,
EVENTOUT | - | | - | - | - | - | - | - | E10 | - | - | - | - | - | E10 | PH4 | I/O | FT_fh | - | I2C2_SCL,
OCTOSPIM_P2_DQS,
PSSI_D14, EVENTOUT | - | | - | - | - | - | - | - | F9 | - | - | - | - | - | F9 | PH5 | I/O | FT_f | - | I2C2_SDA,
DCMI_PIXCLK/PSSI_PDCK,
EVENTOUT | - | | - | - | - | 1 | - | - | E11 | 1 | - | 1 | - | - | E11 | PH6 | I/O | FT_hv | - | I2C2_SMBA,
OCTOSPIM_P2_CLK,
DCMI_D8/PSSI_D8, EVENTOUT | - | | - | - | - | - | - | - | F8 | - | - | - | - | - | F8 | PH7 | I/O | FT_
fhv | - | I2C3_SCL,
OCTOSPIM_P2_NCLK,
DCMI_D9/PSSI_D9, EVENTOUT | - | | - | - | - | - | - | - | D12 | - | - | - | - | - | D12 | PH8 | I/O | FT_fh | - | I2C3_SDA, OCTOSPIM_P2_IO3,
DCMI_HSYNC/PSSI_DE,
EVENTOUT | - |

| | Table 26. STM3 | | | | | | | | | | | 575x | x pin definition | s ⁽¹⁾ | (contin | uec | 1) | |------------------------------|----------------|--------------|--------------|---------------|--------------|---------------|--------------------|--------|---------|----------|---------|----------|---------------------------------------|------------------|---------------|-------|---------------------------------------------------------------------------|-------------------------| | | 1 | 1 | , | 1 | Pir | n num | ber | 1 | 1 | 1 | 1 | , | | LQFP48 SMPS
UFQFPN48 SMPS | LQFP64 SMPS | WLCSP90 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | UFBGA169 SMPS | LQFP48
UFQFPN48 | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | UFBGA169 | Pin name
(function after
reset) | Pin type | I/O structure | Notes | Alternate functions | Additional
functions | | - | - | - | - | - | - | E9 | 1 | - | - | - | - | E9 | PH9 | I/O | FT_h | - | I2C3_SMBA,
OCTOSPIM_P2_IO4,
DCMI_D0/PSSI_D0, EVENTOUT | - | | - | - | - | - | - | - | C13 | - | - | - | - | - | C13 | PH10 | I/O | FT_h | - | TIM5_CH1, OCTOSPIM_P2_IO5,
DCMI_D1/PSSI_D1, EVENTOUT | - | | - | - | - | - | - | - | D9 | - | - | - | - | - | D9 | PH11 | I/O | FT_h | - | TIM5_CH2, OCTOSPIM_P2_IO6,
DCMI_D2/PSSI_D2, EVENTOUT | - | | - | - | - | - | - | - | B13 | - | - | - | - | - | B13 | PH12 | I/O | FT_h | - | TIM5_CH3, TIM8_CH4N,
OCTOSPIM_P2_IO7,
DCMI_D3/PSSI_D3, EVENTOUT | - | | - | - | - | - | - | - | C12 | - | - | - | - | - | C12 | PH13 | I/O | FT | - | TIM8_CH1N, FDCAN1_TX,
EVENTOUT | - | | - | - | - | - | - | - | C11 | - | - | - | - | - | C11 | PH14 | I/O | FT | - | TIM8_CH2N, FDCAN1_RX,
DCMI_D4/PSSI_D4, EVENTOUT | - | | - | - | - | - | - | - | A13 | - | - | - | - | - | A13 | PH15 | I/O | FT_h | - | TIM8_CH3N,
OCTOSPIM_P2_IO6,
DCMI_D11/PSSI_D11,
EVENTOUT | - | | - | - | - | - | - | - | A11 | - | - | - | - | - | A11 | VDD | S | - | - | - | - | | - | - | - | - | - | - | B12 | 1 | - | - | - | - | B12 | PI0 | I/O | FT_h | - | TIM5_CH4, OCTOSPIM_P1_IO5,
SPI2_NSS,
DCMI_D13/PSSI_D13,
EVENTOUT | - | | - | - | - | _ | - | - | A12 | - | - | - | - | - | A12 | Pl1 | I/O | FT_h | - | SPI2_SCK, OCTOSPIM_P2_IO2,
DCMI_D8/PSSI_D8, EVENTOUT | - |

Table 26. STM32U575xx pi	n definitions ⁽¹⁾	(continued)
--------------------------	------------------------------	-------------

	Table 20. 31 W											0.00				100	',	1
					Pir	num	ber
LQFP48 SMPS UFQFPN48 SMPS	LQFP64 SMPS	WLCSP90 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	UFBGA169 SMPS	LQFP48 UFQFPN48	LQFP64	LQFP100	UFBGA132	LQFP144	UFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	-	-	-	ı	-	D11	1	-	ī	1	-	D11	Pl2	I/O	FT_hv	-	TIM8_CH4, SPI2_MISO, OCTOSPIM_P2_IO1, DCMI_D9/PSSI_D9, EVENTOUT	-
-	-	-	1	1	-	D10	-	-	-	1	-	D10	PI3	I/O	FT_h	-	TIM8_ETR, SPI2_MOSI, OCTOSPIM_P2_IO0, DCMI_D10/PSSI_D10, EVENTOUT	-
-	-	-	-	-	-	B2	-	-	-	-	-	B2	VSS	S	-	-	-	-
-	-	-	-	-	-	B1	-	-	-	-	-	B1	VDD	S	-	-	-	-
-	-	-	-	-	-	B10	-	-	-	-	-	B10	PI4	I/O	FT	-	TIM8_BKIN, SPI2_RDY, DCMI_D5/PSSI_D5, EVENTOUT	-
-	-	-	-	-	-	B3	-	-	-	-	-	B3	PI5	I/O	FT_h	-	TIM8_CH1, OCTOSPIM_P2_NCS, DCMI_VSYNC/PSSI_RDY, EVENTOUT	-
-	-	-	-	-	-	A2	-	-	-	-	-	A2	Pl6	I/O	FT_hv	-	TIM8_CH2, OCTOSPIM_P2_CLK, DCMI_D6/PSSI_D6, EVENTOUT	-
-	-	-	-	-	-	C3	-	-	-	-	-	CЗ	PI7	I/O	FT_hv	-	TIM8_CH3, OCTOSPIM_P2_NCLK, DCMI_D7/PSSI_D7, EVENTOUT	-

^1. Function availability depends on the chosen device.

^2. PC13, PC14 and PC15 are supplied through the power switch (by V_SW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs in output mode is limited:

^- PC13 speed must not exceed 2 MHz with a maximum load of 30 pF. Refer to FT_o electrical characteristics for PC14, PC15.

^- These GPIOs must not be used as current sources (for example to drive a LED).

3. After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
4. After reset, a pull-down resistor (Rd = 5.1 kΩ from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15 (UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2). This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register.
5. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

4.3 Alternate functions

DS13737 Rev 10

132/346

Table 27	Alternate	function	AFO to	A F7(1)
Table 21.	Allemale	TUTICLION	AFU IU	AF/\

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
	Port	CRS/LPTIM1/ SYS_AF	LPTIM1/ TIM1/2/5/8	LPTIM1/2/3/ TIM1/2/3/4/5	ADF1/I2C4/ OCTOSPIM_P1/ OTG_FS/SAI1/ SPI2/TIM1/8/ USART2	DCMI/ I2C1/2/3/4/ LPTIM3	DCMI/I2C4/MDF1/ OCTOSPIM_P1/2/ SPI1/2/3	I2C3/MDF1/ OCTOSPIM_P2/ SPI3	USART1/2/3
	PA0	-	TIM2_CH1	TIM5_CH1	TIM8_ETR	-	-	SPI3_RDY	USART2_CTS
	PA1	LPTIM1_CH2	TIM2_CH2	TIM5_CH2	-	I2C1_SMBA	SPI1_SCK	-	USART2_ RTS/USART2_ DE
	PA2	-	TIM2_CH3	TIM5_CH3	-	-	SPI1_RDY	-	USART2_TX
	PA3	-	TIM2_CH4	TIM5_CH4	SAI1_CK1	-	-	-	USART2_RX
	PA4	-	-	-	OCTOSPIM_P1 _NCS	-	SPI1_NSS	SPI3_NSS	USART2_CK
	PA5	CSLEEP	TIM2_CH1	TIM2_ETR	TIM8_CH1N	PSSI_D14	SPI1_SCK	-	USART3_RX
	PA6	CDSTOP	TIM1_BKIN	TIM3_CH1	TIM8_BKIN	DCMI_PIXCL K/PSSI_ PDCK	SPI1_MISO	-	USART3_CTS
Port A	PA7	SRDSTOP	TIM1_CH1N	TIM3_CH2	TIM8_CH1N	I2C3_SCL	SPI1_MOSI	-	USART3_TX
ď	PA8	MCO	TIM1_CH1	-	SAI1_CK2	-	SPI1_RDY	-	USART1_CK
	PA9	-	TIM1_CH2	-	SPI2_SCK	-	DCMI_D0/PSSI_D0	-	USART1_TX
	PA10	CRS_SYNC	TIM1_CH3	LPTIM2_IN2	SAI1_D1	-	DCMI_D1/PSSI_D1	-	USART1_RX
	PA11	-	TIM1_CH4	TIM1_BKIN2	-	-	SPI1_MISO	-	USART1_CTS
	PA12	-	TIM1_ETR	-	-	-	SPI1_MOSI	OCTOSPIM_ P2_NCS	USART1_ RTS/USART1_ DE
	PA13	JTMS/SWDIO	IR_OUT	-	-	-	-	-	-
	PA14	JTCK/SWCLK	LPTIM1_CH1	-	-	I2C1_SMBA	I2C4_SMBA	-	-
	PA15	JTDI	TIM2_CH1	TIM2_ETR	USART2_RX	-	SPI1_NSS	SPI3_NSS	USART3_ RTS/USART3_ DE

Electrical Characteristics

The definition and values of output AC characteristics are given in Figure 37: Output AC characteristics definition and in the table below respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 32.

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in $V_{BAT}$ mode and FT_o I/Os $^{(1)}$ ) $^{(2)(3)(4)}$

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			$C_L = 50 \text{ pF}, 2.7 \text{ V} \le V_{DDIOX} \le 3.6 \text{ V}$	-	12.5
			C _L = 50 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	5
	Fmax	Maximum frequency	C _L = 50 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	1	- MHz
	Fillax	all I/Os	C _L = 10 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	12.5	IVITZ
			C _L = 10 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	5
00			C _L = 10 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	1
00			C _L = 50 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	17
			$C_L = 50 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	33
	t _r /t _f	Output rise and fall time	C _L = 50 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	85	ne
		all I/Os	C _L = 10 pF, 2.7 V ≤ V _DDIOX ≤ 3.6 V	-	12.5	ns
			$C_L = 10 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	25
			$C_L = 10 \text{ pF}, 1.08 \text{ V} \le V_{DDIOx} < 1.58 \text{ V}$	-	50
	Fmax	Maximum frequency	$C_L = 30 \text{ pF}, 2.7 \text{ V} \le V_{DDIOX} \le 3.6 \text{ V}$	-	55
			$C_L = 30 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} \le 2.7 \text{ V}$	-	12.5	– MHz
			$C_L = 30 \text{ pF}, 1.08 \text{ V} \le V_{DDIOx} < 1.58 \text{ V}$	-	2.5
	Tillax	all I/Os	$C_L = 10 \text{ pF}, 2.7 \text{ V} \le V_{DDIOx} \le 3.6 \text{ V}$	-	55
			$C_L = 10 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	12.5
01			$C_L = 10 \text{ pF}, 1.08 \text{ V} \le V_{DDIOx} \le 1.58 \text{ V}$	-	2.5
01			$C_L = 30 \text{ pF}, 2.7 \text{ V} \le V_{DDIOX} \le 3.6 \text{ V}$	-	5.8
			$C_L = 30 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	10	ns
	t _r /t _f	Output rise and fall time	$C_L = 30 \text{ pF}, 1.08 \text{ V} \le V_{DDIOX} < 1.58 \text{ V}$	-	18
	47 4	all I/Os	$C_L = 10 \text{ pF}, 2.7 \text{ V} \le V_{DDIOX} \le 3.6 \text{ V}$	-	4.2
			$C_L = 10 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	7.5
			$C_L = 10 \text{ pF}, 1.08 \text{ V} \le V_{DDIOX} < 1.58 \text{ V}$	-	12
Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in $V_{BAT}$ mode and FT_o I/Os⁽¹⁾)^(2)(3)(4) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			$C_L = 30 \text{ pF}, 2.7 \text{ V} \le V_{DDIOx} \le 3.6 \text{ V}$	-	100 ⁽⁵⁾
		Maximum frequency	C _L = 30 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	33 ⁽⁵⁾
	Fmax		C _L = 30 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	5
		all I/Os	C _L = 10 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	133 ⁽⁵⁾	MHz
			C _L = 10 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	40 ⁽⁵⁾
10			C _L = 10 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	5
10			C _L = 30 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	3.3 ⁽⁵⁾
			C _L = 30 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	6.0 ⁽⁵⁾
	4 /4	Output rise and fall time	C _L = 30 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	13.3	]
	t _r /t _f	all I/Os	C _L = 10 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	2 ⁽⁵⁾	ns
			C _L = 10 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	4.1 ⁽⁵⁾
			C _L = 10 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	9.2
		Maximum frequency All I/Os except FT_c, FT_v, and TT_v	C _L = 30 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	100 ⁽⁵⁾
			C _L = 30 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	33 ⁽⁵⁾
			C _L = 30 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	5
	Fmax		C _L = 10 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	133 ⁽⁵⁾	- MHz
			C _L = 10 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	40 ⁽⁵⁾
			C _L = 10 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	5
	Fillax		C _L = 30 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	140 ⁽⁵⁾
			C _L = 30 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	40 ⁽⁵⁾
11		Maximum frequency	C _L = 30 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	5
11		FT_v and TT_v I/Os	C _L = 10 pF, 2.7 V ≤ V _DDIOX ≤ 3.6 V	-	166 ⁽⁵⁾
			C _L = 10 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	50 ⁽⁵⁾
			$C_L = 10 \text{ pF}, 1.08 \text{ V} \le V_{DDIOX} < 1.58 \text{ V}$	-	5
			$C_L = 30 \text{ pF}, 2.7 \text{ V} \le V_{DDIOX} \le 3.6 \text{ V}$	-	3.3 ⁽⁵⁾
			$C_L = 30 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	6.0 ⁽⁵⁾
	t _r /t _f	Output rise and fall time	C _L = 30 pF, 1.08 V ≤ V _DDIOX < 1.58 V	-	13.3	ns
	ا لرا ل	All I/Os except FT_c, FT_v, and TT_v	C _L = 10 pF, 2.7 V ≤ V _DDIOX ≤ 3.6 V		2.0 ⁽⁵⁾	115
			C _L = 10 pF, 1.58 V ≤ V _DDIOX < 2.7 V		4.1 ⁽⁵⁾
			C _L = 10 pF, 1.08 V ≤ V _DDIOX < 1.58 V		9.2
Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c	,
-----------------------------------------------------------------------------------------------	---
FT_t in V _BAT mode and FT_o I/Os ⁽¹⁾ ) ^(2)(3)(4) (continued)
Speed	Symbol	Parameter	Conditions	Min	Max	Unit
--------------------------------------------	--------------------------------	---------------------------------	-----------------------------------------------------------------------	-----	---------------------	------
			C _L = 30 pF, 2.7 V ≤ V _DDIOx ≤ 3.6 V	-	2.5 ⁽⁵⁾
11 (cont'd) t _r /t _f			C _L = 30 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	5.0 ⁽⁵⁾
	1 /1	Output rise and fall time	C _L = 30 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	11
	ι _r /ι _f	FT_v and TT_v I/Os	$C_L = 10 \text{ pF}, 2.7 \text{ V} \le V_{DDIOx} \le 3.6 \text{ V}$	-	1.66 ⁽⁵⁾	ns
			C _L = 10 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	3.1 ⁽⁵⁾
			C _L = 10 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	7
	Fmax	Maximum frequency	$C_L = 550 \text{ pF}, 1.08 \text{ V} \le V_{DDIOx} < 3.6 \text{ V}$	-	1	MHz
			C _L = 100 pF, 1.58 V ≤ V _DDIOx < 3.6 V	-	50
Fm+	+	Output fall time ⁽⁶⁾	$C_L = 100 \text{ pF}, 1.08 \text{ V} \le V_{DDIOx} < 1.58 \text{ V}$	-	80	no
	t _f	Output fail time.	$C_L = 550 \text{ pF}, 1.58 \text{ V} \le V_{DDIOx} < 3.6 \text{ V}$	-	100	ns
			C _L = 550 pF, 1.08 V ≤ V _DDIOX < 1.58 V	-	220

FT_t I/O characteristics are degraded only in V_BAT mode (refer to Table 99). FT_o I/O characteristics are provided in this table for revision X devices. FT_o I/O characteristics are provided in Table 99 for all other device revisions.
1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register.
1. Specified by design. Not tested in production.
5. Compensation system enabled.
1. The fall time is defined between 70% and 30% of the output waveform accordingly to I²C specification.

Table 97. Output AC characteristics, HSLV ON (all I/Os except FT_c)^(1)(2)(3)(4)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
Fm			$C_L = 50 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	10
	Emay	Maximum frequency	C _L = 50 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	4	MHz
	Fillax		$C_L = 10 \text{ pF}, 1.58 \text{ V} \le V_{DDIOX} < 2.7 \text{ V}$	-	15	IVITIZ
00			C _L = 10 pF, 1.08 V ≤ V _DDIOX < 1.58 V	-	4
00		t _r /t _f Output rise and fall time	$C_L = 50 \text{ pF}, 1.58 \text{ V} \le V_{DDIOx} < 2.7 \text{ V}$	-	18
	+ /+-		C _L = 50 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	32	ns
	۲r/ ۲f		C _L = 10 pF, 1.58 V ≤ V _DDIOx < 2.7 V	-	12	113
			C _L = 10 pF, 1.08 V ≤ V _DDIOx < 1.58 V	-	21
Table 97. Output AC characteristics, HSLV ON (all I/Os except FT_c)(1)(2)(3)(4) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	50
			CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	10
	Fmax	Maximum frequency	CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	67	MHz
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	10
01			CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	5.3
		Output rise and fall time	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	10.6
	tr/tf		CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	3.1	ns
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	5.6
			CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	75(5)
			CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	15
	Fmax	Maximum frequency	CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	100(5)	MHz
10			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	15
			CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	4.4(5)
			CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	9.6	ns
		tr/tf Output rise and fall time	CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	2.2(5)
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	4.7
		Maximum frequency All I/Os except FT_c, FT_v, and TT_v	CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	75(5)
			CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	15
			CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	100(5)
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	15
11	Fmax		CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	110(5)	MHz
		Maximum frequency	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	25
		FT_v and TT_v I/Os	CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	150(5)
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	25
			CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	4.4(5)
		Output rise and fall time	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	9.6
		All I/Os except FT_c, FT_v, and TT_v	CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	2.2(5)
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	4.7
11	tr/tf		CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	3.0(5)	ns
		Output rise and fall time	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	6.6
		FT_v and TT_v I/Os	CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	1.6(5)
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	3.4
^1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

^2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register.

1. Specified by design. Not tested in production.
1. FT_t I/O characteristics are degraded only in VBAT mode (refer to Table 99).
5. Compensation system enabled.

Table 98. Output AC characteristics for FT_c I/Os(1)(2)

| Speed | Symbol | Parameter | Conditions | Min | Max | Unit | |-------|---------------------------|---------------------------|-------------------------------------------------|-------------------------------------------------|-----|------|-----| | | Fmax
Maximum frequency | | All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V | - | 10 | | | | | All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V | - | 5 | MHz | | 00 | tr/tf | | All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V | - | 33 | | | | | Output rise and fall time | All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V | - | 66 | ns | | | | Fmax | Maximum frequency | All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V | - | 25 | MHz | | 01 | | | All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V | - | 10 | | | | | | All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V | - | 13 | | | tr/tf | Output rise and fall time | All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V | - | 33 | ns | | | Fmax | Maximum frequency | All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V | - | 40 | MHz | | 1x | | | All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V | - | 20 | | | | Output rise and fall time | All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V | - | 8 | ns | | | tr/tf | | All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V | - | 17 | ^1. Specified by design. Not tested in production.

Table 99. Output AC characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os(1)(2)

Symbol	Parameter	Conditions	Min	Max	Unit
		CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V	-	0.5	MHz
	Fmax Maximum frequency	CL = 50 pF, 1.58 V ≤ VSW < 2.7 V	-	0.25
		CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V	-	400	ns
tr/tf Output rise and fall time		CL = 50 pF, 1.58 V ≤ VSW < 2.7 V	-	900
^1. Specified by design. Not tested in production.

^2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register.

^2. FT_o I/Os output AC characteristics are provided in Table 96 for revision X devices.

Figure 37. Output AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 29, Table 30 and Table 31 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 29. Voltage characteristics⁽¹⁾⁽²⁾

Symbol	Ratings	Min	Max	Unit
V _DDX - V _SS	External main supply voltage (including VDDSMPS, VDDA, VDDUSB, VBAT, VREF+)	-0.3	4.0
V _DDIOx ⁽³⁾ - V _SS	I/O supply when HSLV = 0	-0.3	4.0
V _IN ⁽⁴⁾	I/O supply when HSLV = 1	-0.3	2.75	V
	Input voltage on FT_xx pins except FT_c pins	V _SS - 0.3	Min (min (V _DD , V _DDA , V _DDUSB , V _DDIO2 ) + 4.0, 6.0) ⁽⁵⁾⁽⁶⁾
	Input voltage on FT_t pins in V _BAT mode	V _SS - 0.3	Min (min (V _BAT , V _DDA , V _DDUSB , V _DDIO2 ) + 4.0, 6.0) ⁽⁵⁾⁽⁶⁾
V _IN ⁽⁴⁾	Input voltage on FT_c pins	V _SS - 0.3	5.5
VIN'	Input voltage on any other pins	V _SS - 0.3	4.0	V
V _REF+ - V _DDA	Allowed voltage difference for V _REF+ > V _DDA	-	0.4
$ \Delta V_{DDx} $	Variations between different VDDx power pins of the same domain	-	50.0	m/
V _SSx -V _SS	Variations between all the different ground pins ⁽⁷⁾	-	50.0	mV

^1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must always be connected to the external power supply, in the permitted range.

Table 30. Current characteristics

Symbol	Ratings	Max	Unit
∑IV _DD	Total current into sum of all V _DD power lines (source) ⁽¹⁾	200
ΣIV _SS	Total current out of sum of all V _SS ground lines (sink) ⁽¹⁾	200
IV _DD	Maximum current into each VDD power pin (source) ⁽¹⁾	100
IV _SS	Maximum current out of each VSS ground pin (sink) ⁽¹⁾	100
1.	Output current sunk by any I/O and control pin	20	mA
I _IO	Output current sourced by any I/O and control pin	20	IIIA
71	Total output current sunk by sum of all I/Os and control pins ⁽²⁾	120
$\sum I_{(PIN)}$	Total output current sourced by sum of all I/Os and control pins ⁽²⁾	120
I _INJ(PIN) (3)(4)	Injected current on FT_xx, TT_xx, RST pins	-5/+0
Σ I _INJ(PIN)	Total injected current (sum of all I/Os and control pins) ⁽⁵⁾	±25
All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must always be connected to the external power supplies, in the permitted range.

^2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

^3. $V_{DDIO1}$ or $V_{DDIO2}$ or $V_{SW}$ , $V_{DDIO1} = V_{DD}$ .

^4. V_IN maximum must always be respected. Refer to Table 30 for the maximum allowed injected current values.

^5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.

^6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.

^7. Including VREF- pin.

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
1. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
1. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 29 for the minimum allowed input voltage values.
1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN) is the absolute sum of the negative injected currents (instantaneous values).

Table 31. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	–65 to +150
TJ	Maximum junction temperature	140	°C

Thermal Information

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated using the following equation:

TJ max = TA max + (PD max × ΘJA)

where:

TA max is the maximum ambient temperature in °C.
ΘJA is the package junction-to-ambient thermal resistance in °C/W.
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max).
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins:

$$P_{I/O} \max = \sum (V_{OL} \times I_{OL}) + \sum ((V_{DDIOx} - V_{OH}) \times I_{OH})$$

taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application.

Table 165. Package thermal characteristics

Symbol	Parameter	Package	Value	Unit
		LQFP48 7 x 7 mm	45.8
		UFQFPN48 7 x 7 mm	26.9
		LQFP64 10 x 10 mm	39.6
		WLCSP90 4.2 x 3.95 mm	42.3
ΘJA	Thermal resistance junction-ambient	LQFP100 - 14 × 14 m	34.4
		UFBGA132 7 x 7 mm	35.2
		LQFP144 20 x 20 mm	35.9
		UFBGA169 7 x 7 mm	33.7
		LQFP48 7 x 7 mm	23.4
	Thermal resistance junction-board	UFQFPN48 7 x 7 mm	11.2
		LQFP64 10 x 10 mm	22
		WLCSP90 4.2 x 3.95 mm	27.5
ΘJB		LQFP100 - 14 × 14 m	20.3	°C/W
		UFBGA132 7 x 7 mm	20.7
		LQFP144 20 x 20 mm	24.8
		UFBGA169 7 x 7 mm	19.3
		LQFP48 7 x 7 mm	10.7
		UFQFPN48 7 x 7 mm	8
		LQFP64 10 x 10 mm	9.0
		WLCSP90 4.2 x 3.95 mm	1.6
ΘJC	Thermal resistance junction-top case	LQFP100 - 14 × 14 m	7.4
		UFBGA132 7 x 7 mm	8.3
		LQFP144 20 x 20 mm	7.6
		UFBGA169 7 x 7 mm	8.3

6.9.1 Reference documents

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) available on www.jedec.org.
For information on thermal management, refer to application note "Guidelines for thermal management on STM32 applications" (AN5036) available on www.st.com.

STM32U575RIT6

Overview

Features

Includes ST state-of-the-art patented technology

Ultra-low-power with FlexPowerControl

Core

ART Accelerator

Power management

Benchmarks

Memories

Security

Clock management

General-purpose input/outputs

Up to 17 timers and 2 watchdogs

Up to 22 communication peripherals

16- and 4-channel DMA controllers, functional in Stop mode

Graphic features

Mathematical coprocessor

Up to 22 capacitive sensing channels

Rich analog peripherals (independent supply)

CRC calculation unit

Debug

ECOPACK2 compliant packages Table 1. Device summary

Pin Configuration

Electrical Characteristics

Absolute Maximum Ratings

Thermal Information

where:

6.9.1 Reference documents