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STM32U575ZG/I

Ultra-low-power Arm Cortex-M33 32-bit MCU

The STM32U575ZG/I is a ultra-low-power arm cortex-m33 32-bit mcu from STMicroelectronics. View the full STM32U575ZG/I datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Overview

Part: STM32U575xx from STMicroelectronics

Type: Ultra-low-power Arm Cortex-M33 32-bit MCU+TrustZone+FPU

Description: Ultra-low-power Arm Cortex-M33 32-bit MCU with TrustZone and FPU, featuring up to 2 MB Flash memory, 786 KB SRAM, and operating at up to 160 MHz (240 DMIPS).

Operating Conditions:

  • Supply voltage: 1.71 V to 3.6 V
  • Operating temperature: -40 °C to +125 °C
  • Max CPU frequency: 160 MHz

Absolute Maximum Ratings:

  • Max supply voltage: null
  • Max continuous current: null
  • Max junction/storage temperature: null

Key Specs:

  • Core: Arm 32-bit Cortex-M33 CPU with TrustZone, MPU, DSP, and FPU
  • Flash Memory: 2 Mbyte with ECC, 2 banks read-while-write
  • SRAM: 786 Kbyte with ECC OFF or 722 Kbyte with ECC ON
  • Run mode current: 19.5 μA/MHz @ 3.3 V
  • Shutdown mode current: 160 nA (24 wake-up pins)
  • ADC: 14-bit 2.5-Msps with hardware oversampling, 12-bit 2.5-Msps
  • I/Os: Up to 136 fast I/Os, most 5V-tolerant
  • DMIPS: 240 DMIPS (up to 160 MHz)

Features:

  • Arm TrustZone and securable I/Os, memories, and peripherals
  • FlexPowerControl with various low-power modes (Shutdown, Standby, Stop 2, Stop 3)
  • ART Accelerator with 8-Kbyte instruction cache and 4-Kbyte data cache
  • Embedded regulator (LDO) and SMPS step-down converter
  • Rich analog peripherals: ADCs, DACs, operational amplifiers, comparators
  • Multiple communication interfaces: USB Type-C/PD, USB OTG 2.0 FS, SAIs, I2C, U(S)ART, SPI, CAN FD, SDMMC

Applications:

  • null

Package:

  • LQFP48 (7 x 7 mm)
  • LQFP64 (10 x 10 mm)
  • LQFP100 (14 x 14 mm)
  • LQFP144 (20 x 20 mm)
  • UFQFPN48 (7 x 7 mm)
  • WLCSP90 (4.2 x 3.95 mm)
  • UFBGA132 (7 x 7 mm)
  • UFBGA169 (7 x 7 mm)

Features

  • Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
  • 1 digital camera interface

Pin Configuration

Table 25. Legend/abbreviations used in the pinout table

NameNameAbbreviationDefinition
Pin namePin nameUnless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin nameUnless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
SSupply pin
typeIInput only pin
I/OInput/output pin
FT5V-tolerant I/O
TT3.6V-tolerant I/O
RSTBidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os (1)Option for TT or FT I/Os (1)
_aI/O, with analog switch function supplied by V DDA
_cI/O with USB Type-C power delivery function
structure_dI/O with USB Type-C power delivery dead battery function
_fI/O, Fm+ capable
_hI/O with high-speed low-voltage mode
_oI/O with OSC32_IN/OSC32_OUT capability
_sI/O supplied only by V DDIO2
_tI/O with a function supplied by V SW
_uI/O, with USB function supplied by V DDUSB
_vI/O very high-speed capable
Unless otherwise specified by a note, all I/Os are set as analog inputs during andUnless otherwise specified by a note, all I/Os are set as analog inputs during and
NotesNotesafter reset.after reset.
Pin functionsAlternate functionsFunctions selected through GPIOx_AFR registersFunctions selected through GPIOx_AFR registers
Pin functionsAdditional functionsFunctions directly selected/enabled through peripheral registersFunctions directly selected/enabled through peripheral registers

Table 25. Legend/abbreviations used in the pinout table

149

Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)Table 26. STM32U575xx pin definitions (1)
104/346Pin numberPin numberPin numberPin numberPin numberPin numberPin numberPin numberPin numberPin numberPin numberPin name (function after reset)Pin typeI/O structureAlternate functions
104/346LQFP48 SMPS UFQFPN48 SMPSLQFP64 SMPSWLCSP90 SMPSLQFP100 SMPS UFBGA132 SMPSLQFP144 SMPSUFBGA169 SMPSLQFP48 UFQFPN48LQFP64LQFP100UFBGA132LQFP144NotesAlternate functionsAdditional functions
104/346---1B3 1A1--1B31PE2I/OFT_ha-TRACECLK, TIM3_ETR, SAI1_CK1, TSC_G7_IO1, LPGPIO1_P14, FMC_A23, SAI1_MCLK_A, EVENTOUT-
104/346--C152A2 2D3--2A22PE3I/OFT_ hat-TRACED0, TIM3_CH1, OCTOSPIM_P1_DQS, TSC_G7_IO2, LPGPIO1_P15, FMC_A19, SAI1_SD_B, EVENTOUTTAMP_IN6/ TAMP_ OUT3
104/346--D143B2 3C2--3B23PE4I/OFT_ hat-TRACED1, TIM3_CH2, SAI1_D2, MDF1_SDI3, TSC_G7_IO3, DCMI_D4/PSSI_D4, FMC_A20, SAI1_FS_A, EVENTOUTWKUP1, TAMP_IN7/ TAMP_ OUT8
104/346--E134A1 4D2--4A14PE5I/OFT_ hat-TRACED2, TIM3_CH3, SAI1_CK2, MDF1_CKI3, TSC_G7_IO4, DCMI_D6/PSSI_D6, FMC_A21, SAI1_SCK_A, EVENTOUTWKUP2, TAMP_IN8/ TAMP_ OUT7
104/346--D165C2 5E4--5C25PE6I/OFT_ht-TRACED3, TIM3_CH4, SAI1_D1, DCMI_D7/PSSI_D7, FMC_A22, SAI1_SD_A, EVENTOUTWKUP3, TAMP_IN3/ TAMP_ OUT6
104/34611C176B1 6C1116B16VBATS----
104/346----- -F2-----VSSS----

Electrical Characteristics

The definition and values of output AC characteristics are given in Figure 37: Output AC characteristics definition and in the table below respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 32 .

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FTc, FTt in V BAT mode and FTo I/Os (1) ) (2)(3)(4)

SpeedSymbolParameterConditionsMinMaxUnit
00FmaxMaximum frequency all I/OsC L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-12.5MHz
00FmaxMaximum frequency all I/OsC L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V-5MHz
00FmaxMaximum frequency all I/OsC L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V-1MHz
00FmaxMaximum frequency all I/OsC L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-12.5MHz
00FmaxMaximum frequency all I/OsC L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V-5MHz
00FmaxMaximum frequency all I/OsC L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V-1MHz
00t r /t fOutput rise and fall time all I/OsC L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-17ns
00t r /t fOutput rise and fall time all I/OsC L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V-33ns
00t r /t fOutput rise and fall time all I/OsC L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V-85ns
00t r /t fOutput rise and fall time all I/OsC L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-12.5ns
00t r /t fOutput rise and fall time all I/OsC L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V-25ns
00t r /t fOutput rise and fall time all I/OsC L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V-50ns
01FmaxMaximum frequency all I/OsC L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-55MHz
01FmaxMaximum frequency all I/OsC L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V-12.5MHz
01FmaxMaximum frequency all I/OsC L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V-2.5MHz
01FmaxMaximum frequency all I/OsC L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-55MHz
01FmaxMaximum frequency all I/OsC L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V-12.5MHz
01FmaxMaximum frequency all I/OsC L = 10 pF, 1.08 V ≤ V DDIOx ≤ <1.58 V-2.5MHz
01t r /t fOutput rise and fall time all I/OsC L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-5.8ns
01t r /t fOutput rise and fall time all I/OsC L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V-10ns
01t r /t fOutput rise and fall time all I/OsC L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V-18ns
01t r /t fOutput rise and fall time all I/OsC L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V-4.2ns
01t r /t fOutput rise and fall time all I/OsC L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V-7.5ns
01t r /t fOutput rise and fall time all I/OsC L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V-12ns

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FTc, FTt in V BAT mode and FTo I/Os (1) ) (2)(3)(4)

305

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 29 , Table 30 and Table 31 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

305

Table 29. Voltage characteristics (1)(2)

SymbolRatingsMinMaxUnit
V DDX - V SSExternal main supply voltage (including V DDSMPS , V DDA , V DDUSB , V BAT , V REF+ )-0.34.0V
V DDIOx (3) - V SSI/O supply when HSLV = 0-0.34.0V
V DDIOx (3) - V SSI/O supply when HSLV = 1-0.32.75V
V IN (4)Input voltage on FT_xx pins except FT_c pinsV SS - 0.3Min (min (V DD ,V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0) (5)(6)V
V IN (4)Input voltage on FT_t pins in V BAT modeV SS - 0.3Min (min (V BAT , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0) (5)(6)V
V IN (4)Input voltage on FT_c pinsV SS - 0.35.5V
V IN (4)Input voltage on any other pinsV SS - 0.34.0V
V REF+ - V DDAAllowed voltage difference for V REF+ > V DDA-0.4V
| ∆ V DDx |Variations between different VDDx power pins of the same domain-50.0mV
|V SSx -V SS |Variations between all the different ground pins (7)-50.0mV
  1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
  2. VDDIO1 or V DDIO2 or V SW , V DDIO1 = V DD .
  3. VIN maximum must always be respected. Refer to Table 30 for the maximum allowed injected current values.
  4. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
  5. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
  6. Including VREF- pin.

Table 30. Current characteristics

SymbolRatingsMaxUnit
∑ IV DDTotal current into sum of all V DD power lines (source) (1)200mA
∑ IV SSTotal current out of sum of all V SS ground lines (sink) (1)200mA
IV DDMaximum current into each VDD power pin (source) (1)100mA
IV SSMaximum current out of each VSS ground pin (sink) (1)100mA
I IOOutput current sunk by any I/O and control pin20mA
I IOOutput current sourced by any I/O and control pin20mA
∑ I (PIN)Total output current sunk by sum of all I/Os and control pins (2)120mA
∑ I (PIN)Total output current sourced by sum of all I/Os and control pins (2)120mA
I INJ(PIN) (3)(4)Injected current on FT_xx, TT_xx, RST pins-5/+0mA
∑ |I INJ(PIN) |Total injected current (sum of all I/Os and control pins) (5)±25mA

Table 30. Current characteristics

  1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
  2. Positive injection (when V IN > V DDIOx ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  3. A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 29 for the minimum allowed input voltage values.
  4. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) is the absolute sum of the negative injected currents (instantaneous values).

Table 31. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature140°C

Table 31. Thermal characteristics

305

Thermal Information

The maximum chip-junction temperature, T J max, in degrees Celsius, can be calculated using the following equation:T _ { J } max = T _ { A } max + ( P _ { D } max × Θ _ { J A } )$

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

Related Variants

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