STM32H563ZIT6

The STM32H562xx and STM32H563xx devices are a high-performance microcontrollers family (STM32H5 Series) based on the high-performance Arm ® Cortex ® -M33 32-bit RISC core. They operate at a frequency of up to 250 MHz.

The Cortex ® -M33 core features a single-precision floating-point unit (FPU), that supports all the Arm ® single-precision data-processing instructions and all the data types.

The Cortex ® -M33 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (2 Mbytes of dual bank flash memory and 640 Kbytes of SRAM), a flexible external memory controller (FMC) (for devices with packages of 100 pins and more), one Octo-SPI memory interface (at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.

The devices offer security foundation compliant with the trusted-based security architecture (TBSA) requirements from Arm ® . It embeds features to implement a secure firmware update. Besides these capabilities, the devices incorporate a secure firmware installation feature, that allows the customer to secure the provisioning of the code during its production. A flexible life cycle is managed thanks to multiple levels of protection and secure debug authentication. Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege configuration of peripherals and memories.

The devices feature several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, secure and hide protection areas.

The devices embed several peripherals reinforcing security: a HASH hardware accelerator, and a true random number generator

The devices offer active tamper detection and protection against transient and environmental perturbation attacks, thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications.

The devices offer two fast 12-bit ADC, two DAC channels, an internal voltage reference buffer, a low-power RTC, two 32-bit general-purpose timers, two 16-bit PWM timers dedicated to motor control, eight 16-bit general-purpose timers, two 16-bit basic timers and six 16-bit low-power timers.

The devices also feature standard and advanced communication interfaces such as: four I 2 Cs, one I3C, six SPIs, three I2Ss, six USARTs, six UARTs and one low-power UART, two SAIs, one digital camera interface (DCMI), up to two SDMMC, up to two FDCAN, one USB full-speed, one USB Type-C™ /USB Power Delivery controller, an Ethernet interface (available only on STM32H563xx device).

The devices operate in the - 40 to + 85 °C (+ 130 °C junction) and - 40 to + 125 °C (+ 130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.

A comprehensive set of power-saving modes allow the design of low-power applications.

Some independent power supplies are supported like an analog independent supply input for ADC, DACs, a 3.3 V dedicated supply input for USB and a dedicated supply input for some GPIOs and SDMMC. A VBAT input is available for connecting a backup battery in

order to preserve the RTC functionality and to backup 32x 32-bit registers and 4-Kbyte SRAM.

The devices offer eight packages from 64-pin to 176-pin.

All packages are available with two options LDO or SMPS supply for the V CORE (except for LQFP64 and VFQFPN68 packages which are not available in SMPS and WLCSP80 which is not available in LDO).

Table 2. STM32H56xxx features and peripheral counts

Peripherals	Peripherals	STM32H563RI/G	STM32H562RI/G	STM32H563MI	STM32H563VI/G	STM32H562VI/G	STM32H563ZI/G	STM32H562ZI/G	STM32H563AI/G	STM32H562AI/G	STM32H563II/G	STM32H562II/G
Flash memory (Mbytes)	Flash memory (Mbytes)	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes	Up to 2 Mbytes
SRAM	System (Kbytes)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)	640 (256+64+320)
SRAM	Backup (bytes)	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes	4 Kbytes
Flexible memory controller for external memories (FMC)	Flexible memory controller for external memories (FMC)	No		yes (1)	yes (2)	yes	yes	yes	yes	yes	yes	yes
OCTOSPI	OCTOSPI	1	1	1	1	1	1	1	1	1	1	1
Timers	Advanced control	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)
Timers	General purpose	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)	(32 bits) and 8 (16 bits)
Timers	Basic	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)	2 (16 bits)
Timers	Low power	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)	6 (16 bits)
Timers	SysTick timer	2	2	2	2	2	2	2	2	2	2	2
Timers	Watchdog timers (independent, window)	2	2	2	2	2	2	2	2	2	2	2

Table 2. STM32H56xxx features and peripheral counts

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Table 2. STM32H56xxx features and peripheral counts (continued)

Peripherals	Peripherals	STM32H563RI/G	STM32H562RI/G	STM32H563MI	STM32H563VI/G	STM32H562VI/G	STM32H563ZI/G	STM32H562ZI/G	STM32H563AI/G	STM32H562AI/G	STM32H563II/G	STM32H562II/G
	SPI / I2S	4/3	4/3	4/3	5/3	5/3	5/3	6/3	6/3	6/3	6/3	6/3
	I2C				4	4	4	4	4	4	4	4
	I3C				1 (3)	1 (3)	1 (3)	1 (3)	1 (3)	1 (3)	1 (3)	1 (3)
	USART	5	5	5	6	6	6	6	6	6	6	6
	UART	5	5	5	6	6	6	6	6	6	6	6
	LPUART	1	1	1	1	1	1	1	1	1	1	1
	SAI	2	2	2	2	2	2	2	2	2	2	2
	FDCAN	2	1	2	2	1	2	1	2	1	2	1
	USB	yes	yes	yes	yes	yes	yes	yes	yes	yes	yes	yes
	UCPD	yes	yes	yes	yes	yes	yes	yes	yes	yes	yes	yes
	SDMMC	1	1	1	2	1	2	1	2	1	2	1
	Digital camera interface (DCMI) / PSSI (4)	yes	yes	yes	yes	yes	yes	yes	yes	yes	yes	yes
	Ethernet (Legacy / SMPS)	Yes/ NA	No	NA/ Yes	Yes / No	No	Yes/ No	No	Yes/ Yes	No	Yes /Yes	No
	HDMI-CEC	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
CORDIC co-processor	CORDIC co-processor	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Filter mathematical accelerator (FMAC)	Filter mathematical accelerator (FMAC)	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Real time clock (RTC)	Real time clock (RTC)	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Tamper pins (legacy/SMPS)	Tamper pins (legacy/SMPS)	5 / NA	5 / NA	NA/ 5	8/8	8/8	8/8	8/8	8/8	8/8	8/8	8/8
Active tampers (legacy/SMPS) (5)	Active tampers (legacy/SMPS) (5)	4 / NA	4 / NA	NA/ 4	7/7	7/7	7/7	7/7	7/7	7/7	7/7	7/7
True random number generator	True random number generator	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
HASH (SHA-512)	HASH (SHA-512)	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
GPIOs (legacy/SMPS)	GPIOs (legacy/SMPS)	53 / NA (6)	53 / NA (6)	NA/ 57	80/ 78	80/ NA	112/ 110	112/ NA	136/ 134	136/ NA	140 (7) /139	140 (7)
Wakeup pins (legacy/SMPS)	Wakeup pins (legacy/SMPS)	6 / NA (8)	6 / NA (8)	NA/ 6	7/7	7/ NA	7/7	7/ NA	8/8	8/ NA	8/8	8/ NA
Number of I/Os down to 1.08 V (legacy/SMPS)	Number of I/Os down to 1.08 V (legacy/SMPS)	0 / NA	0 / NA	NA/ 0	0/0	0/ NA	10/ 10	10/ NA	10/7	10/ NA	10/7	10/ NA

Table 2. STM32H56xxx features and peripheral counts (continued)

Table 2. STM32H56xxx features and peripheral counts (continued)

Peripherals	Peripherals	STM32H563RI/G	STM32H562RI/G	STM32H563MI	STM32H563VI/G	STM32H562VI/G	STM32H563ZI/G	STM32H562ZI/G	STM32H563AI/G	STM32H562AI/G	STM32H563II/G	STM32H562II/G
	12-bitADC	2	2	2	2	2	2	2	2	2	2	2
	Number of channels (legacy/SMP S)	16/NA	16/NA	NA/ 16	16/ 14	16/ NA	20/ 18	20/ NA	20/ 20	20/ NA	20/ 20	20/ NA
	12-bit DAC controller	1	1	1	1	1	1	1	1	1	1	1
	Number of 12-bit Dto-A converters	2	2	2	2	2	2	2	2	2	2	2
Internal voltage reference buffer	Internal voltage reference buffer	No	No	No	No	YES	YES	YES	YES	YES	YES	YES
Maximum CPU frequency	Maximum CPU frequency	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz	250 MHz
Operating voltage	Operating voltage	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V	1.71 to 3.6 V
Operating temperature	Operating temperature	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C	Ambient operating temperature: - 40 to 85 °C / - 40 to 125 °C Junction temperature: - 40 to 130 °C
Package	Package	LQFP64 VFQFPN68	WLCSP80	WLCSP80	LQFP100	LQFP100	LQFP144	LQFP144	UFBGA169	UFBGA169	LQFP176 UFBGA176	LQFP176 UFBGA176

1. Shares the same IOs than I2C4.
2. DCMI and PSSI cannot be used at the same time as they share the same circuitry.
3. Active tampers in output sharing mode (one output shared by all inputs).
4. 49 for LQFP64.
5. 136 for LQFP176.
6. 5 for VFQFPN68.

18

Figure 1. STM32H562xx and STM32H563xx block diagram

Note:

PC[15:13] are in the VBAT domain.

• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches and cryptographic peripherals.
• 32 32-bit backup registers:
• -The backup registers (TAMP_BKPxR) are implemented in the Backup domain that remains powered-on by V BAT when the V DD power is switched off.
• Up to 8 tamper pins for 8 external tamper detection events:
• -Active tamper mode: continuous comparison between tamper output and input to protect from physical open-short attacks
• -Flexible active tamper I/O management: from 4 meshes (each input associated to its own exclusive output) to 7 meshes (single output shared for up to 7 tamper inputs)
• -Passive tampers: ultra-low power edge or level detection with internal pull-up hardware management
• -Configurable digital filter

Note: As a tamper input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT modes. As a tamper output, only PC13, PA1, and PI8 are functional in Standby and VBAT modes.

• Internal tamper events to protect against transient or environmental perturbation attacks
• Each tamper can be configured in two modes:
• -Hardware mode: immediate erase of secrets on tamper detection, including backup registers erase
• -Software mode: erase of secrets following a tamper detection launched by software
• Any tamper detection can generate an RTC time stamp event.
• TrustZone support:
• -Tamper secure or non-secure configuration.
• -Backup registers configuration in 3 configurable-size areas:
• 1 read/write secure area
• 1 write secure/read non-secure area
• 1 read/write non-secure area
• -Secret key, stored in backup registers, protected against read and write access
• Tamper configuration and backup registers privilege protection

64

• Monotonic counter

Pin	Name	Type	Description
1	PE2	I/O	alt: DCMI_D3, DEBUG_TRACECLK, ETH_MII_TXD3, FMC_A23, LPTIM1_IN2, OCTOSPI1_IO2, PSSI_D3, SAI1_CK1, SAI1_MCLK_A, SPI4_SCK, UART8_TX, USART10_RX
2	PE3	I/O	alt: DEBUG_TRACED0, FMC_A19, SAI1_SD_B, TAMP_IN6, TAMP_OUT3, TIM15_BKIN, USART10_TX
3	PE4	I/O	alt: DCMI_D4, DEBUG_TRACED1, FMC_A20, PSSI_D4, SAI1_D2, SAI1_FS_A, SPI4_NSS, TAMP_IN7, TAMP_OUT8, TIM15_CH1N
4	PE5	I/O	alt: DCMI_D6, DEBUG_TRACED2, FMC_A21, PSSI_D6, SAI1_CK2, SAI1_SCK_A, SPI4_MISO, TAMP_IN8, TAMP_OUT7, TIM15_CH1
5	PE6	I/O	alt: DCMI_D7, DEBUG_TRACED3, FMC_A22, PSSI_D7, SAI1_D1, SAI1_SD_A, SAI2_MCLK_B, SPI4_MOSI, TAMP_IN3, TAMP_OUT6, TIM15_CH2, TIM1_BKIN2
6	VBAT	P
7	PC13	I/O	alt: PWR_WKUP4, RTC_OUT1, RTC_TS, TAMP_IN1, TAMP_OUT2, TAMP_OUT3
8	PC14-OSC32_IN(OSC32_IN)	I/O	alt: RCC_OSC32_IN
9	PC15-OSC32_OUT(OSC32_OUT)	I/O	alt: ADC1_EXTI15, ADC2_EXTI15, RCC_OSC32_OUT
10	PF0	I/O	alt: FMC_A0, I2C2_SDA, LPTIM5_CH1
11	PF1	I/O	alt: FMC_A1, I2C2_SCL, LPTIM5_CH2
12	PF2	I/O	alt: FMC_A2, I2C2_SMBA, LPTIM3_CH2, LPTIM3_IN2, LPTIM5_IN1, UART12_TX, USART11_CK
13	PF3	I/O	alt: FMC_A3, LPTIM3_IN1, LPTIM5_IN2, USART11_TX
14	PF4	I/O	alt: FMC_A4, LPTIM3_ETR, USART11_RX
15	PF5	I/O	alt: FMC_A5, I2C4_SCL, I3C1_SCL, LPTIM3_CH1, LPTIM3_IN1, UART12_RX, USART11_CTS, USART11_NSS
16	VSS	P
17	VDD	P
18	PF6	I/O	alt: LPTIM5_CH1, OCTOSPI1_IO3, SAI1_SD_B, SPI5_NSS, TIM16_CH1, UART7_RX
19	PF7	I/O	alt: LPTIM5_CH2, OCTOSPI1_IO2, SAI1_MCLK_B, SPI5_SCK, TIM17_CH1, UART7_TX
20	PF8	I/O	alt: LPTIM5_IN1, OCTOSPI1_IO0, SAI1_SCK_B, SPI5_MISO, TIM13_CH1, TIM16_CH1N, UART7_DE, UART7_RTS
21	PF9	I/O	alt: DAC1_EXTI9, LPTIM5_IN2, OCTOSPI1_IO1, SAI1_FS_B, SPI5_MOSI, TIM14_CH1, TIM17_CH1N, UART7_CTS
22	PF10	I/O	alt: DCMI_D11, OCTOSPI1_CLK, PSSI_D11, PSSI_D15, SAI1_D3, TIM16_BKIN
23	PH0-OSC_IN(PH0)	I/O	alt: RCC_OSC_IN
24	PH1-OSC_OUT(PH1)	I/O	alt: RCC_OSC_OUT
25	NRST	RST
26	PC0	I/O	alt: ADC1_INP10, ADC2_INP10, FMC_A25, FMC_SDNWE, OCTOSPI1_IO7, SAI1_MCLK_A, SAI2_FS_B, SPI2_RDY, TIM16_BKIN
27	PC1	I/O	alt: ADC1_INN10, ADC1_INP11, ADC2_INN10, ADC2_INP11, DEBUG_TRACED0, ETH_MDC, I2S2_SDO, OCTOSPI1_IO4, PWR_WKUP6, SAI1_D1, SAI1_SD_A, SAI2_SD_A, SDMMC2_CK, SPI2_MOSI, TAMP_IN3, TAMP_OUT5, USART11_DE, USART11_RTS
28	PC2	I/O	alt: ADC1_INN11, ADC1_INP12, ADC2_INN11, ADC2_INP12, ETH_MII_TXD2, FMC_SDNE0, I2S2_SDI, OCTOSPI1_IO2, OCTOSPI1_IO5, PWR_CSLEEP, SPI2_MISO, TIM17_CH1, TIM4_CH4
29	PC3	I/O	alt: ADC1_INN12, ADC1_INP13, ADC2_INN12, ADC2_INP13, ETH_MII_TX_CLK, FMC_SDCKE0, I2S2_SDO, LPTIM3_CH1, OCTOSPI1_IO0, OCTOSPI1_IO6, PWR_CSTOP, SAI1_D3, SPI2_MOSI
30	VDD	P
31	VSSA	P
32	VREF+	P
33	VDDA	P
34	PA0	I/O	alt: ADC1_INN1, ADC1_INP0, ADC2_INN1, ADC2_INP0, ETH_MII_CRS, PWR_WKUP1, SAI2_SD_B, SDMMC2_CMD, SPI3_RDY, SPI6_NSS, TAMP_IN2, TAMP_OUT1, TIM15_BKIN, TIM2_CH1, TIM2_ETR, TIM5_CH1, TIM8_ETR, UART4_TX, USART2_CTS, USART2_NSS
35	PA1	I/O	alt: ADC1_INP1, ADC2_INP1, ETH_MII_RX_CLK, ETH_RMII_REF_CLK, LPTIM1_IN1, OCTOSPI1_DQS, OCTOSPI1_IO3, SAI2_MCLK_B, TAMP_IN5, TAMP_OUT4, TIM15_CH1N, TIM2_CH2, TIM5_CH2, UART4_RX, USART2_DE, USART2_RTS
36	PA2	I/O	alt: ADC1_INP14, ADC2_INP14, ETH_MDIO, LPTIM1_IN2, PWR_WKUP2, SAI2_SCK_B, TAMP_IN4, TAMP_OUT3, TIM15_CH1, TIM2_CH3, TIM5_CH3, USART2_TX
37	PA3	I/O	alt: ADC1_INP15, ADC2_INP15, ETH_MII_COL, I2S2_WS, OCTOSPI1_CLK, SAI1_SD_B, SPI2_NSS, TIM15_CH2, TIM2_CH4, TIM5_CH4, USART2_RX
38	VSS	P
39	VDD	P
40	PA4	I/O	alt: ADC1_INP18, ADC2_INP18, DAC1_OUT1, DCMI_HSYNC, I2S1_WS, I2S3_WS, LPTIM2_CH1, PSSI_DE, SPI1_NSS, SPI3_NSS, SPI6_NSS, TIM5_ETR, USART2_CK
41	PA5	I/O	alt: ADC1_INN18, ADC1_INP19, ADC2_INN18, ADC2_INP19, DAC1_OUT2, ETH_MII_TX_EN, ETH_RMII_TX_EN, I2S1_CK, PSSI_D14, SPI1_SCK, SPI6_SCK, TIM2_CH1, TIM2_ETR, TIM8_CH1N
42	PA6	I/O	alt: ADC1_INP3, ADC2_INP3, DCMI_PIXCLK, I2S1_SDI, OCTOSPI1_IO3, PSSI_PDCK, SPI1_MISO, SPI6_MISO, TIM13_CH1, TIM1_BKIN, TIM3_CH1, TIM8_BKIN, USART11_TX
43	PA7	I/O	alt: ADC1_INN3, ADC1_INP7, ADC2_INN3, ADC2_INP7, ETH_MII_RX_DV, ETH_RMII_CRS_DV, FMC_NWE, FMC_SDNWE, I2S1_SDO, OCTOSPI1_IO2, SPI1_MOSI, SPI6_MOSI, TIM14_CH1, TIM1_CH1N, TIM3_CH2, TIM8_CH1N, USART11_RX
44	PC4	I/O	alt: ADC1_INP4, ADC2_INP4, ETH_MII_RXD0, ETH_RMII_RXD0, FMC_SDNE0, I2S1_MCK, LPTIM2_ETR, SAI1_CK1, TIM2_CH4, USART3_RX
45	PC5	I/O	alt: ADC1_INN4, ADC1_INP8, ADC2_INN4, ADC2_INP8, ETH_MII_RXD1, ETH_RMII_RXD1, FMC_SDCKE0, OCTOSPI1_DQS, PSSI_D15, SAI1_D3, SAI1_FS_A, TIM1_CH4N, UART12_DE, UART12_RTS
46	PB0	I/O	alt: ADC1_INN5, ADC1_INP9, ADC2_INN5, ADC2_INP9, ETH_MII_RXD2, LPTIM3_CH1, OCTOSPI1_IO1, TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS, USART11_CK
47	PB1	I/O	alt: ADC1_INP5, ADC2_INP5, ETH_MII_RXD3, LPTIM3_CH2, OCTOSPI1_IO0, TIM1_CH3N, TIM3_CH4, TIM8_CH3N
48	PB2	I/O	alt: I2S3_SDO, LPTIM1_CH1, LPTIM5_ETR, OCTOSPI1_CLK, OCTOSPI1_DQS, RCC_LSCO, RTC_OUT2, SAI1_D1, SAI1_SD_A, SDMMC1_CMD, SPI1_RDY, SPI3_MOSI, TIM8_CH4N
49	PF11	I/O	alt: ADC1_EXTI11, ADC1_INP2, ADC2_EXTI11, DCMI_D12, FMC_SDNRAS, LPTIM6_CH1, OCTOSPI1_NCLK, PSSI_D12, SAI2_SD_B, SPI5_MOSI
50	PF12	I/O	alt: ADC1_INN2, ADC1_INP6, FMC_A6, LPTIM6_CH2
51	VSS	P
52	VDD	P
53	PF13	I/O	alt: ADC2_INP2, FMC_A7, I2C4_SMBA, LPTIM6_IN1
54	PF14	I/O	alt: ADC2_INN2, ADC2_INP6, FMC_A8, LPTIM6_IN2
55	PF15	I/O	alt: ADC1_EXTI15, ADC2_EXTI15, FMC_A9, I2C4_SDA, I3C1_SDA
56	PG0	I/O	alt: FMC_A10, LPTIM4_IN1, UART9_RX
57	PG1	I/O	alt: FMC_A11, I2S2_SDO, SPI2_MOSI, UART9_TX
58	PE7	I/O	alt: FMC_D4, FMC_DA4, OCTOSPI1_IO4, TIM1_ETR, UART12_DE, UART12_RTS, UART7_RX
59	PE8	I/O	alt: FMC_D5, FMC_DA5, OCTOSPI1_IO5, TIM1_CH1N, UART12_CTS, UART7_TX
60	PE9	I/O	alt: DAC1_EXTI9, FMC_D6, FMC_DA6, OCTOSPI1_IO6, TIM1_CH1, UART12_RX, UART7_DE, UART7_RTS
61	VSS	P
62	VDD	P
63	PE10	I/O	alt: FMC_D7, FMC_DA7, OCTOSPI1_IO7, TIM1_CH2N, UART12_TX, UART7_CTS
64	PE11	I/O	alt: ADC1_EXTI11, ADC2_EXTI11, FMC_D8, FMC_DA8, OCTOSPI1_NCS, SAI2_SD_B, SPI1_RDY, SPI4_NSS, TIM1_CH2
65	PE12	I/O	alt: FMC_D9, FMC_DA9, SAI2_SCK_B, SPI4_SCK, TIM1_CH3N
66	PE13	I/O	alt: FMC_D10, FMC_DA10, SAI2_FS_B, SPI4_MISO, TIM1_CH3
67	PE14	I/O	alt: FMC_D11, FMC_DA11, SAI2_MCLK_B, SPI4_MOSI, TIM1_CH4
68	PE15	I/O	alt: ADC1_EXTI15, ADC2_EXTI15, FMC_D12, FMC_DA12, TIM1_BKIN, TIM1_CH4N, USART10_CK
69	PB10	I/O	alt: ETH_MII_RX_ER, I2C2_SCL, I2S2_CK, LPTIM2_IN1, LPTIM3_CH1, OCTOSPI1_NCS, SPI2_SCK, TIM2_CH3, USART3_TX
70	VCAP	P
71	VSS	P
72	VDD	P
73	PB12	I/O	alt: ETH_MII_TXD0, ETH_RMII_TXD0, FDCAN2_RX, I2C2_SDA, I2S2_WS, OCTOSPI1_NCLK, SPI2_NSS, TIM1_BKIN, UART5_RX, UCPD1_FRSTX, USART3_CK
74	PB13	I/O	alt: FDCAN2_TX, I2C2_SMBA, I2S2_CK, LPTIM2_CH1, LPTIM3_IN1, SDMMC1_D0, SPI2_SCK, TIM1_CH1N, UART5_TX, UCPD1_CC1, USART3_CTS, USART3_NSS
75	PB14	I/O	alt: I2S2_SDI, LPTIM3_ETR, SDMMC2_D0, SPI2_MISO, TIM12_CH1, TIM1_CH2N, TIM8_CH2N, UART4_DE, UART4_RTS, UCPD1_CC2, USART1_TX, USART3_DE, USART3_RTS
76	PB15	I/O	alt: ADC1_EXTI15, ADC2_EXTI15, DCMI_D2, ETH_MII_TXD1, ETH_RMII_TXD1, I2S2_SDO, OCTOSPI1_CLK, PSSI_D2, PWR_PVD_IN, RTC_REFIN, SDMMC2_D1, SPI2_MOSI, TIM12_CH2, TIM1_CH3N, TIM8_CH3N, UART4_CTS, UART5_RX, USART11_CTS, USART11_NSS, USART1_RX
77	PD8	I/O	alt: FMC_D13, FMC_DA13, USART3_TX
78	PD9	I/O	alt: DAC1_EXTI9, FDCAN2_RX, FMC_D14, FMC_DA14, USART3_RX
79	PD10	I/O	alt: FMC_D15, FMC_DA15, LPTIM2_CH2, USART3_CK
80	PD11	I/O	alt: ADC1_EXTI11, ADC2_EXTI11, FMC_A16, FMC_CLE, I2C4_SMBA, LPTIM2_IN2, OCTOSPI1_IO0, SAI1_CK1, SAI2_SD_A, UART4_RX, USART3_CTS, USART3_NSS
81	PD12	I/O	alt: DCMI_D12, FMC_A17, FMC_ALE, I2C4_SCL, I3C1_SCL, LPTIM1_IN1, LPTIM2_IN1, OCTOSPI1_IO1, PSSI_D12, SAI1_D1, SAI2_FS_A, TIM4_CH1, UART4_TX, USART3_DE, USART3_RTS
82	PD13	I/O	alt: DCMI_D13, FMC_A18, I2C4_SDA, I3C1_SDA, LPTIM1_CH1, LPTIM2_CH1, LPTIM4_IN1, OCTOSPI1_IO3, PSSI_D13, SAI2_SCK_A, TIM4_CH2, UART9_DE, UART9_RTS
83	VSS	P
84	VDD	P
85	PD14	I/O	alt: FMC_D0, FMC_DA0, TIM4_CH3, UART8_CTS, UART9_RX
86	PD15	I/O	alt: ADC1_EXTI15, ADC2_EXTI15, FMC_D1, FMC_DA1, TIM4_CH4, UART8_DE, UART8_RTS, UART9_TX
87	PG2	I/O	alt: FMC_A12, LPTIM6_ETR, TIM8_BKIN, UART12_RX
88	PG3	I/O	alt: FMC_A13, LPTIM5_ETR, TIM8_BKIN2, UART12_TX
89	PG4	I/O	alt: FMC_A14, FMC_BA0, LPTIM4_ETR, TIM1_BKIN2
90	PG5	I/O	alt: FMC_A15, FMC_BA1, TIM1_ETR
91	PG6	I/O	alt: DCMI_D12, FMC_NE3, I2C4_SDA, I3C1_SDA, OCTOSPI1_NCS, PSSI_D12, SPI1_RDY, TIM17_BKIN, UCPD1_FRSTX
92	PG7	I/O	alt: DCMI_D13, FMC_INT, I2C4_SCL, I3C1_SCL, PSSI_D13, SAI1_CK2, SAI1_MCLK_A, UCPD1_FRSTX, USART6_CK
93	PG8	I/O	alt: ETH_PPS_OUT, FMC_SDCLK, SPI6_NSS, TIM8_ETR, USART6_DE, USART6_RTS
94	VSS	P
95	VDD	P
96	PC6	I/O	alt: DCMI_D0, FMC_NWAIT, I2S2_MCK, OCTOSPI1_IO5, PSSI_D0, SAI1_SCK_A, SDMMC1_D0DIR, SDMMC1_D6, SDMMC2_D6, TIM3_CH1, TIM8_CH1, USART6_TX
97	PC7	I/O	alt: DCMI_D1, DEBUG_TRGIO, FMC_NE1, I2S3_MCK, OCTOSPI1_IO6, PSSI_D1, SDMMC1_D123DIR, SDMMC1_D7, SDMMC2_D7, TIM3_CH2, TIM8_CH2, USART6_RX
98	PC8	I/O	alt: DCMI_D2, DEBUG_TRACED1, FMC_ALE, FMC_INT, FMC_NCE, FMC_NE2, PSSI_D2, SDMMC1_D0, TIM3_CH3, TIM8_CH3, UART5_DE, UART5_RTS, USART6_CK
99	PC9	I/O	alt: AUDIOCLK, DAC1_EXTI9, DCMI_D3, FMC_CLE, I2C3_SDA, OCTOSPI1_IO0, PSSI_D3, RCC_MCO_2, SDMMC1_D1, TIM3_CH4, TIM8_CH4, UART5_CTS, UCPD1_DB2
100	PA8	I/O	alt: DCMI_D3, FMC_NOE, I2C3_SCL, PSSI_D3, RCC_MCO_1, SPI1_RDY, TIM1_CH1, TIM8_BKIN2, UART7_RX, USART1_CK, USB_SOF
101	PA9	I/O	alt: DAC1_EXTI9, DCMI_D0, ETH_MII_TX_ER, FMC_NWE, I2C3_SMBA, I2S2_CK, LPUART1_TX, PSSI_D0, SPI2_SCK, TIM1_CH2, UCPD1_DB1, USART1_TX
102	PA10	I/O	alt: DCMI_D1, FDCAN2_TX, LPTIM2_IN2, LPUART1_RX, PSSI_D1, SDMMC1_D0, TIM1_CH3, UCPD1_FRSTX, USART1_RX
103	PA11	I/O	alt: ADC1_EXTI11, ADC2_EXTI11, FDCAN1_RX, I2S2_WS, LPUART1_CTS, SPI2_NSS, TIM1_CH4, UART4_RX, USART1_CTS, USART1_NSS, USB_DM
104	PA12	I/O	alt: FDCAN1_TX, I2S2_CK, LPUART1_DE, LPUART1_RTS, SAI2_FS_B, SPI2_SCK, TIM1_ETR, UART4_TX, USART1_DE, USART1_RTS, USB_DP
105	PA13(JTMS/SWDIO)	I/O	alt: DEBUG_JTMS-SWDIO
106	VDDUSB	P
107	VSS	P
108	VDD	P
109	PA14(JTCK/SWCLK)	I/O	alt: DEBUG_JTCK-SWCLK
110	PA15(JTDI)	I/O	alt: ADC1_EXTI15, ADC2_EXTI15, CEC, DCMI_D11, DEBUG_JTDI, FMC_NBL1, I2S1_WS, I2S3_WS, LPTIM3_IN2, PSSI_D11, SPI1_NSS, SPI3_NSS, SPI6_NSS, TIM2_CH1, TIM2_ETR, UART4_DE, UART4_RTS, UART7_TX
111	PC10	I/O	alt: DCMI_D8, ETH_MII_TXD0, ETH_RMII_TXD0, I2S3_CK, LPTIM3_ETR, OCTOSPI1_IO1, PSSI_D8, SDMMC1_D2, SPI3_SCK, UART4_TX, USART3_TX
112	PC11	I/O	alt: ADC1_EXTI11, ADC2_EXTI11, DCMI_D4, I2S3_SDI, LPTIM3_IN1, OCTOSPI1_NCS, PSSI_D4, SDMMC1_D3, SPI3_MISO, UART4_RX, USART3_RX
113	PC12	I/O	alt: DCMI_D9, DEBUG_TRACED3, I2S3_SDO, PSSI_D9, SDMMC1_CK, SPI3_MOSI, SPI6_SCK, TIM15_CH1, UART5_TX, USART3_CK
114	PD0	I/O	alt: FDCAN1_RX, FMC_D2, FMC_DA2, TIM8_CH4N, UART4_RX, UART9_CTS
115	PD1	I/O	alt: FDCAN1_TX, FMC_D3, FMC_DA3, UART4_TX
116	PD2	I/O	alt: DCMI_D11, DEBUG_TRACED2, LPTIM4_ETR, PSSI_D11, PWR_WKUP7, SDMMC1_CMD, TIM15_BKIN, TIM3_ETR, UART5_RX
117	PD3	I/O	alt: DCMI_D5, FMC_CLK, I2S2_CK, PSSI_D5, PWR_WKUP8, SPI2_SCK, USART2_CTS, USART2_NSS
118	PD4	I/O	alt: FMC_NOE, OCTOSPI1_IO4, USART2_DE, USART2_RTS
119	PD5	I/O	alt: FDCAN1_TX, FMC_NWE, OCTOSPI1_IO5, SPI2_RDY, TIM1_CH4N, USART2_TX
120	VSS	P
121	VDDIO2	P
122	PD6	I/O	alt: DCMI_D10, FMC_NWAIT, I2S3_SDO, OCTOSPI1_IO6, PSSI_D10, SAI1_D1, SAI1_SD_A, SDMMC2_CK, SPI3_MOSI, USART2_RX
123	PD7	I/O	alt: FMC_NCE, FMC_NE1, I2S1_SDO, LPTIM4_OUT, OCTOSPI1_IO7, SDMMC2_CMD, SPI1_MOSI, USART2_CK
124	PG9	I/O	alt: DAC1_EXTI9, DCMI_VSYNC, FMC_NCE, FMC_NE2, I2S1_SDI, OCTOSPI1_IO6, PSSI_RDY, SAI2_FS_B, SDMMC2_D0, SPI1_MISO, USART6_RX
125	PG10	I/O	alt: DCMI_D2, FMC_NE3, I2S1_WS, PSSI_D2, SAI2_SD_B, SDMMC2_D1, SPI1_NSS
126	PG11	I/O	alt: ADC1_EXTI11, ADC2_EXTI11, DCMI_D3, ETH_MII_TX_EN, ETH_RMII_TX_EN, I2S1_CK, LPTIM1_IN2, PSSI_D3, SDMMC2_D2, SPI1_SCK, USART10_RX, USART11_DE, USART11_RTS
127	PG12	I/O	alt: DCMI_D11, ETH_MII_TXD1, ETH_RMII_TXD1, FMC_NE4, LPTIM1_IN1, LPTIM5_CH1, PSSI_D11, PSSI_D15, SDMMC2_D3, SPI6_MISO, USART10_TX, USART6_DE, USART6_RTS
128	PG13	I/O	alt: DEBUG_TRACED0, ETH_MII_TXD0, ETH_RMII_TXD0, FMC_A24, LPTIM1_CH1, LPTIM5_CH2, SDMMC2_D6, SPI6_SCK, USART10_CTS, USART10_NSS, USART6_CTS, USART6_NSS
129	PG14	I/O	alt: DEBUG_TRACED1, ETH_MII_TXD1, ETH_RMII_TXD1, FMC_A25, LPTIM1_CH2, LPTIM1_ETR, LPTIM5_IN1, OCTOSPI1_IO7, SDMMC2_D7, SPI6_MOSI, USART10_DE, USART10_RTS, USART6_TX
130	VSS	P
131	VDD	P
132	PG15	I/O	alt: ADC1_EXTI15, ADC2_EXTI15, DCMI_D13, FMC_SDNCAS, PSSI_D13, SPI4_RDY, USART10_CK, USART6_CTS, USART6_NSS
133	PB3(JTDO/TRACESWO)	I/O	alt: CRS_SYNC, DEBUG_JTDO-SWO, I2C2_SDA, I2S1_CK, I2S3_CK, LPTIM6_ETR, SDMMC2_D2, SPI1_SCK, SPI3_SCK, SPI6_SCK, TIM2_CH2, UART12_CTS, UART7_RX
134	PB4(NJTRST)	I/O	alt: DCMI_D7, DEBUG_NJTRST, I2S1_SDI, I2S2_WS, I2S3_SDI, LPTIM1_CH2, OCTOSPI1_CLK, PSSI_D7, SDMMC2_D3, SPI1_MISO, SPI2_NSS, SPI3_MISO, SPI6_MISO, TIM16_BKIN, TIM3_CH1, UART7_TX
135	PB5	I/O	alt: DCMI_D10, ETH_PPS_OUT, FDCAN2_RX, FMC_SDCKE1, I2C1_SMBA, I2C4_SMBA, I2S1_SDO, I2S3_SDO, OCTOSPI1_NCLK, PSSI_D10, SPI1_MOSI, SPI3_MOSI, SPI6_MOSI, TIM17_BKIN, TIM3_CH2, UART5_RX
136	PB6	I/O	alt: CEC, DCMI_D5, FDCAN2_TX, FMC_SDNE1, I2C1_SCL, I2C4_SCL, I3C1_SCL, LPUART1_TX, OCTOSPI1_NCS, PSSI_D5, TIM16_CH1N, TIM4_CH1, UART5_TX, USART1_TX
137	PB7	I/O	alt: DCMI_VSYNC, FDCAN1_TX, FMC_NL, I2C1_SDA, I2C4_SDA, I3C1_SDA, LPUART1_RX, PSSI_RDY, PWR_WKUP5, SDMMC2_CKIN, SDMMC2_D5, TIM17_CH1N, TIM4_CH2, USART1_RX
138	BOOT0	I
139	PB8	I/O	alt: DCMI_D6, ETH_MII_TXD3, FDCAN1_RX, I2C1_SCL, I2C4_SCL, I3C1_SCL, PSSI_D6, SDMMC1_CKIN, SDMMC1_D4, SDMMC2_D4, SPI4_RDY, TIM16_CH1, TIM4_CH3, UART4_RX
140	PB9	I/O	alt: DAC1_EXTI9, DCMI_D7, FDCAN1_TX, I2C1_SDA, I2C4_SDA, I2S2_WS, I3C1_SDA, PSSI_D7, SDMMC1_CDIR, SDMMC1_D5, SDMMC2_CKIN, SDMMC2_D5, SPI2_NSS, TIM17_CH1, TIM4_CH4, UART4_TX
141	PE0	I/O	alt: DCMI_D2, FDCAN1_RX, FMC_NBL0, LPTIM1_ETR, LPTIM2_CH2, LPTIM2_ETR, PSSI_D2, SAI2_MCLK_A, SPI3_RDY, TIM4_ETR, UART8_RX
142	VCAP	P
143	VSS	P
144	VDD	P

Unless otherwise specified, the parameters given in Table 92 are derived from tests performed under the ambient temperature, f PCLK2 frequency and V DDA supply voltage conditions summarized in Table 20: General operating conditions .

Table 92. 12-bit ADC characteristics (1)(2)

Symbol	Parameter	Conditions	Conditions	Conditions	Conditions	Conditions	Conditions	Min	Typ	Max	Unit
V DDA	Analog supply voltage for ADC ON	-	-	-	-	-	-	1.62	-	3.6	V
V REF+	Positive reference voltage	-	-	-	-	-	-	1.62	-	V DDA	V
V REF-	Negative reference voltage	-	-	-	-	-	-	V SSA	V SSA	V SSA	V
f ADC	ADC clock frequency	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.5	-	75	MHz
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Continuous Mode	1.8V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	5.00	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Continuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 70 MH z	SMP =2.5		4.66		MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Single or Discontinuous Mode	2.4V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 60MHz	SMP =2.5		4.00	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Single or Discontinuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 50MHz	SMP =2.5		3.33	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for fast channels (VIN[0:5])	Resolution = 10 bits	Continuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	5.77	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 10 bits	Single or Discontinuous Mode	2.4V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5		5.77	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 10 bits	Single or Discontinuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 65MHz	SMP =2.5		5.00	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 8 bits	All Modes	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	6.82	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 6 bits	All Modes	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	8.33	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 12 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 35MHz	SMP =2.5	-	2.30	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 10 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 35MHz	SMP =2.5	-	2.70	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 8 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 50MHz	SMP =2.5	-	4.50	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 6 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 50MHz	SMP =2.5	-	5.50	-	MSPS
t TRIG	External trigger period	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	-	-	15	1/f ADC

Table 92. 12-bit ADC characteristics (1)(2)

Table 92. 12-bit ADC characteristics (1)(2) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V AIN (2)	Conversion voltage range	-	0	-	V REF+	V
V CMIV	Common mode input voltage	-	V REF /2 - 10%	V REF /2	V REF /2+ 10%	V
R AIN (5)	External input impedance	Resolution = 12 bits, T J = 130°C (Tolerance 4 LSBs)	-	-	321	Ω
R AIN (5)	External input impedance	Resolution = 12 bits, T J = 125°C	-	-	220	Ω
R AIN (5)	External input impedance	Resolution = 10 bits, T J = 130°C	-	-	1039	Ω
R AIN (5)	External input impedance	Resolution = 10 bits, T J = 125°C	-	-	2100	Ω
R AIN (5)	External input impedance	Resolution = 8 bits, T J = 130°C	-	-	6327	Ω
R AIN (5)	External input impedance	Resolution = 8 bits, T J = 125°C	-	-	12000	Ω
R AIN (5)	External input impedance	Resolution = 6 bits, T J = 130°C	-	-	47620	Ω
R AIN (5)	External input impedance	Resolution = 6 bits, T J = 125°C	-	-	80000	Ω
C ADC	Internal sample and hold capacitor	-	-	3	-	pF
t ADCVREG_ STUP	ADC LDO startup time	-	-	5	10	μs
t STAB	ADC power-up time	LDO already started	1	-	-	conversion cycle
t OFF_CAL	Offset calibration time	-		1335
t LATR	Trigger conversion	CKMODE = 00	1.5	2	2.5
t LATR	latency for	CKMODE = 01	-	-	2.5
t LATR	regular and injected channels	CKMODE = 10			2.5
t LATR	without aborting the conversion	CKMODE = 11			2.25
t LATRINJ	Trigger	CKMODE = 00	2.5	3	3.5	1/f ADC
t LATRINJ	conversion latency for regular and	CKMODE = 01	-	-	3.5	1/f ADC
t LATRINJ	injected channels	CKMODE = 10	-	-	3.5	1/f ADC
t LATRINJ	when a regular conversion is aborted	CKMODE = 11	-	-	3.25	1/f ADC
t S	Sampling time	-	2.5	-	640.5	1/f ADC
t CONV	Total conversion time (including	N-bits resolution	t S + 0.5 + N

244

Table 92. 12-bit ADC characteristics (1)(2) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
I DDA_D(ADC)	ADC consumption on V DDA and V REF , Differential mode	fs= 5MSPS	-	600	-	μA
I DDA_D(ADC)	ADC consumption on V DDA and V REF , Differential mode	fs= 1MSPS	-	190	-	μA
I DDA_D(ADC)		fs= 0.1MSPS	-	50	-	μA
I DDA_SE(ADC)	ADC consumption on V DDA and V REF Single- ended mode	fs= 5MSPS	-	500	-	μA
I DDA_SE(ADC)	ADC consumption on V DDA and V REF Single- ended mode	fs= 1MSPS	-	150	-	μA
I DDA_SE(ADC)	ADC consumption on V DDA and V REF Single- ended mode	fs= 0.1MSPS	-	50	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =75MHz	-	265	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =50MHz		175	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =25MHz	-	90	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =12.5MHz	-	45	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =6.25MHz	-	22	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =3.125MHz	-	11	-	μA

1. The voltage booster on ADC switches must be used for V DDA < 2.7 V (embedded I/O switches).
2. These values are valid on BGA packages.
3. Depending on the package, V REF+ can be internally connected to V DDA and V REF- to V SSA .
4. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions, otherwise specified.

Table 93. Minimum sampling time versus R AIN (1)(2)

Resolution	R ( Ω )	Minimum sampling time (s)	Minimum sampling time (s)
Resolution	AIN	Fast channel	Slow channel (3)
12 bits	47	3.75E-08	6.12E-08
12 bits	68	3.94E-08	6.25E-08
12 bits	100	4.36E-08	6.51E-08
12 bits	150	5.11E-08	7.00E-08
12 bits	220	6.54E-08	7.86E-08
12 bits	330	8.80E-08	9.57E-08
12 bits	470	1.17E-07	1.23E-07
12 bits	680	1.60E-07	1.65E-07

Table 93. Minimum sampling time versus R AIN (1)(2)

Table 93. Minimum sampling time versus R AIN (1)(2) (continued)

• Resolution R AIN ( Ω ) Minimum sampling time (s)
• Resolution R AIN ( Ω ) Fast channel Slow channel (3)
• 47 3.19E-08 5.17E-08
• 68 3.35E-08 5.28E-08
• 100 3.66E-08 5.45E-08
• 150 4.35E-08 5.83E-08
• 220 5.43E-08 6.50E-08
• 330 7.18E-08 7.89E-08
• 470 9.46E-08 1.00E-07
• 680 1.28E-07 1.33E-07
• 1000 1.81E-07 1.83E-07
• 1500 2.63E-07 2.63E-07
• 2200 3.79E-07 3.76E-07
• 3300 5.57E-07 5.52E-07
• 47 2.64E-08 4.17E-08
• 68 2.76E-08 4.24E-08
• 100 3.02E-08 4.39E-08
• 150 3.51E-08 4.66E-08
• 220 4.27E-08 5.13E-08
• 330 5.52E-08 6.19E-08
• 470 7.17E-08 7.72E-08
• 680 9.68E-08 1.00E-07
• 1000 1.34E-07 1.37E-07
• 1500 1.93E-07 1.94E-07
• 2200 2.76E-07 2.74E-07
• 3300 4.06E-07 4.01E-07
• 4700 5.73E-07 5.62E-07
• 6800 8.21E-07 7.99E-07
• 10000 1.20E-06 1.17E-06
• 15000 1.79E-06 1.74E-06

244

Table 93. Minimum sampling time versus R AIN (1)(2) (continued)

Resolution	R AIN ( Ω )	Minimum sampling time (s)	Minimum sampling time (s)
Resolution	R AIN ( Ω )	Fast channel	Slow channel (3)
6 bits	47	2.14E-08	3.16E-08
6 bits	68	2.23E-08	3.21E-08
6 bits	100	2.40E-08	3.31E-08
6 bits	150	2.68E-08	3.52E-08
6 bits	220	3.13E-08	3.87E-08
6 bits	330	3.89E-08	4.51E-08
6 bits	470	4.88E-08	5.39E-08
6 bits	680	6.38E-08	6.79E-08
6 bits	1000	8.70E-08	8.97E-08
6 bits	1500	1.23E-07	1.24E-07
6 bits	2200	1.73E-07	1.73E-07
6 bits	3300	2.53E-07	2.49E-07
6 bits	4700	3.53E-07	3.45E-07
6 bits	6800	5.04E-07	4.90E-07
6 bits	10000	7.34E-07	7.11E-07
6 bits	15000	1.09E-06	1.05E-06

1. Specified by design - Not tested in production.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and V DDA = 1.6 V.
3. Slow channels correspond to all ADC inputs except for the fast channels.

Figure 54. ADC conversion timing diagram

Table 94. ADC accuracy (1)(2)

Symbol	Parameter	Conditions	Conditions	Min	Typ	Max	Unit
ET	Total unadjusted error	Fast and slow channels	Single ended	-	±3.5	±12	LSB
ET	Total unadjusted error	Fast and slow channels	Differential	-	±2.5	±7.5	LSB
EO	Offset error	-	Single ended	-	±3	±5.5
EO	Offset error	-	Differential	-	±2	±3.5
EG	Gain error	-	Single ended	-	±3.5	±11
EG	Gain error	-	Differential		±2.5	±7
ED	Differential linearity error	-	Single ended	-	±0.75	+2/-1
ED	Differential linearity error	-	Differential	-	±0.75	+2/-1
EL	Integral linearity error	Fast and	Single ended	-	±2	±6.5
EL	Integral linearity error	slow channels	Differential	-	±1	±4
ENOB	Effective number of bits	Single ended	Single ended	-	10.8	-	Bits
ENOB	Effective number of bits	Differential	Differential	-	11.5	-	Bits
SINAD	Signal-to-noise and distortion ratio	Single ended	Single ended	-	68	-	dB
SINAD	Signal-to-noise and distortion ratio	Differential	Differential	-	71	-	dB
SNR	Signal-to-noise ratio	Single ended	Single ended	-	70	-	dB
SNR	Signal-to-noise ratio	Differential	Differential	-	72	-	dB
THD	Total harmonic distortion	Single ended	Single ended	-	-70	-	dB
THD	Total harmonic distortion	Differential	Differential	-	-80	-	dB

Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics , Table 18: Current characteristics and Table 19 . Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 17. Voltage characteristics (1)

Symbol	Ratings	Min	Max	Unit
V DDx - V SS	External main supply voltage (including V DDSMPS (2) , V DDA , V DDUSB , V DDIO2 (2)(3)(4) , V BAT , and V REF+ )	-0.3	4.0	V
V DDIOx (4) - V SS	I/O supply when HSLV (2) = 0	-0.3	4.0	V
V DDIOx (4) - V SS	I/O supply when HSLV (2) = 1	-0.3	2.75	V
V IN (5)	Input voltage on FT_xxx pins except FT_c pins	V SS -0.3	min (min(V DD , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0 V) (6)(7)	V
V IN (5)	Input voltage on FT_t in V BAT mode	V SS -0.3	min (min(V BAT ,V DDA ,V DDUSB , V DDIO2 ) + 4.0V, 6.0 V)	V
V IN (5)	Input voltage on TT_xx pins	V SS -0.3	4.0	V
V IN (5)	Input voltage on BOOT0 pin	V SS	min (min(V DD , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0 V) (6)	V
V IN (5)	Input voltage on FT_c pins	V SS -0.3	5.5	V
V IN (5)	Input voltage on any other pins	V SS -0.3	4.0	V
V REF+ -V DDA	Allowed voltage difference for V REF+ > V DDA	-	0.4	V
\	∆ V DDx \		Variations between different V DDX power pins of the same domain	-
\	V SSx -V SS \		Variations between all the different ground pins	-

1. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
2. If HSLV = 0.
3. VDDIO1 or V DDIO2 . V DDIO1 = V DD .
4. VIN maximum must always be respected. Refer to the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
6. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.

Table 18. Current characteristics

Symbol	Ratings	Max	Unit
∑ IV DD	Total current into sum of all V DD power lines (source) (1)	350	mA
∑ IV SS	Total current out of sum of all V SS ground lines (sink) (1)	350	mA
IV DD	Maximum current into each V DD power pin (source) (1)	100	mA
IV SS	Maximum current out of each V SS ground pin (sink) (1)	100	mA
I IO(PIN)	Output current sourced by any I/O and control pin	20	mA
∑ I IO(PIN)	Total output current sunk by sum of all I/Os and control pins (2)	140	mA
∑ I IO(PIN)	Total output current sourced by sum of all I/Os and control pins (2)	140	mA
I INJ(PIN) (3)(4)	Injected current on FT_xxx, TT_xx, NRST pins	-5 / 0	mA
∑ \	I INJ(PIN) \		Total injected current (sum of all I/Os and control pins) (5)

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
2. Positive injection (when V IN > V DDIOx ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
3. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 17: Voltage characteristics for the minimum allowed input voltage values.
4. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 19. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	130 (1)	°C

The maximum chip-junction temperature, T Jmax , in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max × Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

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