STM32H563ZIT6

Part: STM32H563ZIT6 — STMicroelectronics

Type: ARM Cortex-M33 32-bit MCU with TrustZone and FPU

Description: 32-bit Arm Cortex-M33 MCU with TrustZone and FPU at up to 250 MHz (375 DMIPS), with 2 MB flash and 640 KB SRAM, operating from a 1.71–3.6 V supply.

Operating Conditions:

• Supply voltage (VDD): 1.71–3.6 V (HSLV = 0); 1.71–2.7 V (HSLV = 1)
• Operating temperature: suffix 6 grade (power dissipation specified at 85 °C ambient)
• Max HCLK frequency: 250 MHz (VOS0), 200 MHz (VOS1), 150 MHz (VOS2), 100 MHz (VOS3)
• VBAT: 1.2–3.6 V

Absolute Maximum Ratings:

• Max external main supply voltage (VDDx − VSS): 4.0 V
• Max I/O supply (VDDIOx − VSS): 4.0 V (HSLV = 0); 2.75 V (HSLV = 1)
• Max current into each VDD pin: 100 mA; total into all VDD lines: 350 mA
• Max output current sourced by any I/O pin: 20 mA
• Max junction temperature: 130 °C
• Storage temperature: −65 to +150 °C

Key Specs:

• Core voltage VCORE (internal regulator ON): 1.35 V typ (VOS0), 1.20 V typ (VOS1), 1.10 V typ (VOS2), 1.00 V typ (VOS3)
• VDDA analog supply: 1.62 V min with ADC, 1.8 V min with DAC, 2.1 V min with VREFBUF; max 3.6 V
• VDDUSB: 3.0–3.6 V when USB is used
• VDDIO2: 1.08–3.6 V when its I/Os are used
• I/O input voltage (FT_c pins): max 5.0 V
• Total injected current: ±25 mA
• Benchmarks: 1.5 DMIPS/MHz; 1023 CoreMark (4.092 CoreMark/MHz)

Features:

• Arm Cortex-M33 with TrustZone, FPU and MPU; 8 KB instruction cache and 4 KB data cache (ART accelerator)
• 2 MB flash with ECC (2 banks, read-while-write), 2 KB OTP, 640 KB SRAM, 4 KB backup SRAM
• Flexible memory controller (SRAM, PSRAM, FRAM, SDRAM, NOR/NAND) and one Octo-SPI interface
• Internal oscillators (64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI); external 4–50 MHz HSE and 32.768 kHz LSE
• Embedded LDO or SMPS step-down regulator; Sleep, Stop, Standby and VBAT modes
• Up to 139 fast I/Os, most 5 V tolerant
• Up to 24 timers; up to 12 U(S)ARTs plus 1 LPUART, up to 6 SPIs, 4 I2C FM+, one I3C, 2 SAI, 2 FD-CAN, 2 SDMMC
• USB 2.0 full-speed, USB Type-C/PD 3.1, Ethernet MAC, HDMI-CEC, camera interface (DCMI) and PSSI
• Two 12-bit ADCs (up to 5 MSPS) and two 12-bit DACs
• CORDIC and FMAC math accelerators; HASH accelerator; true random number generator (RNG)
• Secure firmware install (SFI), authenticated debug and active tampers
• SWD, JTAG and ETM debug
• ECOPACK2 compliant packages

Applications:

• Secure connected embedded systems
• Industrial and consumer control

Package:

• LQFP144 (the "Z" code in STM32H563ZIT6 denotes 144 pins; the "T" code denotes LQFP)

• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches and cryptographic peripherals.
• 32 32-bit backup registers:
• -The backup registers (TAMP_BKPxR) are implemented in the Backup domain that remains powered-on by V BAT when the V DD power is switched off.
• Up to 8 tamper pins for 8 external tamper detection events:
• -Active tamper mode: continuous comparison between tamper output and input to protect from physical open-short attacks
• -Flexible active tamper I/O management: from 4 meshes (each input associated to its own exclusive output) to 7 meshes (single output shared for up to 7 tamper inputs)
• -Passive tampers: ultra-low power edge or level detection with internal pull-up hardware management
• -Configurable digital filter

Note: As a tamper input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT modes. As a tamper output, only PC13, PA1, and PI8 are functional in Standby and VBAT modes.

• Internal tamper events to protect against transient or environmental perturbation attacks
• Each tamper can be configured in two modes:
• -Hardware mode: immediate erase of secrets on tamper detection, including backup registers erase
• -Software mode: erase of secrets following a tamper detection launched by software
• Any tamper detection can generate an RTC time stamp event.
• TrustZone support:
• -Tamper secure or non-secure configuration.
• -Backup registers configuration in 3 configurable-size areas:
• 1 read/write secure area
• 1 write secure/read non-secure area
• 1 read/write non-secure area
• -Secret key, stored in backup registers, protected against read and write access
• Tamper configuration and backup registers privilege protection

64

• Monotonic counter

Table 13. Legend/abbreviations used in the pinout table

Name	Name	Abbreviation	Definition
Pin name	Pin name	Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name	Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
		S	Supply pin
Pin type	Pin type	I	Input only pin
		I/O	Input/output pin
		FT	5V-tolerant I/O
		TT	3.6V-tolerant I/O
		RST	Bidirectional reset pin with embedded weak pull-up resistor
		Option for TT or FT I/Os (1)	Option for TT or FT I/Os (1)
		_a	I/O, with analog switch function supplied by V DDA
I/O structure	I/O structure	_c	I/O with USB Type-C power delivery function
		_d	I/O with USB Type-C power delivery dead battery function
		_f	I/O, Fm+ capable
		_h	I/O with high-speed low-voltage mode
		_s	I/O supplied only by V DDIO2
		_t	I/O with tamper function functional in VBAT mode
		_u	I/O, with USB function supplied by V DDUSB
Notes	Notes	Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.	Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
	Alternate functions	Functions selected through GPIOx_AFR registers	Functions selected through GPIOx_AFR registers
	Additional functions	Functions directly selected/enabled through peripheral registers	Functions directly selected/enabled through peripheral registers

Table 13. Legend/abbreviations used in the pinout table

77

78/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - WLCSP80 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - LQFP100 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - LQFP144 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - UFBGA169 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - LQFP176 SMPS UFBGA176+25 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - LQFP64	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - LQFP100	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - LQFP144	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - UFBGA169	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - LQFP176	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - UFBGA176+25	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - Pin name (function (3)(4) VFQFPN68	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - reset)	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - Pin type	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - I/O structure	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - Notes	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - Alternate functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition - Pin number (1)(2) after - Additional functions
	-	1	1 C3	1	D4	-	1		1	A1	1 A2	-	PE2	I/O	FT_h	-	TRACECLK, LPTIM1_IN2, SAI1_CK1, SPI4_SCK, SAI1_MCLK_A, USART10_RX, UART8_TX, OCTOSPI1_IO2, ETH_MII_TXD3, FMC_A23, DCMI_D3/PSSI_D3, EVENTOUT	-
DS14258	-	2	2 D4	2	B2	-	2	2	B2	2	A1	-	PE3	I/O	FT_h	-	TRACED0, TIM15_BKIN, SAI1_SD_B, USART10_TX, FMC_A19, EVENTOUT	TAMP_IN6/TAMP_OUT3
Rev 1	-	3	3	D3	3 C3	-	3	3	D4	3	B1	-	PE4	I/O	FT_h	-	TRACED1, SAI1_D2, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, FMC_A20, DCMI_D4/PSSI_D4, EVENTOUT	TAMP_IN7/TAMP_OUT8
	-	4	4	C2	4 D3	-	4	4	C2	4	B2	-	PE5	I/O	FT_h	-	TRACED2, SAI1_CK2, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6/PSSI_D6, EVENTOUT	TAMP_IN8/TAMP_OUT7
	-	5	5 D2	5	C2	-	5	5	D3	5	B3	-	PE6	I/O	FT_h	-	TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCLK_B, FMC_A22, DCMI_D7/PSSI_D7, EVENTOUT	TAMP_IN3/TAMP_OUT6
	A1	-	-	-	- -	-	-	-		- -	-	-	VDD	S	-	-	-	-
	B8	-	-	-	- -	-	-	-	-	-	-	-	VSS	S	-	-	-	-
	B10	6	6	C1	6 B1	1	6		6	E2 6	C1	1	VBAT	S	-	-	-	-
	D2	-	-	-	-	-	-	- -		- -	-	-	VSS	S	-	-	-	-

(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS	(1)(2) - Pin LQFP176 SMPS UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176 UFBGA176+25	(1)(2) - VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
-	-	- E4	7	E2	-	-	-	E3	7	D2 -	PI8	I/O	FT_t	(5)	EVENTOUT	TAMP_IN2/TAMP_OUT3, RTC_OUT2, WKUP3
C9	7	7 E3	8	E3	2	7	7	E4	8 D1	2	PC13	I/O	FT_t	(5)	EVENTOUT	TAMP_IN1/TAMP_OUT2/ TAMP_OUT3, RTC_OUT1/ RTC_TS, WKUP4
G9	-	- -	-	-	-	-	-	-	-	- -	VSS	S	-	-	-	-
D10	8	8 D1	9	D2	3	8	8	B1	9 E1	3	PC14- OSC32_ IN (OSC32_IN)	I/O	FT	-	EVENTOUT	OSC32_IN
F10	9	9 E1	10	D1	4	9	9	C1	10 F1	4	OSC32_OU T (OSC32_O UT)	I/O	FT	-	EVENTOUT	OSC32_OUT
-	-	- -	11	E1	-	-	-	-	11	D3 -	PI9	I/O	FT_h	-	UART4_RX, FDCAN1_RX, EVENTOUT	-
-	-	- -	12	F4	-	-	-	-	12 E3	-	PI10	I/O	FT_h	-	FDCAN1_RX,ETH_MII_RX_ER, PSSI_D14, EVENTOUT	-
-	-	- -	13	F3	-	-	-	F4	13	E4 -	PI11	I/O	FT	-	PSSI_D15, EVENTOUT	TAMP_IN4/TAMP_OUT5
-	- -	B2	14	C1	-	-	-	D2	14	D5 -	VSS	S	-	-	-	-
-	-	- B1	15	D5	-	-	-	D1	15	C5 -	VDD	S	-	-	-	-
-	-	10 E2	16	F2	-	-	10	F3	16	E2 -	PF0	I/O	FT_f	-	I2C2_SDA, FMC_A0, LPTIM5_CH1, EVENTOUT	-
-	-	11 F3	17	F1	-	-	11	E1	17 H3	-	PF1	I/O	FT_f	-	I2C2_SCL, FMC_A1, LPTIM5_CH2, EVENTOUT	-

80/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Pin	number	(1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
	WLCSP80 SMPS	LQFP100 SMPS LQFP144 SMPS		UFBGA169 SMPS LQFP176 SMPS	UFBGA176+25 SMPS	LQFP64	LQFP100	LQFP144	UFBGA169	LQFP176 UFBGA176+25	VFQFPN68	Pin name (function after reset) (3)(4)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
	- -	12	F4	18	G3	-	-	12	F2	18 H2	-	PF2	I/O	FT_h	-	LPTIM3_CH2, LPTIM3_IN2, I2C2_SMBA, UART12_TX, USART11_CK, FMC_A2, LPTIM5_IN1, EVENTOUT	-
	- -	13	G6	19	G2	-	-	13	F5	19 J2	-	PF3	I/O	FT_h	-	LPTIM3_IN1, USART11_TX, FMC_A3, LPTIM5_IN2, EVENTOUT	-
DS14258	- -	14	G5	20	G1	-	-	14	F1	20 J3	-	PF4	I/O	FT_h	-	LPTIM3_ETR, USART11_RX, FMC_A4, EVENTOUT	-
Rev 1	- -	15	G3	21	H3	-	-	15	F6	21 K3	-	PF5	I/O	FT_fh	-	LPTIM3_CH1, I2C4_SCL, I3C1_SCL, UART12_RX, USART11_CTS/USART11_NSS, FMC_A5, LPTIM3_IN1, EVENTOUT	-
	H2 10	16	F2	22	G4	-	10	16	G2	22 F2	-	VSS	S	-	-	-	-
	A7 11	17	G1	23	E4	-	11	17	G1	23 F3	-	VDD	S	-	-	-	-
	- -	18	G7	24	H1	-	-	18	G4	24 K2	-	PF6	I/O	FT_h	-	TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, OCTOSPI1_IO3, LPTIM5_CH1, EVENTOUT	-
	- -	19	F1	25	K2	-	-	19	G3	25 K1	-	PF7	I/O	FT_h	-	TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, OCTOSPI1_IO2, LPTIM5_CH2, EVENTOUT	-

WLCSP80 SMPS	LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS LQFP176 SMPS	UFBGA176+25 SMPS	LQFP64	LQFP100	LQFP144	UFBGA169	LQFP176 UFBGA176+25	VFQFPN68	Pin name (function after reset) (3)(4)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	- 20	G4	26	H2	-	-	20	G5	26 L3	-	PF8	I/O	FT_h	-	TIM16_CH1N, SPI5_MISO, SAI1_SCK_B, UART7_RTS, TIM13_CH1, OCTOSPI1_IO0, LPTIM5_IN1, EVENTOUT	-
-	- 21	G2	27	J3	-	-	21	H3	27 L2	-	PF9	I/O	FT_h	-	TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, OCTOSPI1_IO1, LPTIM5_IN2, EVENTOUT	-
-	- 22	H4	-	J4	-	-	22	G6	28 L1	-	PF10	I/O	FT_h	-	TIM16_BKIN, SAI1_D3, PSSI_D15, OCTOSPI1_CLK, DCMI_D11/PSSI_D11, EVENTOUT	-
K10	12 23	H1	28	J1	5	12	23	H1	29 G1	5	PH0- OSC_IN(PH 0)	I/O	FT	-	EVENTOUT	OSC_IN
J9	13 24	J1	29	J2	6	13	24	H2	30 H1	6	PH1- OSC_OUT( PH1)	I/O	FT	-	EVENTOUT	OSC_OUT
F8	14 25	H3	30	K3	7	14	25	H4	31 J1	7	NRST	I/O	RST	-	-	-
H8	15 26	J2	31	L1	8	15	26	J1	32 M2	8	PC0	I/O	FT_a	-	TIM16_BKIN, SAI1_MCLK_A, SPI2_RDY, SAI2_FS_B, FMC_A25, OCTOSPI1_IO7, FMC_SDNWE, EVENTOUT	ADC12_INP10

number (1)(2) - 82/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - WLCSP80 SMPS	LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS	Pin LQFP176 SMPS UFBGA176+25 SMPS	LQFP64	LQFP100	LQFP144	UFBGA169	LQFP176	UFBGA176+25 VFQFPN68	Pin name (function after reset) (3)(4)		Pin type	I/O structure	Notes	Alternate functions	Additional functions
	G7	16	27	J3	32 L2	9	16	27	J2	33	M3	9	PC1	I/O	FT_ah	-	TRACED0, SAI1_D1, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, USART11_RTS, SAI2_SD_A, SDMMC2_CK, OCTOSPI1_IO4, ETH_MDC, EVENTOUT	ADC12_INP11, ADC12_INN10, TAMP_IN3/TAMP_OUT5, WKUP6
DS14258 Rev 1	M10	17	28	K1	33 K4	10		17	28	J3 34	M4	10	PC2	I/O	FT_a	-	PWR_CSLEEP, TIM17_CH1, TIM4_CH4, SPI2_MISO/I2S2_SDI, OCTOSPI1_IO5, OCTOSPI1_IO2, ETH_MII_TXD2, FMC_SDNE0, EVENTOUT	ADC12_INP12, ADC12_INN11
	L9	18	29	K2	34	N3	11	18	29	H5 35	M5	11	PC3	I/O	FT_a	-	PWR_CSTOP, SAI1_D3, LPTIM3_CH1, SPI2_MOSI/I2S2_SDO, OCTOSPI1_IO6, OCTOSPI1_IO0, ETH_MII_TX_CLK, FMC_SDCKE0, EVENTOUT	ADC12_INP13, ADC12_INN12
	G1	-	-	-			-	- 30		M1 36		-			-	-	-	-
		-	-	H2	35	H4		-	-	M2	G3		VDD	S	-		-	-
	P2				-	K1	-			-	G2	-	VSS	S		-
	N9	19	30	L1	36	M2	12	19	31	K2	37 M1	12	VSSA	S	-	-	-	-
20	-	- - 20	-	L2	-	N2	-	- 21	32	K1 - L2	N1	-	VREF-	S	-	- -	- -	-
			31	M2	37	N1	-				38 P1	-	VREF+	S	-	-	-	-
22		21 P10	32	M1	38	M1	13		33	L1 39	R1	13	VDDA	S	-			-

(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176	(1)(2) - UFBGA176+25 VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
K8	22	33 K3	39	P2	14	23	34	J4	40	N3 14		PA0	I/O	FT_at	(5)	TIM2_CH1, TIM5_CH1, TIM8_ETR, TIM15_BKIN, SPI6_NSS, SPI3_RDY, USART2_CTS/USART2_NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH_MII_CRS, TIM2_ETR, EVENTOUT	ADC12_INP0, ADC12_INN1, TAMP_IN2/TAMP_OUT1, WKUP1
J7	23	34 H5	40	L3	15	24	35	J5	41	N2 15		PA1	I/O	FT_aht	(5)	TIM2_CH2, TIM5_CH2, TIM15_CH1N, LPTIM1_IN1, OCTOSPI1_DQS, USART2_RTS, UART4_RX, OCTOSPI1_IO3,SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_RMII_R EF_CLK, EVENTOUT	ADC12_INP1, TAMP_IN5/TAMP_OUT4
M8	24	35 L3	41	M3	16	25	36	L3	42	P2 16		PA2	I/O	FT_hat	(5)	TIM2_CH3, TIM5_CH3, TIM15_CH1, LPTIM1_IN2, USART2_TX, SAI2_SCK_B, ETH_MDIO, EVENTOUT	ADC12_INP14, TAMP_IN4/TAMP_OUT3, WKUP2
-	-	- J4	42	R2	-	-	-	K3	43	F4 -		PH2	I/O	FT_h	-	LPTIM1_IN2, OCTOSPI1_IO4, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, EVENTOUT	-
H10	- -	-	-	L4	-	-	-	-	-	K4 -	VDD		S	-	-	-	-
P8	-	-	- -	M4	-	-	-	-	-	L4 -		VSS	S	-	-	-	-
-	-	- N2	43	P3	-	-	-	N2	44	G4 -		PH3	I/O	FT_ah	-	OCTOSPI1_IO5,SAI2_MCLK_B, ETH_MII_COL, FMC_SDNE0, EVENTOUT	-

84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	84/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
	WLCSP80 SMPS LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS	LQFP176 SMPS	Pin UFBGA176+25 SMPS	number LQFP64	LQFP100 LQFP144	UFBGA169	LQFP176	UFBGA176+25	VFQFPN68	Pin name (function after reset) (3)(4)	Pin type	I/O structure	Notes	Alternate functions		Additional functions
	-	- -	N1	-	R1	-	-	-	N1	45	H4 -	PH4	I/O	FT_fa		-	I2C2_SCL, SPI5_RDY, SPI6_RDY, PSSI_D14, EVENTOUT	-
	-	-	-	L4 -	P1	-	-	-	M3	46	J4 -	PH5		I/O	FT_fa	-	I2C2_SDA, SPI5_NSS, SPI6_RDY, FMC_SDNWE, EVENTOUT	-
DS14258 Rev	T10	25 36	K4	44	N5	17	26	37	N3	47	R2 17	PA3		I/O	FT_ah	-	TIM2_CH4, TIM5_CH4, OCTOSPI1_CLK, TIM15_CH2, SPI2_NSS/I2S2_WS, SAI1_SD_B, USART2_RX, ETH_MII_COL, EVENTOUT	ADC12_INP15
1	-	26	37	M3 45	M7	18	27	38	M4	48 M8	18	VSS	S	-		-	-	-
	R1	27	38	N3 46	M6	19	28	39	N4	49	N8 19	VDD		S	-	-	-	-
	R9	28	39	M4 47	M5	20	29	40	L4	50	N4 20	PA4	I/O	TT_a		-	TIM5_ETR, LPTIM2_CH1, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS, DCMI_HSYNC/PSSI_DE, EVENTOUT	ADC12_INP18, DAC1_OUT1
	L7	29	40	J5 48	R3	21	30	41	K4	51 P4	21	PA5	I/O		TT_ah	-	TIM2_CH1, TIM8_CH1N, SPI1_SCK/I2S1_CK,SPI6_SCK, ETH_MII_TX_EN/ETH_RMII_TX _EN, PSSI_D14, TIM2_ETR, EVENTOUT	ADC12_INP19, ADC12_INN18, DAC1_OUT2

(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS LQFP144 SMPS	(1)(2)	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - UFBGA176+25 SMPS	(1)(2) - LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176	(1)(2) - UFBGA176+25 VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
H6	30 41	N4	49	P5	22	31	42	M5	52	P3 22		PA6	I/O	FT_ah	-	TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO/I2S1_SDI, OCTOSPI1_IO3, USART11_TX, SPI6_MISO, TIM13_CH1, DCMI_PIXCLK/PSSI_PDCK, EVENTOUT	ADC12_INP3
K6	31 42	K5	50	R4	23	32	43	K5	53	R3 23	PA7		I/O	FT_ah	-	TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SDO, USART11_RX, SPI6_MOSI, TIM14_CH1, OCTOSPI1_IO2, ETH_MII_RX_DV/ETH_RMII_CR S_DV, FMC_SDNWE, FMC_NWE, EVENTOUT	ADC12_INP7, ADC12_INN3
M6	- -	L5	51	N4	24	33	44	N5	54	N5 24	PC4		I/O	FT_a	-	TIM2_CH4, SAI1_CK1, LPTIM2_ETR, I2S1_MCK, USART3_RX, ETH_MII_RXD0/ETH_RMII_RXD 0, FMC_SDNE0, EVENTOUT	ADC12_INP4
N7	- -	M5	52	P4	25	34	45	H6	55	P5 25	PC5		I/O	FT_ah	-	TIM1_CH4N, SAI1_D3, PSSI_D15, SAI1_FS_A, UART12_RTS, OCTOSPI1_DQS, ETH_MII_RXD1/ETH_RMII_RXD 1, FMC_SDCKE0, EVENTOUT	ADC12_INP8, ADC12_INN4
T8	-	- -	-	M8	-	-	-	-	-	- -	VDD		S	-	-	-	-

86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	86/275 Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after	Pin number (1)(2) after
	WLCSP80 SMPS	LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS LQFP176 SMPS	UFBGA176+25 SMPS	LQFP64	LQFP100	LQFP144	UFBGA169	LQFP176 UFBGA176+25	VFQFPN68	Pin name (function reset) (3)(4)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
	R7	32	43 N5	53	R5	26	35	46	L5	56 R5	26	PB0	I/O	FT_ah	-	TIM1_CH2N, TIM3_CH3, TIM8_CH2N, OCTOSPI1_IO1, USART11_CK, UART4_CTS, ETH_MII_RXD2, LPTIM3_CH1, EVENTOUT	ADC12_INP9, ADC12_INN5
	P6	33	44 H6	54	N6	27	36	47	K6 57	R4	27	PB1	I/O	FT_ah	-	TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OCTOSPI1_IO0, ETH_MII_RXD3, LPTIM3_CH2, EVENTOUT	ADC12_INP5
	L5	34	45	N6 55	P6	28	37	48	L6 58	M6	28	PB2	I/O	FT_ah	-	RTC_OUT2, SAI1_D1, TIM8_CH4N, SPI1_RDY, LPTIM1_CH1, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, OCTOSPI1_CLK, OCTOSPI1_DQS, SDMMC1_CMD, LPTIM5_ETR, EVENTOUT	LSCO
	-	-	46 J6	56	R6	-	-	49	J6 59	R6 -		PF11	I/O	FT_ah	-	SPI5_MOSI, OCTOSPI1_NCLK, SAI2_SD_B, FMC_NRAS, DCMI_D12/PSSI_D12, LPTIM6_CH1, EVENTOUT	ADC1_INP2
	-	-	47 K6	57	N7	-	-	50	N6 60	P6 -		PF12	I/O	FT_ah	-	FMC_A6, LPTIM6_CH2, EVENTOUT	ADC1_INP6, ADC1_INN2
	-	-	48 M7	58	-	-	-	51	M7 61	-	-	VSS	S	-	-	-	-
	-	-	49	N7 59	-	-	-	52	N7 62	N9	-	VDD	S	-	-	-	-
	-	-	50	H7 60	P7		-	- 53	H7 63	N6	-	PF13	I/O	FT_ah	-	I2C4_SMBA, FMC_A7, LPTIM6_IN1, EVENTOUT	ADC2_INP2

WLCSP80 SMPS	LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS LQFP176 SMPS	UFBGA176+25 SMPS	LQFP64	LQFP100	LQFP144	UFBGA169	LQFP176 UFBGA176+25	VFQFPN68	Pin name (function after reset) (3)(4)	Pin type I/O structure		Notes	Alternate functions	Additional functions
-	- 51	L6	61	R7	-	-	54	M6	64	R7 -	PF14	I/O	FT_fah	-	FMC_A8, LPTIM6_IN2, EVENTOUT	ADC2_INP6, ADC2_INN2
-	- 52	J7	62	N8	-	-	55	J7	65	P7 -	PF15	I/O	FT_fh	-	I2C4_SDA, I3C1_SDA,FMC_A9, EVENTOUT	-
-	- 53	M6	63	R8	-	-	56	L7	66	N7 -	PG0	I/O	FT_h	-	UART9_RX, FMC_A10, LPTIM4_IN1, EVENTOUT	-
-	- 54	K7	64	P8	-	-	57	K7	67	M7 -	PG1	I/O	FT_h	-	SPI2_MOSI/I2S2_SDO, UART9_TX, FMC_A11, EVENTOUT	-
T6	35 55	L7	65	R9	-	38	58	N8	68	R8 -	PE7	I/O	FT_ah	-	TIM1_ETR, UART12_RTS, UART7_RX, OCTOSPI1_IO4, FMC_D4/FMC_AD4, EVENTOUT	-
N5	36 56	J8	66	P9	-	39	59	G7	69	P8 -	PE8	I/O	FT_ah	-	TIM1_CH1N, UART12_CTS/UART12_NSS, UART7_TX, OCTOSPI1_IO5, FMC_D5/FMC_AD5, EVENTOUT	-
R5	37 57	N8	67	N9	-	40	60	L8	70	P9 -	PE9	I/O	FT_ah	-	TIM1_CH1, UART12_RX, UART7_RTS, OCTOSPI1_IO6, FMC_D6/FMC_AD6, EVENTOUT	-
-	- 58	-	68	-	-	-	61	-	71	- -	VSS	S	-	-	-	-
-	- 59	-	69	-	-	-	62	-	72	- -	VDD	S	-	-	-	-

	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
88/275	WLCSP80 SMPS	LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS LQFP176 SMPS	Pin UFBGA176+25 SMPS	number LQFP64	(1)(2) LQFP100	LQFP144	UFBGA169	LQFP176 UFBGA176+25	VFQFPN68	Pin name (function after reset) (3)(4)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
	M4	38 60	L8	70	R10	-	41	63	H8	73	R9 -	PE10	I/O	FT_ah	-	TIM1_CH2N, UART12_TX, UART7_CTS, OCTOSPI1_IO7, FMC_D7/FMC_AD7, EVENTOUT	-
DS14258	-	39 61	M8	71	P10	-	42	64	M8	74	P10 -	PE11	I/O	FT_ah	-	TIM1_CH2, SPI1_RDY, SPI4_NSS, OCTOSPI1_NCS, SAI2_SD_B, FMC_D8/FMC_AD8, EVENTOUT	-
Rev 1	-	40 62	M9	72	R11	-	43	65	K8	75	R10 -	PE12	I/O	FT_h	-	TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9/FMC_AD9, EVENTOUT	-
	-	41 63	K8	73	P11	-	44	66	L9	76	N11 -	PE13	I/O	FT_h	-	TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10/FMC_AD10, EVENTOUT	-
	-	42 64	J9	74	N10	-	45	67	J8	77	P11 -	PE14	I/O	FT_h	-	TIM1_CH4, SPI4_MOSI, SAI2_MCLK_B, FMC_D11/FMC_AD11, EVENTOUT	-
	-	43	65 L9	75	N11	-	46	68	N9	78	R11 -	PE15	I/O	FT_h	-	TIM1_BKIN, TIM1_CH4N, USART10_CK, FMC_D12/FMC_AD12, EVENTOUT	-

(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176	(1)(2) - UFBGA176+25	(1)(2) - Pin name (function after reset) (3)(4) VFQFPN68	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
P4	44 66	K9	76	M10	29	47	69		K9 79	R12	29	PB10	I/O	FT_f	-	TIM2_CH3, LPTIM3_CH1, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OCTOSPI1_NCS, ETH_MII_RX_ER, EVENTOUT	-
-	45 67	L10	77	N12	-	-	-	M9	80	R13	30	PB11	I/O	FT_f	-	TIM2_CH4, LPTIM2_ETR, I2C2_SDA, SPI2_RDY, SPI4_RDY, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX _EN, FMC_NBL1, EVENTOUT	-
T4	46 68	N9	78	R12	-	-		-	- -	-	-	VLXSMPS	S	-	-	-	-
R3	47	69 N10	79	R13	-	-		-	- -	-	-	VDDSMPS	S	-	-	-	-
N3	48 70	M10	80	P12	-		-	-	- -	-	-	VSSSMPS	S	-	-	-	-
T2	49 71	N11	81	R14	30	48		70	N10 81	M10	31	VCAP	S	-	-	-	-
-	50 72	M11	82	M9	31		49	71	M12 82	M9	32	VSS	S	-	-	-	-
-	51	73 N12	83	M11	32	50		72	N11 83	N10	33	VDD	S	-	-	-	-
-	- -	N13	84	P13	-		-	-	K10 84	M11	-	PH6	I/O	FT	-	TIM1_CH3N, TIM12_CH1, TIM8_CH1, I2C2_SMBA, SPI5_SCK, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8/PSSI_D8, EVENTOUT	-
-	-	- L11	85	P14	-	-	-		L10 85	N12	-	PH7	I/O	FT_f	-	TIM1_CH3, TIM8_CH1N, I2C3_SCL, SPI5_MISO, ETH_MII_RXD3,FMC_SDCKE1, DCMI_D9/PSSI_D9, EVENTOUT	-

90/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - WLCSP80 SMPS LQFP100 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - LQFP144 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - UFBGA169 SMPS LQFP176 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - UFBGA176+25 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - LQFP64	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - LQFP100	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - LQFP144	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - UFBGA169	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - LQFP176	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - UFBGA176+25	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin number (1)(2) - VFQFPN68	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - after - Pin name (function reset) (3)(4)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin type	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - I/O structure	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Notes	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Alternate functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - functions - Additional
	-	- -	M12	-	N13	-	-	-		M10 86	M12 -		PH8	I/O	FT_fh	-	TIM1_CH2N, TIM5_ETR, TIM8_CH2, I2C3_SDA, SPI5_MOSI, DCMI_HSYNC/PSSI_DE, EVENTOUT	-
DS14258	- -	-	M13	86	M12	-	-	-	-	87	M13	-	PH9	I/O	FT_h	-	TIM1_CH2, TIM12_CH2, TIM8_CH2N, I2C3_SMBA, SPI5_NSS, DCMI_D0/PSSI_D0, EVENTOUT	-
Rev 1	-	- -	K10	87	N14	-	-	-	M11	88	L13 -		PH10	I/O	FT_h	-	TIM1_CH1N, TIM5_CH1, TIM8_CH3, I2C4_SMBA, SPI5_RDY, DCMI_D1/PSSI_D1, EVENTOUT	-
	-	- -	L13	88	P15	-	-	-	N12	89	L12 -		PH11	I/O	FT_fh	-	TIM1_CH1, TIM5_CH2, TIM8_CH3N, I2C4_SCL, I3C1_SCL, DCMI_D2/PSSI_D2, EVENTOUT	-
	-	- -	L12	89	M13	-	-	-	N13	90	K12 -	PH12		I/O	FT_fh	-	TIM1_BKIN, TIM5_CH3, TIM8_BKIN, I2C4_SDA, I3C1_SDA, TIM8_CH4N, DCMI_D3/PSSI_D3, EVENTOUT	-
	-	- -	-	90	H12	-	-	-	-	-	- -		VSS	S	-	-	-	-
	-	- -	-	91	J12	-	-	-	L13	91	J12 -		VDD	S	-	-	-	-

(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176	(1)(2) - UFBGA176+25 VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
L3	- -	K11	92	L12	33	51	73	K11	92	P12	34	PB12	I/O	FT_fh	-	TIM1_BKIN, OCTOSPI1_NCLK, I2C2_SDA,SPI2_NSS/I2S2_WS, UCPD1_FRSTX, USART3_CK, FDCAN2_RX, ETH_MII_TXD0/ETH_RMII_TXD 0, UART5_RX, EVENTOUT	-
M2	52 74	K12	93	R15	34	52	74	L11	93	P13 35		PB13	I/O	FT_c	-	TIM1_CH1N, LPTIM3_IN1, LPTIM2_CH1, I2C2_SMBA, SPI2_SCK/I2S2_CK, USART3_CTS/USART3_NSS, FDCAN2_TX, SDMMC1_D0, UART5_TX, EVENTOUT	UCPD1_CC1
N1	53 75	J10	94	N15	35	53	75	M13	94	R14 36		PB14	I/O	FT_c	-	TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS, UART4_RTS, SDMMC2_D0, LPTIM3_ETR, EVENTOUT	UCPD1_CC2
L1	54 76	H10	95	M14	36	54	76	J10	95	R15 37		PB15	I/O	FT_h	-	RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, USART11_CTS/USART11_NSS, UART4_CTS, SDMMC2_D1, OCTOSPI1_CLK, ETH_MII_TXD1/ETH_RMII_TXD 1, DCMI_D2/PSSI_D2, UART5_RX, EVENTOUT	PVD_IN

92/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - WLCSP80 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP100 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169 SMPS LQFP176 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin UFBGA176+25 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - number LQFP64	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - (1)(2) LQFP100	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP176	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA176+25 VFQFPN68	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin name (function after reset) (3)(4)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin type	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - I/O structure	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Notes	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Alternate functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Additional functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
	-	55 77	J11	96	M15	-	55	77	L12	96	P15 -	PD8	I/O	FT_h	-	USART3_TX, FMC_D13/FMC_AD13, EVENTOUT	-
	-	- -	-	-	G12	-	-	-	-	-	- -	VSS	S	-	-	-	-
	-	56 78	H9	97	L13	-	56	78	J9	97	P14 -	PD9	I/O	FT_h	-	USART3_RX, FDCAN2_RX, FMC_D14/FMC_AD14, EVENTOUT	-
DS14258 Rev	-	57 79	K13	98	K12	-	57	79	J11	98	N15 -	PD10	I/O	FT_h	-	LPTIM2_CH2, USART3_CK, FMC_D15/FMC_AD15, EVENTOUT	-
1	-	58 80	H8	99	L14	-	58	80	H10	99	N14 38	PD11	I/O	FT_h	-	SAI1_CK1, LPTIM2_IN2, I2C4_SMBA, USART3_CTS/USART3_NSS, UART4_RX, OCTOSPI1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT	-
	-	59 81	H11	100	K14	-	59	81	K12	100	N13 39	PD12	I/O	FT_fh	-	LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, I2C4_SCL, I3C1_SCL, SAI1_D1, USART3_RTS, UART4_TX, OCTOSPI1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, DCMI_D12/PSSI_D12, EVENTOUT	-
	(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176	(1)(2) - UFBGA176+25 VFQFPN68	(1)(2) - name (function reset) (3)(4)	(1)(2) - Pin after	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
	-	60 82	G8	101	L15	-	60	82	K13	101	M15	-	PD13	I/O	FT_fh	-	LPTIM1_CH1, TIM4_CH2, LPTIM2_CH1, I2C4_SDA, I3C1_SDA, OCTOSPI1_IO3, SAI2_SCK_A, UART9_RTS, FMC_A18, DCMI_D13/PSSI_D13, LPTIM4_IN1, EVENTOUT	-
DS14258	-	- 83	J12	102	-	-	-	83	H12	102	H12	-	VSS	S	-	-	-	-
	-	- 84	J13	103	-	-	-	84	H13	103	J13	-	VDD	S	-	-	-	-
Rev 1	K2	61 85	H12	104	K13	-	61	85	H11	104	M14	-	PD14	I/O	FT_h	-	TIM4_CH3, UART8_CTS, UART9_RX, FMC_D0/FMC_AD0, EVENTOUT	-
	J1	62 86	G10	105	J13	-	62	86	H9	105	L14	-	PD15	I/O	FT_h	-	TIM4_CH4, UART8_RTS, UART9_TX,FMC_D1/FMC_AD1, EVENTOUT	-
	-	- -	-	-	-	-	-	-	-	-	- -		VDD	S	-	-	-	-
-		- -	-	-	-	-	-	-	-	-	-	-	VSS	S	-	-	-	-
-		- 87	H13	106	K15	-	-		87	J12 106	L15	-	PG2	I/O	FT_h	-	TIM8_BKIN, UART12_RX, FMC_A12, LPTIM6_ETR, EVENTOUT	-
	-	- 88	G9	107	H14	-	-		88	G9 107	K15	-	PG3	I/O	FT_h	-	TIM8_BKIN2, UART12_TX, FMC_A13, LPTIM5_ETR, EVENTOUT	-
93/275	-	-	89 G11	108	J15	-	-		89	J13 108	K14	-	PG4	I/O	FT_h	-	TIM1_BKIN2, FMC_A14/FMC_BA0, LPTIM4_ETR, EVENTOUT	-

94/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - WLCSP80 SMPS LQFP100 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169 SMPS LQFP176 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin UFBGA176+25 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - number LQFP64	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - (1)(2) LQFP100	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP176	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA176+25 VFQFPN68	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin name (function after reset) (3)(4)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin type	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - I/O structure	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Notes	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Alternate functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Additional functions
	-	- 90	F8	109	H15	-	-	90	G10	109	K13	-	PG5	I/O	FT_h	-	TIM1_ETR, FMC_A15/FMC_BA1, EVENTOUT	-
DS14258	-	- 91	G12	110	J14	-	-	91	G11	110	J15 -		PG6	I/O	FT_fh	-	TIM17_BKIN, I3C1_SDA, I2C4_SDA, SPI1_RDY, OCTOSPI1_NCS, UCPD1_FRSTX, FMC_NE3, DCMI_D12/PSSI_D12, EVENTOUT	-
Rev 1	-	- 92	F9	111	H13	-	-	92	G8	111	J14	-	PG7	I/O	FT_fh	-	SAI1_CK2, I3C1_SCL, I2C4_SCL, SAI1_MCLK_A, USART6_CK, UCPD1_FRSTX, FMC_INT, DCMI_D13/PSSI_D13, EVENTOUT	-
	-	- 93	G13	112	G15	-	-	93	F11	112	H14 -		PG8	I/O	FT_h	-	TIM8_ETR, SPI6_NSS, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, EVENTOUT	-
	-	- 94	-	113	-	-	-	94	-	113	- -		VSS	S	-	-	-	-
	-	- 95	-	114	-	-	-	95	-	114	- -		VDD	S	-	-	-	-
	J3	63 96	F10	115	G14	37	63	96	F9	115	H15	40	PC6	I/O	FT_h	-	TIM3_CH1, TIM8_CH1, I2S2_MCK, SAI1_SCK_A, USART6_TX, SDMMC1_D0DIR, FMC_NWAIT, SDMMC2_D6, OCTOSPI1_IO5, SDMMC1_D6, DCMI_D0/PSSI_D0, EVENTOUT	-
	(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS LQFP144 SMPS	(1)(2) - UFBGA169 SMPS	(1)(2) - LQFP176 SMPS	(1)(2) - UFBGA176+25 SMPS	(1)(2) - LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176 UFBGA176+25	(1)(2) - VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
	K4	64 97	F11	116	G13	38	64	97	F10	116	G15 41		PC7	I/O	FT_h	-	TRGIO, TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC1_D123DIR, FMC_NE1, SDMMC2_D7, OCTOSPI1_IO6, SDMMC1_D7, DCMI_D1/PSSI_D1, EVENTOUT	-
DS14258 Rev	J5	65 98	E9	117	F14	39	65	98	G12	117	G14 42	PC8		I/O	FT_h	-	TRACED1, TIM3_CH3, TIM8_CH3, USART6_CK, UART5_RTS, FMC_NE2/FMC_NCE,FMC_INT, FMC_ALE, SDMMC1_D0, DCMI_D2/PSSI_D2, EVENTOUT	-
1	F2	66 99	F12	118	F13	40	66	99	G13	118	F14 43		PC9	I/O	FT_fh	-	MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, AUDIOCLK, UART5_CTS, OCTOSPI1_IO0, FMC_CLE, SDMMC1_D1, DCMI_D3/PSSI_D3, EVENTOUT	UCPD1_DB2
	-	- -	-	-	-	-	-	-	-	-	G12 -	VSS		S	-	-	-	-
	-	- -	-	-	-	-	-	-	-	-	G13 -	VDD		S	-	-	-	-
	G3	67 100	E10	119	F15	41	67	100	F12	119	F15 44	PA8		I/O	FT_fh	-	MCO1,TIM1_CH1,TIM8_BKIN2, I2C3_SCL, SPI1_RDY, USART1_CK, USB_SOF, UART7_RX, FMC_NOE, DCMI_D3/PSSI_D3, EVENTOUT	-

	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)
96/275	WLCSP80 SMPS	LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS	LQFP176 SMPS	UFBGA176+25 SMPS LQFP64	LQFP100	LQFP144 UFBGA169	LQFP176	UFBGA176+25 VFQFPN68	Pin name (function after	reset) (3)(4)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
96/275	H4	68	101 F13	120	E15	42	68	101	E11 120	E15	45	PA9	I/O	FT_d	-	TIM1_CH2, LPUART1_TX, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, ETH_MII_TX_ER, FMC_NWE,DCMI_D0/PSSI_D0, EVENTOUT	UCPD1_DB1
96/275	G5	69	102 E11	121	E14	43	69	102 E10	121	D15	46	PA10	I/O	FT_h	-	TIM1_CH3, LPUART1_RX, LPTIM2_IN2, UCPD1_FRSTX, USART1_RX, FDCAN2_TX, SDMMC1_D0, DCMI_D1/PSSI_D1, EVENTOUT	-
96/275	E1	70	103	C13 122	D15	44	70	103 F13	122	C15	47	PA11	I/O	FT_u	-	TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX, USB_DM, EVENTOUT	-
96/275	C1	71	104	B13 123	C15	45	71	104	E13 123	B15	48	PA12	I/O	FT_u	-	TIM1_ETR, LPUART1_RTS, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS, SAI2_FS_B, FDCAN1_TX, USB_DP, EVENTOUT	-
96/275	F4	72	105 D12	124	E13	46	72	105	E12 124	A15 49		PA13(JTMS /SWDIO)	I/O	FT	(6)	JTMS/SWDIO, EVENTOUT	-
96/275	-	74	107	E12 126	D14	47	74	107	C12 126	F12 50	VSS		S	-	-	-	-
96/275	-	75	108	D13 127	E12	48	75	108	C13 127	F13	51	VDD	S	-	-	-	-
	B2	73	106	E13	125	F12	- 73	106 D13	125	H13 -		VDDUSB	S	-	-	-	-

(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169 LQFP176	(1)(2) - UFBGA176+25 VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions	(1)(2)
-	-	- C12	128	B15	-	-	-	D12 128	E12 -		PH13	I/O	FT_h	-	LPTIM1_IN2, TIM8_CH1N, UART8_TX, UART4_TX, FDCAN1_TX, DCMI_D3/PSSI_D3, EVENTOUT	-
-	-	- D11	129	D13	-	-	-	D10 129	E13 -		PH14	I/O	FT_h	-	TIM8_CH2N, UART4_RX, FDCAN1_RX, DCMI_D4/PSSI_D4, EVENTOUT	-
-	-	- A13	130	C14	-	-	-	D11 130	D13 -		PH15	I/O	FT_h	-	TIM8_CH3N, DCMI_D11/PSSI_D11, EVENTOUT	-
-	-	- B12	131	-	-	-	-	B13 131	E14 -		PI0	I/O	FT_h	-	TIM5_CH4, SPI2_NSS/I2S2_WS, DCMI_D13/PSSI_D13, EVENTOUT	-
-	- -	C11	132	A15	-	-	-	B12 132	D14 -	PI1		I/O	FT_h	-	TIM8_BKIN2, SPI2_SCK/I2S2_CK, DCMI_D8/PSSI_D8, EVENTOUT	-
-	-	- D10	133	B14	-	-	-	A13 133	C14 -		PI2	I/O	FT_h	-	TIM8_CH4, SPI2_MISO/I2S2_SDI, DCMI_D9/PSSI_D9, EVENTOUT	-
-	-	- A12	134	A14	-	-	-	C11 134	C13 -		PI3	I/O	FT_h	-	TIM8_ETR, SPI2_MOSI/I2S2_SDO, DCMI_D10/PSSI_D10, EVENTOUT	-
-	-	- B8	135	D9	-	-	-	B10 135	D9 -	VSS		S	-	-	-	-
-	-	- A8	136	D8	-	-	-	A10 136	C9 -		VDD	S	-	-	-	-

98/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) (1)(2)
98/275	WLCSP80 SMPS	LQFP100 SMPS	LQFP144 SMPS	UFBGA169 SMPS	Pin LQFP176 SMPS	number UFBGA176+25 SMPS LQFP64	LQFP100	LQFP144	UFBGA169	LQFP176	UFBGA176+25 VFQFPN68	Pin name (function after reset) (3)(4)		Pin type	I/O structure	Notes	Alternate functions	Additional functions
98/275	E3	76 109	C10	137	B13	49	76	109	A12	137	A14	52	PA14(JTCK/ SWCLK)	I/O	FT	(6)	JTCK/SWCLK, EVENTOUT	-
98/275	D4	77	110 B10	138	C13	50	77	110	B11	138	A13	53	PA15(JTDI)	I/O	FT	(6)	JTDI, TIM2_CH1, LPTIM3_IN2, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS, UART4_RTS, UART7_TX, FMC_NBL1, DCMI_D11/PSSI_D11, TIM2_ETR, EVENTOUT	-
98/275	C3	78 111	A10	139	D12	51	78	111	C10	139	B14	54	PC10	I/O	FT_h	-	LPTIM3_ETR, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, OCTOSPI1_IO1, ETH_MII_TXD0/ETH_RMII_TXD 0, SDMMC1_D2, DCMI_D8/PSSI_D8, EVENTOUT	-
98/275	E5	79	112	A9 140	C12	52	79	112	A11	140	B13	55	PC11	I/O	FT_h	-	LPTIM3_IN1, SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, OCTOSPI1_NCS,SDMMC1_D3, DCMI_D4/PSSI_D4, EVENTOUT	-
98/275	F6	80 113	D9	141	C11	53	80		113 B9	141	A12 56		PC12	I/O	FT_h	-	TRACED3, TIM15_CH1, SPI6_SCK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, SDMMC1_CK, DCMI_D9/PSSI_D9, EVENTOUT	-
98/275	-	-	-	B11 -	D11	-		- -	-	-	- -	VSS		S	-	-	-	-
	(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - UFBGA176+25 SMPS	(1)(2) - LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176 UFBGA176+25	(1)(2) - VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions	(1)(2)
-	-	-	A11	-	D10	-	-	-	-	-	- -	VDD	S	-	-	-	-
A3		81 114	C9	142	B12	-	81	114	D9	142	B12 -	PD0	I/O	FT_h	-	TIM8_CH4N, UART4_RX, FDCAN1_RX, UART9_CTS, FMC_D2/FMC_AD2, EVENTOUT	-
B4		82 115	B9	143	A13	-	82	115	E9	143	C12 -	PD1	I/O	FT_h	-	UART4_TX, FDCAN1_TX, FMC_D3/FMC_AD3, EVENTOUT	-
A5	83	116	E8	144	C10	54	83	116	C9	144	D12 -	PD2	I/O	FT_h	-	TRACED2, TIM3_ETR, TIM15_BKIN, UART5_RX, SDMMC1_CMD, DCMI_D11/PSSI_D11, LPTIM4_ETR, EVENTOUT	WKUP7
-	84	117	C8	145	A12	-	84	117	A9	145	D11 -	PD3	I/O	FT_h	-	SPI2_SCK/I2S2_CK, USART2_CTS/USART2_NSS, FMC_CLK, DCMI_D5/PSSI_D5, EVENTOUT	WKUP8
-	85	118	D8	146	B11	-	85	118	F8	146	D10 -	PD4	I/O	FT_h	-	USART2_RTS, OCTOSPI1_IO4, FMC_NOE, EVENTOUT	-
-	86	119	A7	147	A11	-	86	119	D8	147	C11 -	PD5	I/O	FT_h	-	TIM1_CH4N, SPI2_RDY, USART2_TX, FDCAN1_TX, OCTOSPI1_IO5, FMC_NWE, EVENTOUT	-
-	-	120	-	148	-	-	-	120	B7	148	D8 -	VSS	S	-	-	-	-
-	-	121	A6	149	D7	-	-	121	A7	149	C8 -	VDDIO2	S	-	-	-	-

Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - WLCSP80 SMPS LQFP100 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169 SMPS LQFP176 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin UFBGA176+25 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - number LQFP64	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP100	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP176 UFBGA176+25	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - VFQFPN68	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin name (function after reset) (3)(4)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin type	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - I/O structure	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Notes	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Alternate functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Additional functions
- 87	122	F7	150	B10	-	87	122	E8	150	B11 -		PD6	I/O	FT_sh	-	SAI1_D1, SPI3_MOSI/I2S3_SDO, SAI1_SD_A, USART2_RX, OCTOSPI1_IO6, SDMMC2_CK, FMC_NWAIT, DCMI_D10/PSSI_D10, EVENTOUT	-
-	88 123	B7	151	A10	-	88	123	B8	151	A11 -		PD7	I/O	FT_sh	-	SPI1_MOSI/I2S1_SDO, USART2_CK, OCTOSPI1_IO7, SDMMC2_CMD, FMC_NE1/FMC_NCE, LPTIM4_OUT, EVENTOUT	-
- -	-	-	-	D6	-	-	-	-	-	- -		VSS	S	-	-	-	-
- -	124	E7	152	B9	-	-	124	F7	152	C10 -		PG9	I/O	FT_sh	-	SPI1_MISO/I2S1_SDI, USART6_RX, OCTOSPI1_IO6, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, DCMI_VSYNC/PSSI_RDY, EVENTOUT	-
- -	125	C7	153	A9	-	-	125	A8	153	B10 -	PG10		I/O	FT_sh	-	SPI1_NSS/I2S1_WS, SAI2_SD_B, SDMMC2_D1, FMC_NE3, DCMI_D2/PSSI_D2, EVENTOUT	-
(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144 UFBGA169	(1)(2) - LQFP176	(1)(2) - UFBGA176+25 VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions	(1)(2)
-	- -	-	154	C9	-	-	126 E7	154	B9	-	PG11	I/O	FT_sh	-	LPTIM1_IN2, SPI1_SCK/I2S1_CK, USART10_RX, USART11_RTS, SDMMC2_D2, ETH_MII_TX_EN/ETH_RMII_TX _EN, DCMI_D3/PSSI_D3, EVENTOUT	-
-	- 126	D7	155	B8	-	-	127 C8	155	B8 -		PG12	I/O	FT_sh	-	LPTIM1_IN1, PSSI_D15, SPI6_MISO, USART10_TX, USART6_RTS, SDMMC2_D3, ETH_MII_TXD1/ETH_RMII_TXD 1, FMC_NE4, DCMI_D11/PSSI_D11, LPTIM5_CH1, EVENTOUT	-
-	- 127	-	156	C8	-	-	128 D7	156	A8 -		PG13	I/O	FT_sh	-	TRACED0, LPTIM1_CH1, SPI6_SCK, USART10_CTS/USART10_NSS, USART6_CTS/USART6_NSS, SDMMC2_D6, ETH_MII_TXD0/ETH_RMII_TXD 0, FMC_A24, LPTIM5_CH2, EVENTOUT	-
-	- 128	-	157	A8	-	-	129 C7	157	A7 -		PG14	I/O	FT_sh	-	TRACED1, LPTIM1_ETR, LPTIM1_CH2, SPI6_MOSI, USART10_RTS, USART6_TX, OCTOSPI1_IO7, SDMMC2_D7, ETH_MII_TXD1/ETH_RMII_TXD 1, FMC_A25, LPTIM5_IN1, EVENTOUT	-
-	-	129 B4	158	-	-	-	130 -	158	D7 -	VSS		S	-	-	-	-

102/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - WLCSP80 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP100 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169 SMPS LQFP176 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin UFBGA176+25 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - number LQFP64	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - (1)(2) LQFP100	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP176 UFBGA176+25	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - VFQFPN68	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin name (function after reset) (3)(4)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin type	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - I/O structure	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Notes	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Alternate functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Additional functions
	-	- 130	A3	159	-	-	-	131	-	159	C7 -	VDD		S	-	-	-	-
	-	- 131	B6	160	A7	-	-	132	B6	160	B7 -	PG15		I/O	FT_h	-	SPI4_RDY, USART10_CK, USART6_CTS/USART6_NSS, FMC_NCAS, DCMI_D13/PSSI_D13, EVENTOUT	-
DS14258 Rev 1	C5	89 132	F6	161	B7	55	89	133	E6	161	A10 57	PB3(JTDO/ TRACESW O)		I/O	FT_fh	-	JTDO/TRACESWO, TIM2_CH2, I2C2_SDA, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, UART12_CTS/UART12_NSS, SPI6_SCK, SDMMC2_D2, CRS_SYNC, UART7_RX, LPTIM6_ETR, EVENTOUT	-
	B6	90 133	A5	162	C7	56	90	134	A6	162	A9 58	T)	PB4(NJTRS	I/O	FT_h	-	NJTRST, TIM16_BKIN, TIM3_CH1, OCTOSPI1_CLK, LPTIM1_CH2, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO, SDMMC2_D3, UART7_TX,DCMI_D7/PSSI_D7, EVENTOUT	-

(1)(2) - WLCSP80 SMPS LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS	(1)(2) - LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100	(1)(2) - LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176 UFBGA176+25	(1)(2) - VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2) - Alternate functions	(1)(2) - Additional functions
D6	91 134	E6	163	A6	57	91	135	C6	163	A6 59		PB5	I/O	FT_h	-	TIM17_BKIN, TIM3_CH2, OCTOSPI1_NCLK, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, I2C4_SMBA, SPI3_MOSI/I2S3_SDO, SPI6_MOSI, FDCAN2_RX, ETH_PPS_OUT,FMC_SDCKE1, DCMI_D10/PSSI_D10, UART5_RX, EVENTOUT	-
E7	92 135	C6	164	B6	58	92	136	A5	164	B6 60	PB6		I/O	FT_f	-	TIM16_CH1N, TIM4_CH1, I3C1_SCL, I2C1_SCL, HDMI_CEC, I2C4_SCL, USART1_TX, LPUART1_TX, FDCAN2_TX, OCTOSPI1_NCS, FMC_SDNE1, DCMI_D5/PSSI_D5,UART5_TX, EVENTOUT	-
C7	93 136	D6	165	C6	59	93	137	D6	165	B5 61		PB7	I/O	FT_fa	-	TIM17_CH1N, TIM4_CH2, I3C1_SDA, I2C1_SDA, I2C4_SDA, USART1_RX, LPUART1_RX, FDCAN1_TX, SDMMC2_D5, SDMMC2_CKIN, FMC_NL, DCMI_VSYNC/PSSI_RDY, EVENTOUT	WKUP5
D8	94	137 B5	166	A5	60	94	138	B5	166	D6 62	BOOT0		I	B	-	-	-

104/275	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - WLCSP80 SMPS LQFP100 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169 SMPS LQFP176 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin UFBGA176+25 SMPS	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - number LQFP64	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - (1)(2) LQFP100	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP144	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA169	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - LQFP176	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - UFBGA176+25 VFQFPN68	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin name (function after reset) (3)(4)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Pin type	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - I/O structure	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Notes	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Alternate functions	Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued) - Additional functions
	E9 95	138	F5	167	B5	61	95	139	E5	167	A5	63	PB8	I/O	FT_fh	-	TIM16_CH1, TIM4_CH3, I3C1_SCL, I2C1_SCL, SPI4_RDY, I2C4_SCL, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMI_D6/PSSI_D6, EVENTOUT	-
DS14258 Rev 1	-	96 139	E5	168	A4	-	96	140	A4	168	B4 64		PB9	I/O	FT_fh	-	TIM17_CH1, TIM4_CH4, I3C1_SDA, I2C1_SDA, SPI2_NSS/I2S2_WS,I2C4_SDA, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, SDMMC2_CKIN, SDMMC1_D5, DCMI_D7/PSSI_D7, EVENTOUT	-
	- 97	140	D5	169	C5	-	97	141	C5	169	A4 65		PE0	I/O	FT_h	-	LPTIM1_ETR, TIM4_ETR, LPTIM2_CH2, LPTIM2_ETR, SPI3_RDY, UART8_RX, FDCAN1_RX, SAI2_MCLK_A, FMC_NBL0,DCMI_D2/PSSI_D2, EVENTOUT	-
	- -	141	C5	170	B4	-	-	-	D5	170	A3 -		PE1	I/O	FT_h	-	LPTIM1_IN2, UART8_TX, FDCAN1_TX, FMC_NBL1, DCMI_D3/PSSI_D3, EVENTOUT	-
	A9 98	142	A4	171	A3	62	98	142	B4	171	C6 66	VCAP		S	-	-	-	-
	- 99	143	-	-	-	63	99	143	B3	-	- 67	VSS		S	-	-	-	-
	-	100 144	-	172	-	64	100	144	A3	172	-	68	VDD	S	-	-	-	-
(1)(2) - WLCSP80 SMPS	(1)(2) - LQFP100 SMPS	(1)(2) - LQFP144 SMPS	(1)(2) - UFBGA169 SMPS LQFP176 SMPS	(1)(2) - Pin UFBGA176+25 SMPS	(1)(2) - number LQFP64	(1)(2) - LQFP100 LQFP144	(1)(2) - UFBGA169	(1)(2) - LQFP176	(1)(2) - UFBGA176+25	(1)(2) - VFQFPN68	(1)(2) - Pin name (function after reset) (3)(4)	(1)(2) - Pin type	(1)(2) - I/O structure	(1)(2) - Notes	(1)(2)	(1)(2) - Alternate functions	(1)(2) - Additional functions	(1)(2)
-	-	- C4	173	B3 -		-	-	C4	173 D4	-	PI4	I/O	FT_h		-	TIM8_BKIN, SPI2_RDY, SAI2_MCLK_A, DCMI_D5/PSSI_D5, EVENTOUT	-
-	-	-	B3 174	A2	-	-	-	-	174	C4 -	PI5		I/O	FT_h	-	TIM8_CH1, SAI2_SCK_A, DCMI_VSYNC/PSSI_RDY, EVENTOUT	-
-	-	- A2	175	C4 -	-		-	C3	175 C3	-	PI6		I/O	FT_h	-	TIM8_CH2, SAI2_SD_A, DCMI_D6/PSSI_D6, EVENTOUT	-
-	-	- A1	176	A1 -	-		-	A2	176 C2	-		PI7	I/O	FT_h	-	TIM8_CH3, SAI2_FS_A, DCMI_D7/PSSI_D7, EVENTOUT	-
-	-	- -	-	F6	-	-	-	-	- F6	-	VSS		S	-	-	-	-
-	-	-	- -	F7	-	-	-	-	- F7	-	VSS		S	-	-	-	-
-	-	- -	-	F8	-	-	-	-	- F8	-		VSS	S	-	-	-	-
-	-	- -	-	F9	-	-	-	-	- F9	-	VSS		S	-	-	-	-
-	-	-	- -	F10	-	-	-	-	-	F10 -		VSS	S	-	-	-	-
-	- -	-	-	G6	-	-	-	-	-	G6 -	VSS		S	-	-	-	-
-	-	-	- -	G7	-	-	-	-	- G7	-	VSS		S	-	-	-	-
-	-	-	- -	G8	-	-	-	-	- G8	-	VSS		S	-	-	-	-
-	-	-	- -	G9	-	-	-	-	- G9	-	VSS		S	-	-	-	-
-	-	-	- -	G10	-	-	-	-	- G10	-		VSS	S	-	-	-	-
-	-	-	- -	H6	-	-	-	-	- H6	-	VSS		S	-	-	-	-
-	-	-	- -	H7	-	-	- -	-	H7	-	VSS	S	-		-	-	-
-	-	-	- -	- H8		-	- -	-	H8	-		VSS	S	-	-	-	-

Pin number (1)(2) after - WLCSP80 SMPS	Pin number (1)(2) after - LQFP100 SMPS	Pin number (1)(2) after - LQFP144 SMPS	Pin number (1)(2) after - UFBGA169 SMPS	Pin number (1)(2) after - LQFP176 SMPS	Pin number (1)(2) after - UFBGA176+25 SMPS	Pin number (1)(2) after - LQFP64	Pin number (1)(2) after - LQFP100	Pin number (1)(2) after - LQFP144	Pin number (1)(2) after - UFBGA169	Pin number (1)(2) after - LQFP176 UFBGA176+25	Pin number (1)(2) after - VFQFPN68	Pin number (1)(2) after - Pin name (function reset) (3)(4)	Pin type	I/O structure	Notes	Alternate functions	functions
-	-	-	-	-	H9	-	-	- -	-	H9	-	VSS	S	-	-	-	-
-	-	-	-	-	H10	-	-	-	- -	H10	-	VSS	S	-	-	-	-
-	-	-	-	-	J6	-	-	-	- -	J6	-	VSS	S	-	-	-	-
-	-	-	-	-	J7	-	-	-	- -	J7	-	VSS	S	-	-	-	-
-	-	-	-	-	J8	-	-	-	- -	J8	-	VSS	S	-	-	-	-
-	-	-	-	-	J9	-	-	-	- -	J9	-	VSS	S	-	-	-	-
-	-	-	-	-	J10	-	-	-	- -	J10	-	VSS	S	-	-	-	-
-	-	-	-	-	K6	-	-	-	-	- K6	-	VSS	S	-	-	-	-
-	-	-	-	-	K7	-	-	-	- -	K7	-	VSS	S	-	-	-	-
-	-	-	-	-	K8	-	-	-	- -	K8	-	VSS	S	-	-	-	-
-	-	-	-	-	K9	-	-	-	- -	K9	-	VSS	S	-	-	-	-
-	-	-	-	-	K10	-	-	-	- -	K10	-	VSS	S	-	-	-	-

1. The devices with SMPS correspond to commercial code STM32H53xIxxQ.
2. A non-connected I/O in a given package is configured as an output tied to VSS. When VREF+ pad is not available on a package, the internal voltage reference buffer (VREFBUF) is not available and must be kept disabled.
3. PC13, PC14 and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current, the use of PC13 to PC15 GPIOs in output mode is limited: The speed must not exceed 2 MHz with a maximum load of 30 pF. These GPIOs must not be used as current sources (for example to drive a LED).
4. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
5. As a tamper input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT mode. As a tamper output, only PC13, PA1, and PI8 are functional in Standby and VBAT mode.
6. After reset, these pins are configured as JTAG/SW debug alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated too.

Unless otherwise specified, the parameters given in Table 92 are derived from tests performed under the ambient temperature, f PCLK2 frequency and V DDA supply voltage conditions summarized in Table 20: General operating conditions .

Table 92. 12-bit ADC characteristics (1)(2)

Symbol	Parameter	Conditions	Conditions	Conditions	Conditions	Conditions	Conditions	Min	Typ	Max	Unit
V DDA	Analog supply voltage for ADC ON	-	-	-	-	-	-	1.62	-	3.6	V
V REF+	Positive reference voltage	-	-	-	-	-	-	1.62	-	V DDA	V
V REF-	Negative reference voltage	-	-	-	-	-	-	V SSA	V SSA	V SSA	V
f ADC	ADC clock frequency	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.62V ≤ V DDA ≤ 3.6 V	1.5	-	75	MHz
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Continuous Mode	1.8V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	5.00	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Continuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 70 MH z	SMP =2.5		4.66		MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Single or Discontinuous Mode	2.4V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 60MHz	SMP =2.5		4.00	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 12 bits	Single or Discontinuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 50MHz	SMP =2.5		3.33	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for fast channels (VIN[0:5])	Resolution = 10 bits	Continuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	5.77	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 10 bits	Single or Discontinuous Mode	2.4V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5		5.77	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 10 bits	Single or Discontinuous Mode	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 65MHz	SMP =2.5		5.00	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 8 bits	All Modes	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	6.82	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF		Resolution = 6 bits	All Modes	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 75MHz	SMP =2.5	-	8.33	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 12 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 35MHz	SMP =2.5	-	2.30	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 10 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 35MHz	SMP =2.5	-	2.70	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 8 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 50MHz	SMP =2.5	-	4.50	-	MSPS
f S (3) with RAIN=47 Ω and C PCB =22pF	Sampling rate for slow channels	Resolution = 6 bits	All modes (4)	1.6V ≤ V DDA ≤ 3.6V	-40°C ≤ T J ≤ 130°C	f ADC = 50MHz	SMP =2.5	-	5.50	-	MSPS
t TRIG	External trigger period	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	-	-	15	1/f ADC

Table 92. 12-bit ADC characteristics (1)(2)

Table 92. 12-bit ADC characteristics (1)(2) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V AIN (2)	Conversion voltage range	-	0	-	V REF+	V
V CMIV	Common mode input voltage	-	V REF /2 - 10%	V REF /2	V REF /2+ 10%	V
R AIN (5)	External input impedance	Resolution = 12 bits, T J = 130°C (Tolerance 4 LSBs)	-	-	321	Ω
R AIN (5)	External input impedance	Resolution = 12 bits, T J = 125°C	-	-	220	Ω
R AIN (5)	External input impedance	Resolution = 10 bits, T J = 130°C	-	-	1039	Ω
R AIN (5)	External input impedance	Resolution = 10 bits, T J = 125°C	-	-	2100	Ω
R AIN (5)	External input impedance	Resolution = 8 bits, T J = 130°C	-	-	6327	Ω
R AIN (5)	External input impedance	Resolution = 8 bits, T J = 125°C	-	-	12000	Ω
R AIN (5)	External input impedance	Resolution = 6 bits, T J = 130°C	-	-	47620	Ω
R AIN (5)	External input impedance	Resolution = 6 bits, T J = 125°C	-	-	80000	Ω
C ADC	Internal sample and hold capacitor	-	-	3	-	pF
t ADCVREG_ STUP	ADC LDO startup time	-	-	5	10	μs
t STAB	ADC power-up time	LDO already started	1	-	-	conversion cycle
t OFF_CAL	Offset calibration time	-		1335
t LATR	Trigger conversion	CKMODE = 00	1.5	2	2.5
t LATR	latency for	CKMODE = 01	-	-	2.5
t LATR	regular and injected channels	CKMODE = 10			2.5
t LATR	without aborting the conversion	CKMODE = 11			2.25
t LATRINJ	Trigger	CKMODE = 00	2.5	3	3.5	1/f ADC
t LATRINJ	conversion latency for regular and	CKMODE = 01	-	-	3.5	1/f ADC
t LATRINJ	injected channels	CKMODE = 10	-	-	3.5	1/f ADC
t LATRINJ	when a regular conversion is aborted	CKMODE = 11	-	-	3.25	1/f ADC
t S	Sampling time	-	2.5	-	640.5	1/f ADC
t CONV	Total conversion time (including	N-bits resolution	t S + 0.5 + N

Table 92. 12-bit ADC characteristics (1)(2) (continued)

244

Table 92. 12-bit ADC characteristics (1)(2) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
I DDA_D(ADC)	ADC consumption on V DDA and V REF , Differential mode	fs= 5MSPS	-	600	-	μA
I DDA_D(ADC)	ADC consumption on V DDA and V REF , Differential mode	fs= 1MSPS	-	190	-	μA
I DDA_D(ADC)		fs= 0.1MSPS	-	50	-	μA
I DDA_SE(ADC)	ADC consumption on V DDA and V REF Single- ended mode	fs= 5MSPS	-	500	-	μA
I DDA_SE(ADC)	ADC consumption on V DDA and V REF Single- ended mode	fs= 1MSPS	-	150	-	μA
I DDA_SE(ADC)	ADC consumption on V DDA and V REF Single- ended mode	fs= 0.1MSPS	-	50	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =75MHz	-	265	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =50MHz		175	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =25MHz	-	90	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =12.5MHz	-	45	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =6.25MHz	-	22	-	μA
I DD(ADC)	ADC consumption on V DD	f ADC =3.125MHz	-	11	-	μA

1. The voltage booster on ADC switches must be used for V DDA < 2.7 V (embedded I/O switches).
2. These values are valid on BGA packages.
3. Depending on the package, V REF+ can be internally connected to V DDA and V REF- to V SSA .
4. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions, otherwise specified.

Table 93. Minimum sampling time versus R AIN (1)(2)

Resolution	R ( Ω )	Minimum sampling time (s)	Minimum sampling time (s)
Resolution	AIN	Fast channel	Slow channel (3)
12 bits	47	3.75E-08	6.12E-08
12 bits	68	3.94E-08	6.25E-08
12 bits	100	4.36E-08	6.51E-08
12 bits	150	5.11E-08	7.00E-08
12 bits	220	6.54E-08	7.86E-08
12 bits	330	8.80E-08	9.57E-08
12 bits	470	1.17E-07	1.23E-07
12 bits	680	1.60E-07	1.65E-07

Table 93. Minimum sampling time versus R AIN (1)(2)

Table 93. Minimum sampling time versus R AIN (1)(2) (continued)

• Resolution R AIN ( Ω ) Minimum sampling time (s) - Fast channel Minimum sampling time (s) - Slow channel (3)
• 47 3.19E-08 5.17E-08
• 68 3.35E-08 5.28E-08
• 100 3.66E-08 5.45E-08
• 150 4.35E-08 5.83E-08
• 220 5.43E-08 6.50E-08
• 330 7.18E-08 7.89E-08
• 470 9.46E-08 1.00E-07
• 680 1.28E-07 1.33E-07
• 1000 1.81E-07 1.83E-07
• 1500 2.63E-07 2.63E-07
• 2200 3.79E-07 3.76E-07
• 3300 5.57E-07 5.52E-07
• 47 2.64E-08 4.17E-08
• 68 2.76E-08 4.24E-08
• 100 3.02E-08 4.39E-08
• 150 3.51E-08 4.66E-08
• 220 4.27E-08 5.13E-08
• 330 5.52E-08 6.19E-08
• 470 7.17E-08 7.72E-08
• 680 9.68E-08 1.00E-07
• 1000 1.34E-07 1.37E-07
• 1500 1.93E-07 1.94E-07
• 2200 2.76E-07 2.74E-07
• 3300 4.06E-07 4.01E-07
• 4700 5.73E-07 5.62E-07
• 6800 8.21E-07 7.99E-07
• 10000 1.20E-06 1.17E-06
• 15000 1.79E-06 1.74E-06

244

Table 93. Minimum sampling time versus R AIN (1)(2) (continued)

Resolution	R AIN ( Ω )	Minimum sampling time (s) - Fast channel	Minimum sampling time (s) - Slow channel (3)
6 bits	47	2.14E-08	3.16E-08
6 bits	68	2.23E-08	3.21E-08
6 bits	100	2.40E-08	3.31E-08
6 bits	150	2.68E-08	3.52E-08
6 bits	220	3.13E-08	3.87E-08
6 bits	330	3.89E-08	4.51E-08
6 bits	470	4.88E-08	5.39E-08
6 bits	680	6.38E-08	6.79E-08
6 bits	1000	8.70E-08	8.97E-08
6 bits	1500	1.23E-07	1.24E-07
6 bits	2200	1.73E-07	1.73E-07
6 bits	3300	2.53E-07	2.49E-07
6 bits	4700	3.53E-07	3.45E-07
6 bits	6800	5.04E-07	4.90E-07
6 bits	10000	7.34E-07	7.11E-07
6 bits	15000	1.09E-06	1.05E-06

1. Specified by design - Not tested in production.
2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and V DDA = 1.6 V.
3. Slow channels correspond to all ADC inputs except for the fast channels.

Figure 54. ADC conversion timing diagram

Table 94. ADC accuracy (1)(2)

Symbol	Parameter	Conditions	Conditions	Min	Typ	Max	Unit
ET	Total unadjusted error	Fast and slow channels	Single ended	-	±3.5	±12	LSB
ET	Total unadjusted error	Fast and slow channels	Differential	-	±2.5	±7.5	LSB
EO	Offset error	-	Single ended	-	±3	±5.5
EO	Offset error	-	Differential	-	±2	±3.5
EG	Gain error	-	Single ended	-	±3.5	±11
EG	Gain error	-	Differential		±2.5	±7
ED	Differential linearity error	-	Single ended	-	±0.75	+2/-1
ED	Differential linearity error	-	Differential	-	±0.75	+2/-1
EL	Integral linearity error	Fast and	Single ended	-	±2	±6.5
EL	Integral linearity error	slow channels	Differential	-	±1	±4
ENOB	Effective number of bits	Single ended	Single ended	-	10.8	-	Bits
ENOB	Effective number of bits	Differential	Differential	-	11.5	-	Bits
SINAD	Signal-to-noise and distortion ratio	Single ended	Single ended	-	68	-	dB
SINAD	Signal-to-noise and distortion ratio	Differential	Differential	-	71	-	dB
SNR	Signal-to-noise ratio	Single ended	Single ended	-	70	-	dB
SNR	Signal-to-noise ratio	Differential	Differential	-	72	-	dB
THD	Total harmonic distortion	Single ended	Single ended	-	-70	-	dB
THD	Total harmonic distortion	Differential	Differential	-	-80	-	dB

Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics , Table 18: Current characteristics and Table 19 . Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 17. Voltage characteristics (1)

Symbol	Ratings	Min	Max	Unit
V DDx - V SS	External main supply voltage (including V DDSMPS (2) , V DDA , V DDUSB , V DDIO2 (2)(3)(4) , V BAT , and V REF+ )	-0.3	4.0	V
V DDIOx (4) - V SS	I/O supply when HSLV (2) = 0	-0.3	4.0	V
V DDIOx (4) - V SS	I/O supply when HSLV (2) = 1	-0.3	2.75	V
V IN (5)	Input voltage on FT_xxx pins except FT_c pins	V SS -0.3	min (min(V DD , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0 V) (6)(7)	V
V IN (5)	Input voltage on FT_t in V BAT mode	V SS -0.3	min (min(V BAT ,V DDA ,V DDUSB , V DDIO2 ) + 4.0V, 6.0 V)	V
V IN (5)	Input voltage on TT_xx pins	V SS -0.3	4.0	V
V IN (5)	Input voltage on BOOT0 pin	V SS	min (min(V DD , V DDA , V DDUSB , V DDIO2 ) + 4.0, 6.0 V) (6)	V
V IN (5)	Input voltage on FT_c pins	V SS -0.3	5.5	V
V IN (5)	Input voltage on any other pins	V SS -0.3	4.0	V
V REF+ -V DDA	Allowed voltage difference for V REF+ > V DDA	-	0.4	V
| ∆ V DDx |	Variations between different V DDX power pins of the same domain	-	50.0	mV
|V SSx -V SS |	Variations between all the different ground pins	-	50.0	mV

1. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
2. If HSLV = 0.
3. VDDIO1 or V DDIO2 . V DDIO1 = V DD .
4. VIN maximum must always be respected. Refer to the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
6. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.

Table 18. Current characteristics

Symbol	Ratings	Max	Unit
∑ IV DD	Total current into sum of all V DD power lines (source) (1)	350	mA
∑ IV SS	Total current out of sum of all V SS ground lines (sink) (1)	350	mA
IV DD	Maximum current into each V DD power pin (source) (1)	100	mA
IV SS	Maximum current out of each V SS ground pin (sink) (1)	100	mA
I IO(PIN)	Output current sourced by any I/O and control pin	20	mA
∑ I IO(PIN)	Total output current sunk by sum of all I/Os and control pins (2)	140	mA
∑ I IO(PIN)	Total output current sourced by sum of all I/Os and control pins (2)	140	mA
I INJ(PIN) (3)(4)	Injected current on FT_xxx, TT_xx, NRST pins	-5 / 0	mA
∑ |I INJ(PIN) |	Total injected current (sum of all I/Os and control pins) (5)	±25	mA

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
2. Positive injection (when V IN > V DDIOx ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
3. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 17: Voltage characteristics for the minimum allowed input voltage values.
4. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 19. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	130 (1)	°C

The maximum chip-junction temperature, T Jmax , in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max × Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

270