Part: STM32H562xx and STM32H563xx from STMicroelectronics

Type: Arm Cortex-M33 32-bit MCU

Description: Arm Cortex-M33 32-bit MCU with TrustZone and FPU, operating up to 250 MHz, featuring up to 2 Mbytes Flash, 640 Kbytes SRAM, and integrated math accelerators.

Operating Conditions:

• Supply voltage: 1.71 V to 3.6 V
• Operating temperature: null
• Max CPU frequency: 250 MHz

Absolute Maximum Ratings:

• Max supply voltage: null
• Max continuous current: null
• Max junction/storage temperature: null

Key Specs:

• CPU: Arm Cortex-M33 with TrustZone, FPU, MPU, up to 250 MHz
• Performance: 375 DMIPS (Dhrystone 2.1), 1023 CoreMark
• Flash Memory: Up to 2 Mbytes with ECC, two banks read-while-write
• SRAM: 640 Kbytes (including 64-Kbyte SRAM2 with ECC and 320-Kbyte SRAM3 with flexible ECC)
• I/Os: Up to 140 fast I/Os with interrupt capability (most 5 V-tolerant)
• ADCs: Two 12-bit ADCs with up to 5 Msps
• DAC: One 12-bit DAC with two channels
• Timers: Up to 24 timers (18x 16-bit, 2x 32-bit, 2x watchdogs, 2x SysTick)

Features:

• Arm TrustZone with Armv8-M mainline security extension
• ART Accelerator (8-Kbyte instruction cache, 4-Kbyte data cache)
• Mathematical acceleration (CORDIC for trigonometric functions, FMAC for filter math)
• Low-power consumption modes: Sleep, Stop, and Standby
• Extensive communication interfaces: I2C, I3C, U(S)ART, SPI, SAI, FDCAN, USB, Ethernet MAC, HDMI-CEC

Applications:

• null

Package:

• LQFP64
• VFQFPN68
• WLCSP80
• LQFP100
• LQFP144
• UFBGA169
• LQFP176
• UFBGA(176+25)
• TFBGA225

• Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• MPCBB and TZIC accessible only with secure transactions
• -Enable illegal access events that may trigger a secure interrupt
• Secure and nonsecure access supported for privileged/non-privileged part of TZSC
• Set of registers to define product security settings:
• -Secure/privilege regions for external memories
• -Secure/privilege access mode for securable peripherals
• -Secure/privilege access mode for securable legacy masters

STM32H563VI/G LQFP64 Pinout

Notes

• Power pins: VBAT (pin 1), VDD (pins 19, 48, 61), VSS (pins 12, 18, 32, 47, 62), VDDA/VREF+ (pin 13), VSSA/VREF- (pin 12)
• Oscillator pins: PH0-OSC_IN (pin 5) and PH1-OSC_OUT (pin 6) for main oscillator; PC14-OSC32_IN (pin 3) and PC15-OSC32_OUT (pin 4) for 32 kHz oscillator
• Reset pin: NRST (pin 7) is active low
• All GPIO pins are bidirectional I/O capable with alternate function support

Unless otherwise specified, the parameters given in Table 95 are derived from tests performed under the ambient temperature, f HCLK frequency, and V DDA supply voltage conditions summarized in Table 20 .

Table 95. 12-bit ADC characteristics (1)(2)

Table 95. 12-bit ADC characteristics (1)(2)

Table 95. 12-bit ADC characteristics (1)(2) (continued)

241

1. This frequency is the analog ADC specification, it must respect the value in Table 21 .
2. These values are valid on BGA packages.
3. Depending upon the package, V REF+ can be internally connected to V DDA , and V REF- to V SSA .
4. The tolerance is two LSBs for 12-, 10-, and 8-bit resolutions, if not otherwise specified.

Table 96. Minimum sampling time versus R AIN (1)(2)

Table 96. Minimum sampling time versus R AIN (1)(2)

Table 96. Minimum sampling time versus R AIN (1)(2) (continued)

241

1. Slow channels correspond to all ADC inputs except for the fast channels.

Figure 56. ADC conversion timing diagram

Stresses above the absolute maximum ratings listed in Table 17 , Table 18 , and Table 19 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 17. Voltage characteristics (1)

1. HSLV = High-speed low-voltage mode. Refer to General purpose I/Os (GPIO) section of RM0481.
2. If HSLV = 0.
3. VDDIO1 or V DDIO2 . V DDIO1 = V DD .
4. VIN maximum must always be respected. Refer to the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
6. This formula must be applied on power supplies related to the I/O structure described by the pin definition table.

241

Table 18. Current characteristics

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
2. Positive injection (when V IN > V DDIOx ) is not possible on these I/Os, and does not occur for input voltages lower than the specified maximum value.
3. A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer to Table 17 for the minimum allowed input voltage values.
4. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 19. Thermal characteristics

The maximum chip-junction temperature, T Jmax in degrees Celsius, can be calculated using the following equation:

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.