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STM32G030C8

Arm Cortex-M0+ 32-bit MCU

The STM32G030C8 is a arm cortex-m0+ 32-bit mcu from STMicroelectronics. View the full STM32G030C8 datasheet below including key specifications, absolute maximum ratings.

STM32G030C8 shares its datasheet with STM32G030F6P6, whose page lists every part number it covers.

Official STM32G030C8 datasheet (PDF) — the source this page was extracted from.

Manufacturer

STMicroelectronics

Package

LQFP-48

STM32G030C8 Key Specifications

ParameterValue
ConnectivityI2C, IrDA, LINbus, SPI, SmartCard, UART/USART
Core ProcessorARM® Cortex®-M0+
Core Size32-Bit
Data ConvertersA/D 13x12b
DigiKey ProgrammableNot Verified
Mounting TypeSurface Mount
Number of I/O17
Operating Temperature-40°C ~ 85°C (TA)
Oscillator TypeExternal, Internal
Package / Case20-TSSOP (0.173", 4.40mm Width)
PackagingTube
PeripheralsDMA, I2S, POR, PWM, WDT
Flash Memory Size32KB (32K x 8)
Program Memory TypeFLASH
RAM Size8K x 8 B
Clock Speed64MHz
Standard Pack Qty1480
Supplier Device Package20-TSSOP
Supply Voltage2V ~ 3.6V

STM32G030C8 Overview

Part: STM32G030F6P6 (STM32G030x6/x8 family) — STMicroelectronics

Type: Arm Cortex-M0+ 32-bit MCU

Description: 32-bit Arm Cortex-M0+ MCU at up to 64 MHz with up to 64 KB Flash and 8 KB SRAM, 2.0–3.6 V supply, 12-bit ADC, 2x USART, 2x I2C, 2x SPI, in packages from 8 to 48 pins.

Operating Conditions:

  • Supply voltage (VDD/VDDA): 2.0–3.6 V
  • Operating temperature: -40 to 85 °C ambient (junction -40 to 105 °C)
  • Max HCLK/PCLK frequency: 64 MHz
  • VBAT backup operating voltage: 1.55–3.6 V

Absolute Maximum Ratings:

  • Max supply voltage (VDD): 4.0 V
  • Max current into VDD/VDDA pins: 100 mA
  • Max output current sunk/sourced by any I/O pin: 15 mA (20 mA sunk for FT_f pins)
  • Total output current sunk or sourced by all I/Os: 80 mA
  • Max junction temperature: 150 °C
  • Storage temperature: -65 to +150 °C

Key Specs:

  • CPU: Arm Cortex-M0+ up to 64 MHz
  • Memory: 8 KB SRAM with HW parity; up to 64 KB Flash (32 KB on the x6 variants)
  • ADC: 12-bit, 0.4 μs, up to 16 external channels, conversion range 0–3.6 V, up to 16-bit with hardware oversampling
  • I/O input voltage: -0.3 V to Min(VDD + 3.6, 5.5) V
  • I/O: up to 44 fast I/Os, multiple 5 V-tolerant
  • Communication: 2x I2C (Fast-mode Plus, 1 Mbit/s), 2x USART, 2x SPI (32 Mbit/s)
  • Timers: 8 (one 16-bit advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick)
  • DMA: 5-channel controller

Features:

  • Arm 32-bit Cortex-M0+ CPU with MPU
  • POR/PDR, low-power modes (Sleep, Stop, Standby), VBAT supply for RTC and backup registers
  • 32 kHz crystal oscillator, 4–48 MHz crystal oscillator, internal 16 MHz RC with PLL, internal 32 kHz RC (±5%)
  • CRC calculation unit
  • Calendar RTC with alarm and periodic wakeup from Stop/Standby
  • Serial wire debug (SWD)
  • ECOPACK 2 compliant

Applications:

  • Consumer, industrial and appliance domains
  • IoT solutions

Package:

  • TSSOP20 (STM32G030Fx)
  • SO8N (STM32G030Jx)
  • LQFP32 (STM32G030Kx)
  • LQFP48 (STM32G030Cx)

STM32G030C8 Features

  • Includes ST state-of-the-art patented technology
  • Core: Arm ® 32-bit Cortex ® -M0+ CPU, frequency up to 64 MHz
  • -40°C to 85°C operating temperature
  • Memories
  • -8 Kbytes of SRAM with HW parity check
  • -Up to 64 Kbytes of flash memory with protection
  • CRC calculation unit
  • Reset and power management
  • -Power-on/Power-down reset (POR/PDR)
  • -Voltage range: 2.0 V to 3.6 V
  • -Low-power modes: Sleep, Stop, Standby
  • -VBAT supply for RTC and backup registers
  • Clock management
  • -32 kHz crystal oscillator with calibration
  • -4 to 48 MHz crystal oscillator
  • -Internal 16 MHz RC with PLL option
  • -Internal 32 kHz RC oscillator (±5 %)
  • Up to 44 fast I/Os
  • -Multiple 5 V-tolerant I/Os
  • -All mappable on external interrupt vectors
  • 5-channel DMA controller with flexible mapping
  • 12-bit, 0.4 μs ADC (up to 16 ext. channels)
  • -Conversion range: 0 to 3.6V
  • -Up to 16-bit with hardware oversampling
  • 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
  • Calendar RTC with alarm and periodic wakeup from Stop/Standby

STM32G030C8 Pin Configuration

Figure 3. STM32G030Jx SO8N pinout

Figure 4. STM32G030Fx TSSOP20 pinout

Figure 5. STM32G030KxT LQFP32 pinout

34

Figure 6. STM32G030CxT LQFP48 pinout

Table 11. Terms and symbols used in Pin assignment and description table

ColumnSymbol Definition Terminal name corresponds parenthesis under the pinPin name to its by-default function at reset, unless otherwise name.
Supply pinSupply pin
II
Input
FT
RST Reset pin with embedded weak pull-up resistor
Options for FT I/Os
5 V tolerant I/O
_f
I/O structure I/O, Fm+ capable
_f
_e I/O, with switchable diode to V DDIO1 NoteUpon reset, all I/Os are set as analog inputs, unless otherwise specified.
Pin functionsAlternate functions
Functions selected through GPIOx_AFR registersAdditional functionsAdditional functions
Functions directly selected/enabled through peripheral registers
Functions directly selected/enabled through peripheral registers

Table 11. Terms and symbols used in Pin assignment and description table

Table 12. Pin assignment and description

Pin - SO8NPin - TSSOP20Pin - LQFP32Pin - LQFP48Pin name (function upon reset)Pin typeI/O structureNoteAlternate functionsAdditional functions
---1PC13I/OFT(1)(2)TIM1_BKTAMP_IN1, RTC_TS, RTC_OUT1, WKUP2
---2PC14- OSC32_IN (PC14)I/OFT(1)(2)TIM1_BK2OSC32_IN
122-PC14- OSC32_IN (PC14)I/OFT(1)(2)TIM1_BK2OSC32_IN, OSC_IN
-333PC15- OSC32_OUT (PC15)I/OFT(1)(2)OSC32_EN, OSC_ENOSC32_OUT
---4VBATS---VBAT
---5VREF+S----
2446VDD/VDDAS----
3557VSS/VSSAS----
---8PF0-OSC_IN (PF0)I/OFT-TIM14_CH1OSC_IN
---9PF1- OSC_OUT (PF1)I/OFT-OSC_ENOSC_OUT
46610NRSTI/ORST(3)-NRST
-7711PA0I/OFT_a(3)SPI2_SCK, USART2_CTS,ADC_IN0, TAMP_IN2,WKUP1
-8812PA1I/OFT_ea(3)SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, I2C1_SMBA, EVENTOUTADC_IN1
-9913PA2I/OFT_a(3)SPI1_MOSI/I2S1_SD, USART2_TX,ADC_IN2, WKUP4,LSCO
-101014PA3I/OFT_ea-SPI2_MISO, USART2_RX, EVENTOUTADC_IN3
---15PA4I/OFT_a-SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, EVENTOUTADC_IN4, RTC_OUT2

Table 12. Pin assignment and description

34

Table 12. Pin assignment and description (continued)

Pin - SO8NPin - TSSOP20Pin - LQFP32Pin - LQFP48Pin name (function upon reset)Pin typeI/O structureNoteAlternate functionsAdditional functions
-1111-PA4I/OFT_a-SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, EVENTOUTADC_IN4, TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2
-121216PA5I/OFT_ea-SPI1_SCK/I2S1_CK, EVENTOUTADC_IN5
-131317PA6I/OFT_ea-SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BK, TIM16_CH1ADC_IN6
-141418PA7I/OFT_a-SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1ADC_IN7
5151519PB0I/OFT_ea-SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2NADC_IN8
5151620PB1I/OFT_ea-TIM14_CH1, TIM3_CH4, TIM1_CH3N, EVENTOUTADC_IN9
-151721PB2I/OFT_ea-SPI2_MISO, EVENTOUTADC_IN10
---22PB10I/OFT_fa-SPI2_SCK, I2C2_SCLADC_IN11
---23PB11I/OFT_fa-SPI2_MOSI, I2C2_SDAADC_IN15
---24PB12I/OFT_a-SPI2_NSS, TIM1_BK, EVENTOUTADC_IN16
---25PB13I/OFT_f-SPI2_SCK, TIM1_CH1N, I2C2_SCL, EVENTOUT-
---26PB14I/OFT_f-SPI2_MISO, TIM1_CH2N, I2C2_SDA, EVENTOUT-
---27PB15I/OFT-SPI2_MOSI, TIM1_CH3N, EVENTOUTRTC_REFIN
5151828PA8I/OFT-MCO, SPI2_NSS, TIM1_CH1, EVENTOUT-
--1929PA9I/OFT_f-MCO, USART1_TX, TIM1_CH2, SPI2_MISO, I2C1_SCL, EVENTOUT-
--2030PC6I/OFT-TIM3_CH1-
---31PC7I/OFT-TIM3_CH2-

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

Pin - SO8NPin - TSSOP20Pin - LQFP32Pin - LQFP48Pin name (function upon reset)Pin typeI/O structureNoteAlternate functionsAdditional functions
--2132PA10I/OFT_f-SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BK, I2C1_SDA, EVENTOUT-
---33PA11 [PA9]I/OFT_f(4)SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BK2, I2C2_SCL-
51622-PA11 [PA9]I/OFT_fa(4)SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BK2, I2C2_SCLADC_IN15
---34PA12 [PA10]I/OFT_f(4)SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA-
61723-PA12 [PA10]I/OFT_fa(4)SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDAADC_IN16
7182435PA13I/OFT_ea(5)SWDIO, IR_OUT, EVENTOUTADC_IN17
8192536PA14-BOOT0I/OFT_a(5)SWCLK, USART2_TX, EVENTOUTADC_IN18, BOOT0
8192637PA15I/OFT-SPI1_NSS/I2S1_WS, USART2_RX, EVENTOUT-
---38PD0I/OFT-EVENTOUT, SPI2_NSS, TIM16_CH1-
---39PD1I/OFT-EVENTOUT, SPI2_SCK, TIM17_CH1-
---40PD2I/OFT-TIM3_ETR, TIM1_CH1N-
---41PD3I/OFT-USART2_CTS, SPI2_MISO, TIM1_CH2N-
-202742PB3I/OFT-SPI1_SCK/I2S1_CK, TIM1_CH2, USART1_RTS_DE_CK, EVENTOUT-
-202843PB4I/OFT-SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BK, EVENTOUT-

Table 12. Pin assignment and description (continued)

34

Table 12. Pin assignment and description (continued)

Pin - SO8NPin - TSSOP20Pin - LQFP32Pin - LQFP48Pin name (function upon reset)Pin typeI/O structureNoteAlternate functionsAdditional functions
8202944PB5I/OFT-SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BK, I2C1_SMBAWKUP6
8203045PB6I/OFT_f-USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, I2C1_SCL, EVENTOUT-
---46PB7I/OFT_f-USART1_RX, SPI2_MOSI, TIM17_CH1N, I2C1_SDA, EVENTOUT-
1131-PB7I/OFT_fa-USART1_RX, SPI2_MOSI, TIM17_CH1N, I2C1_SDA, EVENTOUTADC_IN11
113247PB8I/OFT_f-SPI2_SCK, TIM16_CH1, I2C1_SCL, EVENTOUT-
12148PB9I/OFT_f-IR_OUT, TIM17_CH1, SPI2_NSS, I2C1_SDA, EVENTOUT-
  1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
  • These GPIOs must not be used as current sources (for example to drive a LED).
  • The speed should not exceed 2 MHz with a maximum load of 30 pF
  1. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.
  2. As in SO8N device, the PA0, PA1, and PA2 GPIOs are bonded with NRST on the pin 4, low level applied to any of these GPIOs provokes the device reset. To prevent the risk of spurious resets, keep these GPIOs configured at all times as analog or digital inputs (as opposed to output or alternate function).
  3. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.
  4. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

Table 13. Port A alternate function mapping

PortAF0AF1AF2AF3AF4AF5AF6AF7
PA0SPI2_SCKUSART2_CTS------
PA1SPI1_SCK/ I2S1_CKUSART2_RTS _DE_CK----I2C1_SMBAEVENTOUT
PA2SPI1_MOSI/ I2S1_SDUSART2_TX------
PA3SPI2_MISOUSART2_RX-----EVENTOUT
PA4SPI1_NSS/ I2S1_WSSPI2_MOSI--TIM14_CH1--EVENTOUT
PA5SPI1_SCK/ I2S1_CK------EVENTOUT
PA6SPI1_MISO/ I2S1_MCKTIM3_CH1TIM1_BKIN--TIM16_CH1--
PA7SPI1_MOSI/ I2S1_SDTIM3_CH2TIM1_CH1N-TIM14_CH1TIM17_CH1--
PA8MCOSPI2_NSSTIM1_CH1----EVENTOUT
PA9MCOUSART1_TXTIM1_CH2-SPI2_MISO-I2C1_SCLEVENTOUT
PA10SPI2_MOSIUSART1_RXTIM1_CH3--TIM17_BKINI2C1_SDAEVENTOUT
PA11SPI1_MISO/ I2S1_MCKUSART1_CTSTIM1_CH4--TIM1_BKIN2I2C2_SCL-
PA12SPI1_MOSI/ I2S1_SDUSART1_RTS _DE_CKTIM1_ETR--I2S_CKINI2C2_SDA-
PA13SWDIOIR_OUT-----EVENTOUT
PA14SWCLKUSART2_TX-----EVENTOUT
PA15SPI1_NSS/ I2S1_WSUSART2_RX-----EVENTOUT

Table 13. Port A alternate function mapping

Table 14. Port B alternate function mapping

PortAF0AF1AF2AF3AF4AF5AF6AF7
PB0SPI1_NSS/ I2S1_WSTIM3_CH3TIM1_CH2N-----
PB1TIM14_CH1TIM3_CH4TIM1_CH3N----EVENTOUT
PB2-SPI2_MISO-----EVENTOUT
PB3SPI1_SCK/ I2S1_CKTIM1_CH2--USART1_RTS _DE_CK--EVENTOUT
PB4SPI1_MISO/ I2S1_MCKTIM3_CH1--USART1_CTSTIM17_BKIN-EVENTOUT
PB5SPI1_MOSI/ I2S1_SDTIM3_CH2TIM16_BKIN---I2C1_SMBA-
PB6USART1_TXTIM1_CH3TIM16_CH1N-SPI2_MISO-I2C1_SCLEVENTOUT
PB7USART1_RXSPI2_MOSITIM17_CH1N---I2C1_SDAEVENTOUT
PB8-SPI2_SCKTIM16_CH1---I2C1_SCLEVENTOUT
PB9IR_OUT-TIM17_CH1--SPI2_NSSI2C1_SDAEVENTOUT
PB10-----SPI2_SCKI2C2_SCL-
PB11SPI2_MOSI-----I2C2_SDA-
PB12SPI2_NSS-TIM1_BKIN----EVENTOUT
PB13SPI2_SCK-TIM1_CH1N---I2C2_SCLEVENTOUT
PB14SPI2_MISO-TIM1_CH2N---I2C2_SDAEVENTOUT
PB15SPI2_MOSI-TIM1_CH3N----EVENTOUT

Table 14. Port B alternate function mapping

STM32G030C8 Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 18 , Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to V SS .

Table 18. Voltage characteristics

SymbolRatingsMinMaxUnit
V DDExternal supply voltage-0.34.0V
V BATExternal supply voltage on VBAT pin-0.34.0V
V REF+External voltage on VREF+ pin-0.3Min(V DD + 0.4, 4.0)V
V IN (1)Input voltage on FT_xx-0.3V DD + 4.0 (2)(3)V
V IN (1)Input voltage on any other pin-0.34.0V
  1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
  2. When an FT_a pin is used by an analog peripheral such as ADC, the maximum V IN is 4 V.

Table 19. Current characteristics

SymbolRatingsMaxUnit
I VDD/VDDACurrent into VDD/VDDA power pin (source) (1)100mA
I VSS/VSSACurrent out of VSS/VSSA ground pin (sink) (2)100mA
I IO(PIN)Output current sunk by any I/O and control pin except FT_f15mA
I IO(PIN)Output current sunk by any FT_f pin20mA
I IO(PIN)Output current sourced by any I/O and control pin15mA

Table 19. Current characteristics

Table 19. Current characteristics (continued)

SymbolRatingsMaxUnit
∑ I IO(PIN)Total output current sunk by sum of all I/Os and control pins80mA
∑ I IO(PIN)Total output current sourced by sum of all I/Os and control pins80mA
I INJ(PIN) (2)Injected current on a FT_xx pin-5 / NA (3)mA
∑ |I INJ(PIN) |Total injected current (sum of all I/Os and control pins) (4)25mA
  1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  2. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature150°C

STM32G030C8 Thermal Information

The operating junction temperature T J must never exceed the maximum given in Table 21: General operating conditions

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:

$$T_J(max) = T_A(max) + P_D(max) \times \Theta_{JA}$$

STM32G030C8 Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

Variants on the same datasheet

These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.

Part NumberManufacturerPackage
STM32G030C6STMicroelectronicsLQFP-48
STM32G030C8T6STMicroelectronics48-LQFP
STM32G030F6P6STMicroelectronics20-TSSOP (0.173", 4.40mm Width)
STM32G030J6STMicroelectronicsSO8N
STM32G030K6STMicroelectronicsLQFP-32
STM32G030K8STMicroelectronicsLQFP-32
STM32G030X6/X8STMicroelectronics—

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