Overview

Part: STM32G030x6/x8 from STMicroelectronics

Type: Arm® Cortex®-M0+ 32-bit MCU

Key Specs:

CPU Frequency: up to 64 MHz
Flash Memory: Up to 64 Kbytes
SRAM: 8 Kbytes
Operating Voltage: 2.0 V to 3.6 V
Operating Temperature: -40°C to 85°C
ADC Resolution: 12-bit
ADC Conversion Time: 0.4 µs

Features:

Arm® 32-bit Cortex®-M0+ CPU
Up to 64 Kbytes of flash memory with protection
8 Kbytes of SRAM with HW parity check
CRC calculation unit
Power-on/Power-down reset (POR/PDR)
Low-power modes: Sleep, Stop, Standby
VBAT supply for RTC and backup registers
4 to 48 MHz crystal oscillator
32 kHz crystal oscillator with calibration
Internal 16 MHz RC with PLL option
Internal 32 kHz RC oscillator (±5 %)
Up to 44 fast I/Os, multiple 5 V-tolerant
5-channel DMA controller with flexible mapping
12-bit, 0.4 µs ADC (up to 16 ext. channels, up to 16-bit with hardware oversampling, 0 to 3.6V conversion range)
8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
Calendar RTC with alarm and periodic wakeup from Stop/Standby
Two I2C-bus interfaces (Fastmode Plus, 1 Mbit/s, extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode)
Two USARTs (master/slave synchronous SPI, one supporting ISO7816, LIN, IrDA, auto baud rate detection, wakeup)
Two SPIs (32 Mbit/s, 4- to 16-bit programmable bitframe, one multiplexed with I2S; two extra SPIs through USARTs)
Serial wire debug (SWD)
All packages ECOPACK 2 compliant

Applications:

null

Package:

LQFP48
LQFP32: 7 × 7 mm

Features

Includes ST state-of-the-art patented technology
Core: Arm® 32-bit Cortex®-M0+ CPU, frequency up to 64 MHz
-40°C to 85°C operating temperature
Memories
- Up to 64 Kbytes of flash memory with protection
- 8 Kbytes of SRAM with HW parity check
CRC calculation unit
Reset and power management
- Voltage range: 2.0 V to 3.6 V
- Power-on/Power-down reset (POR/PDR)
- Low-power modes: Sleep, Stop, Standby
- VBAT supply for RTC and backup registers
Clock management
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator with calibration
- Internal 16 MHz RC with PLL option
- Internal 32 kHz RC oscillator (±5 %)
Up to 44 fast I/Os
- All mappable on external interrupt vectors
- Multiple 5 V-tolerant I/Os
5-channel DMA controller with flexible mapping
12-bit, 0.4 µs ADC (up to 16 ext. channels)
- Up to 16-bit with hardware oversampling
- Conversion range: 0 to 3.6V
8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
Calendar RTC with alarm and periodic wakeup from Stop/Standby

LQFP48 LQFP32 (7 × 7 mm) (7 × 7 mm)

Communication interfaces
- Two I2C-bus interfaces supporting Fastmode Plus (1 Mbit/s) with extra current sink, one supporting SMBus/PMBus and wakeup from Stop mode
- Two USARTs with master/slave synchronous SPI; one supporting ISO7816 interface, LIN, IrDA capability, auto baud rate detection and wakeup feature
- Two SPIs (32 Mbit/s) with 4- to 16-bit programmable bitframe, one multiplexed with I2S interface; two extra SPIs through USARTs
Development support: serial wire debug (SWD)
All packages ECOPACK 2 compliant

Table 1. Device summary

Reference	Part number
STM32G030x6	STM32G030C6, STM32G030F6, STM32G030J6, STM32G030K6
STM32G030x8	STM32G030C8, STM32G030K8

Contents STM32G030x6/x8

Pin Configuration

Figure 3. STM32G030Jx SO8N pinout

Figure 4. STM32G030Fx TSSOP20 pinout

Figure 5. STM32G030KxT LQFP32 pinout

PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 PB12 PC13 PC14-OSC32_IN PC15-OSC32_OUT VBAT VREF+ VDD/VDDA VSS/VSSA NRST PF0-OSC_IN PF1-OSC_OUT PA0 PA1 PA14-BOOT0 PA13 PA12 [PA10] PA11 [PA9] PA10 PC7 PC6 PA9 PA8 PB15 PB14 PB13 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PD3 PD2 PD1 PD0 PA15 Top view LQFP48 1 2 3 4 6 7 8 9 10 11 12 36 35 34 33 32 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 14 15 16 17 18 19 20 21 22 23 24

Figure 6. STM32G030CxT LQFP48 pinout

Table 11. Terms and symbols used in Pin assignment and description table

| | Column | Symbol | Definition | |-----------|---------------------------------------------------------------------------------------------|---------------------------------|----------------------------------------------------------------------------------------------|--|--|--| | | Pin name | parenthesis under the pin name. | Terminal name corresponds to its by-default function at reset, unless otherwise specified in | | | | S
Supply pin | | | Pin type | I | Input only pin | | | | I/O | Input / output pin | | | | FT | 5 V tolerant I/O | | | | RST | Reset pin with embedded weak pull-up resistor | | | | | Options for FT I/Os | | | I/O structure | _f | I/O, Fm+ capable | | | | _a | I/O, with analog switch function | | | | _e | I/O, with switchable diode to VDDIO1 | | | Note | | Upon reset, all I/Os are set as analog inputs, unless otherwise specified. | | Pin | Alternate
functions | | Functions selected through GPIOx_AFR registers | | functions | Additional
Functions directly selected/enabled through peripheral registers
functions | Table 12. Pin assignment and description

| | | Pin | |------|---------|--------|--------|--------------------------------------|----------|---------------|--------|---------------------------------------------------------------|--------------------------------------| | SO8N | TSSOP20 | LQFP32 | LQFP48 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | - | - | - | 1 | PC13 | I/O | FT | (1)(2) | TIM1_BK | TAMP_IN1, RTC_TS,
RTC_OUT1, WKUP2 | | - | - | - | 2 | PC14-
OSC32_IN
(PC14) | I/O | FT | (1)(2) | TIM1_BK2 | OSC32_IN | | 1 | 2 | 2 | - | PC14-
OSC32_IN
(PC14) | I/O | FT | (1)(2) | TIM1_BK2 | OSC32_IN, OSC_IN | | - | 3 | 3 | 3 | PC15-
OSC32_OUT
(PC15) | I/O | FT | (1)(2) | OSC32_EN, OSC_EN | OSC32_OUT | | - | - | - | 4 | VBAT | S | - | - | - | VBAT | | - | - | - | 5 | VREF+ | S | - | - | - | - | | 2 | 4 | 4 | 6 | VDD/VDDA | S | - | - | - | - | | 3 | 5 | 5 | 7 | VSS/VSSA | S | - | - | - | - | | - | - | - | 8 | PF0-OSC_IN
(PF0) | I/O | FT | - | TIM14_CH1 | OSC_IN | | - | - | - | 9 | PF1-
OSC_OUT
(PF1) | I/O | FT | - | OSC_EN | OSC_OUT | | 4 | 6 | 6 | 10 | NRST | I/O | RST | (3) | - | NRST | | - | 7 | 7 | 11 | PA0 | I/O | FT_a | (3) | SPI2_SCK, USART2_CTS, | ADC_IN0,
TAMP_IN2,WKUP1 | | - | 8 | 8 | 12 | PA1 | I/O | FT_ea | (3) | SPI1_SCK/I2S1_CK,
USART2_RTS_DE_CK,
I2C1_SMBA, EVENTOUT | ADC_IN1 | | - | 9 | 9 | 13 | PA2 | I/O | FT_a | (3) | SPI1_MOSI/I2S1_SD,
USART2_TX, | ADC_IN2,
WKUP4,LSCO | | - | 10 | 10 | 14 | PA3 | I/O | FT_ea | - | SPI2_MISO, USART2_RX,
EVENTOUT | ADC_IN3 | | - | - | - | 15 | PA4 | I/O | FT_a | - | SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
EVENTOUT | ADC_IN4, RTC_OUT2 |

Table 12. Pin assignment and description (continued)

| | | Pin | |------|---------|--------|--------|--------------------------------------|----------|---------------|------|--------------------------------------------------------------------|--------------------------------------------------| | SO8N | TSSOP20 | LQFP32 | LQFP48 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | - | 11 | 11 | - | PA4 | I/O | FT_a | - | SPI1_NSS/I2S1_WS,
SPI2_MOSI, TIM14_CH1,
EVENTOUT | ADC_IN4,
TAMP_IN1, RTC_TS,
RTC_OUT1, WKUP2 | | - | 12 | 12 | 16 | PA5 | I/O | FT_ea | - | SPI1_SCK/I2S1_CK,
EVENTOUT | ADC_IN5 | | - | 13 | 13 | 17 | PA6 | I/O | FT_ea | - | SPI1_MISO/I2S1_MCK,
TIM3_CH1, TIM1_BK,
TIM16_CH1 | ADC_IN6 | | - | 14 | 14 | 18 | PA7 | I/O | FT_a | - | SPI1_MOSI/I2S1_SD,
TIM3_CH2, TIM1_CH1N,
TIM14_CH1, TIM17_CH1 | ADC_IN7 | | 5 | 15 | 15 | 19 | PB0 | I/O | FT_ea | - | SPI1_NSS/I2S1_WS,
TIM3_CH3, TIM1_CH2N | ADC_IN8 | | 5 | 15 | 16 | 20 | PB1 | I/O | FT_ea | - | TIM14_CH1, TIM3_CH4,
TIM1_CH3N, EVENTOUT | ADC_IN9 | | - | 15 | 17 | 21 | PB2 | I/O | FT_ea | - | SPI2_MISO, EVENTOUT | ADC_IN10 | | - | - | - | 22 | PB10 | I/O | FT_fa | - | SPI2_SCK, I2C2_SCL | ADC_IN11 | | - | - | - | 23 | PB11 | I/O | FT_fa | - | SPI2_MOSI, I2C2_SDA | ADC_IN15 | | - | - | - | 24 | PB12 | I/O | FT_a | - | SPI2_NSS, TIM1_BK,
EVENTOUT | ADC_IN16 | | - | - | - | 25 | PB13 | I/O | FT_f | - | SPI2_SCK, TIM1_CH1N,
I2C2_SCL, EVENTOUT | - | | - | - | - | 26 | PB14 | I/O | FT_f | - | SPI2_MISO, TIM1_CH2N,
I2C2_SDA, EVENTOUT | - | | - | - | - | 27 | PB15 | I/O | FT | - | SPI2_MOSI, TIM1_CH3N,
EVENTOUT | RTC_REFIN | | 5 | 15 | 18 | 28 | PA8 | I/O | FT | - | MCO, SPI2_NSS, TIM1_CH1,
EVENTOUT | - | | - | - | 19 | 29 | PA9 | I/O | FT_f | - | MCO, USART1_TX,
TIM1_CH2, SPI2_MISO,
I2C1_SCL, EVENTOUT | - | | - | - | 20 | 30 | PC6 | I/O | FT | - | TIM3_CH1 | - | | - | - | - | 31 | PC7 | I/O | FT | - | TIM3_CH2 | - |

Table 12. Pin assignment and description (continued)

| | | Pin | |------|---------|--------|--------|--------------------------------------|----------|---------------|------|----------------------------------------------------------------------------|-------------------------| | SO8N | TSSOP20 | LQFP32 | LQFP48 | Pin name
(function
upon reset) | Pin type | I/O structure | Note | Alternate
functions | Additional
functions | | - | - | 21 | 32 | PA10 | I/O | FT_f | - | SPI2_MOSI, USART1_RX,
TIM1_CH3, TIM17_BK,
I2C1_SDA, EVENTOUT | - | | - | - | - | 33 | PA11 [PA9] | I/O | FT_f | (4) | SPI1_MISO/I2S1_MCK,
USART1_CTS, TIM1_CH4,
TIM1_BK2, I2C2_SCL | - | | 5 | 16 | 22 | - | PA11 [PA9] | I/O | FT_fa | (4) | SPI1_MISO/I2S1_MCK,
USART1_CTS, TIM1_CH4,
TIM1_BK2, I2C2_SCL | ADC_IN15 | | - | - | - | 34 | PA12 [PA10] | I/O | FT_f | (4) | SPI1_MOSI/I2S1_SD,
USART1_RTS_DE_CK,
TIM1_ETR, I2S_CKIN,
I2C2_SDA | - | | 6 | 17 | 23 | - | PA12 [PA10] | I/O | FT_fa | (4) | SPI1_MOSI/I2S1_SD,
USART1_RTS_DE_CK,
TIM1_ETR, I2S_CKIN,
I2C2_SDA | ADC_IN16 | | 7 | 18 | 24 | 35 | PA13 | I/O | FT_ea | (5) | SWDIO, IR_OUT, EVENTOUT | ADC_IN17 | | 8 | 19 | 25 | 36 | PA14-BOOT0 | I/O | FT_a | (5) | SWCLK, USART2_TX,
EVENTOUT | ADC_IN18, BOOT0 | | 8 | 19 | 26 | 37 | PA15 | I/O | FT | - | SPI1_NSS/I2S1_WS,
USART2_RX, EVENTOUT | - | | - | - | - | 38 | PD0 | I/O | FT | - | EVENTOUT, SPI2_NSS,
TIM16_CH1 | - | | - | - | - | 39 | PD1 | I/O | FT | - | EVENTOUT, SPI2_SCK,
TIM17_CH1 | - | | - | - | - | 40 | PD2 | I/O | FT | - | TIM3_ETR, TIM1_CH1N | - | | - | - | - | 41 | PD3 | I/O | FT | - | USART2_CTS, SPI2_MISO,
TIM1_CH2N | - | | - | 20 | 27 | 42 | PB3 | I/O | FT | - | SPI1_SCK/I2S1_CK,
TIM1_CH2,
USART1_RTS_DE_CK,
EVENTOUT | - | | - | 20 | 28 | 43 | PB4 | I/O | FT | - | SPI1_MISO/I2S1_MCK,
TIM3_CH1, USART1_CTS,
TIM17_BK, EVENTOUT | - |

8 20 29 44 PB5 I/O FT - SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BK, I2C1_SMBA WKUP6 8 20 30 45 PB6 I/O FT_f - USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, I2C1_SCL, EVENTOUT - - - - 46 PB7 I/O FT_f - USART1_RX, SPI2_MOSI, TIM17_CH1N, I2C1_SDA, EVENTOUT - 1 1 31 - PB7 I/O FT_fa - USART1_RX, SPI2_MOSI, TIM17_CH1N, I2C1_SDA, EVENTOUT ADC_IN11 1 1 32 47 PB8 I/O FT_f - SPI2_SCK, TIM16_CH1, I2C1_SCL, EVENTOUT - IR_OUT, TIM17_CH1, Pin Pin name (function upon reset) Pin type I/O structure Note Alternate functions Additional functions SO8N TSSOP20 LQFP32 LQFP48

Table 12. Pin assignment and description (continued)

SPI2_NSS, I2C1_SDA, EVENTOUT

1 2 1 48 PB9 I/O FT_f -

^1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

^- The speed should not exceed 2 MHz with a maximum load of 30 pF

^- These GPIOs must not be used as current sources (for example to drive a LED).

^2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.

^3. As in SO8N device, the PA0, PA1, and PA2 GPIOs are bonded with NRST on the pin 4, low level applied to any of these GPIOs provokes the device reset. To prevent the risk of spurious resets, keep these GPIOs configured at all times as analog or digital inputs (as opposed to output or alternate function).

^4. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.

^5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
0 P A	S 2_ S C P I K	S 2_ C S U A R T T	-	-	-	-	-	-
P A 1	S / I P I 1_ S C K 2 S 1_ C K	U S A R T 2_ R T S D E_ C K _	-	-	-	-	I 2 C 1_ S M B A	E V E N T O U T
P A 2	S P / I I 1_ M O S I 2 S 1_ S D	U S A R T 2_ T X	-	-	-	-	-	-
P A 3	S P I 2_ M I S O	U S A R T 2_ R X	-	-	-	-	-	E V E N T O U T
P A 4	S / I P I 1_ N S S S S 2 1_ W	S P I 2_ M O S I	-	-	T I M 1 4_ C H 1	-	-	E V E N T O U T
P A 5	S / I P I 1_ S C K 2 S 1_ C K	-	-	-	-	-	-	E V E N T O U T
6 P A	S / I P I 1_ M I S O 2 S 1_ M C K	3_ C 1 T I M H	1_ T I M B K I N	-	-	1 6_ C 1 T I M H	-	-
P A 7	S P / I I 1_ M O S I 2 S 1_ S D	T I M 3_ C H 2	T I M 1_ C H 1 N	-	T I M 1 4_ C H 1	T I M 1 7_ C H 1	-	-
P A 8	C O M	S S S P I 2_ N	C T I M 1_ H 1	-	-	-	-	O E V E N T U T
P A 9	M C O	U S A R T 1_ T X	T I M 1_ C H 2	-	S P I 2_ M I S O	-	I 2 C 1_ S C L	E V E N T O U T
P A 1 0	S P I 2_ M O S I	U S A R T 1_ R X	T I M 1_ C H 3	-	-	T I M 1 7_ B K I N	I 2 C 1_ S D A	E V E N T O U T
P A 1 1	S / I P I 1_ M I S O S C 2 1_ M K	U S A R T 1_ C T S	T I M 1_ C H 4	-	-	T I M 1_ B K I N 2	I 2 C 2_ S C L	-
P A 1 2	S P / I I 1_ M O S I 2 S 1_ S D	U S A R T 1_ R T S D E_ C K _	T I M 1_ E T R	-	-	I 2 S_ C K I N	I 2 C 2_ S D A	-
P A 1 3	S W D I O	I R_ O U T	-	-	-	-	-	E V E N T O U T
P A 1 4	S C W L K	S U A R T 2_ T X	-	-	-	-	-	O E V E N T U T
P A 1 5	S / I P I 1_ N S S 2 S 1_ W S	U S A R T 2_ R X	-	-	-	-	-	E V E N T O U T

Table 14	Port B al	ternate fu	nction n	napping
----------	-----------	------------	----------	---------

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Table 15. Port C alternate function mapping

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
C P 6	-	C T I M 3_ H 1	-	-	-	-	-	-
P C 7	-	T I M 3_ C H 2	-	-	-	-	-	-
P C 1 3	-	-	T I M 1_ B K I N	-	-	-	-	-
P C 1 4	-	-	T I M 1_ B K I N 2	-	-	-	-	-
C 1 P 5	O S C 3 2_ E N	O S C_ E N	-	-	-	-	-	-

Table 16. Port D alternate function mapping

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
P D 0	E V E N T O U T	S P I 2_ N S S	T I M 1 6_ C H 1	-	-	-	-	-
P D 1	O E V E N T U T	S S C P I 2_ K	C T I M 1 7_ H 1	-	-	-	-	-
P D 2	-	T I M 3_ E T R	T I M 1_ C H 1 N	-	-	-	-	-
P D 3	U S A R T 2_ C T S	S P I 2_ M I S O	T I M 1_ C H 2 N	-	-	-	-	-

Table 17. Port F alternate function mapping

Po t r	A F 0	A F 1	A F 2	A F 3	A F 4	A F 5	A F 6	A F 7
P F 0	-	-	T I M 1 4_ C H 1	-	-	-	-	-
P F 1	O S C_ E N	-	-	-	-	-	-	-

Electrical Characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

Parameter values defined at temperatures or in temperature ranges out of the ordering information scope are to be ignored.

Packages used for characterizing certain electrical parameters may differ from the commercial packages as per the ordering information.

5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ±3σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ±2σ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8.

5.1.6 Power supply scheme

MSv47984V2 VDD Backup circuitry (LSE, RTC and backup registers) Kernel logic (CPU, digital and memories) Level shifter IO logic IN OUT Regulator GPIOs 1.55 V to 3.6 V 1 x 100 nF + 1 x 4.7 μF VDD/VDDA VBAT VCORE Power switch VDDIO1 ADC VREF+ VREF-VSS/VSSA VREF 100 nF VSS VSSA VDDA VDD VREF+

Figure 9. Power supply scheme

Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.

5.1.7 Current consumption measurement

Figure 10. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to VSS.

Table 18. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
VDD	External supply voltage	-0.3	4.0	V
VBAT	External supply voltage on VBAT pin	-0.3	4.0	V
VREF+	External voltage on VREF+ pin	-0.3	Min(VDD + 0.4, 4.0)	V
	Input voltage on FT_xx	-0.3	VDD + 4.0(2)(3)
VIN(1)	Input voltage on any other pin	-0.3	4.0	V

^1. Refer to Table 19 for the maximum allowed injected current values.

Table 19. Current characteristics

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)(1)	100	mA
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)(2)	100	mA
	Output current sunk by any I/O and control pin except FT_f	15
IIO(PIN)	Output current sunk by any FT_f pin	20	mA
	Output current sourced by any I/O and control pin	15
^2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

^3. When an FT_a pin is used by an analog peripheral such as ADC, the maximum VIN is 4 V.

Symbol	Ratings	Max	Unit
	Total output current sunk by sum of all I/Os and control pins	80
∑IIO(PIN)	Total output current sourced by sum of all I/Os and control pins	80	mA
IINJ(PIN)(2)	Injected current on a FT_xx pin	-5 / NA(3)	mA
∑ IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(4)	25	mA

Table 19. Current characteristics (continued)

1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.
2. A positive injection is induced by VIN > VDDIO1 while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	-65 to +150	°C
TJ	Maximum junction temperature	150	°C

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to VSS.

Table 18. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
VDD	External supply voltage	-0.3	4.0	V
VBAT	External supply voltage on VBAT pin	-0.3	4.0	V
VREF+	External voltage on VREF+ pin	-0.3	Min(VDD + 0.4, 4.0)	V
	Input voltage on FT_xx	-0.3	VDD + 4.0(2)(3)
VIN(1)	Input voltage on any other pin	-0.3	4.0	V

^1. Refer to Table 19 for the maximum allowed injected current values.

Table 19. Current characteristics

Symbol	Ratings	Max	Unit
IVDD/VDDA	Current into VDD/VDDA power pin (source)(1)	100	mA
IVSS/VSSA	Current out of VSS/VSSA ground pin (sink)(2)	100	mA
	Output current sunk by any I/O and control pin except FT_f	15
IIO(PIN)	Output current sunk by any FT_f pin	20	mA
	Output current sourced by any I/O and control pin	15
^2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

^3. When an FT_a pin is used by an analog peripheral such as ADC, the maximum VIN is 4 V.

Symbol	Ratings	Max	Unit
	Total output current sunk by sum of all I/Os and control pins	80
∑IIO(PIN)	Total output current sourced by sum of all I/Os and control pins	80	mA
IINJ(PIN)(2)	Injected current on a FT_xx pin	-5 / NA(3)	mA
∑ IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(4)	25	mA

Table 19. Current characteristics (continued)

1. All main power (VDD/VDDA, VBAT) and ground (VSS/VSSA) pins must always be connected to the external power supplies, in the permitted range.
2. A positive injection is induced by VIN > VDDIO1 while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage characteristics for the maximum allowed input voltage values.
1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
1. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	-65 to +150	°C
TJ	Maximum junction temperature	150	°C

Thermal Information

The operating junction temperature TJ must never exceed the maximum given in Table 21: General operating conditions

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:

$$T_J(max) = T_A(max) + P_D(max) \times \Theta_{JA}$$

where:

TA(max) is the maximum operating ambient temperature in °C,
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
PD = PINT + PI/O,
- PINT is power dissipation contribution from product of IDD and VDD
- PI/O is power dissipation contribution from output ports where:

$$P_{I/O} = \Sigma (V_{OL} \times I_{OL}) + \Sigma ((V_{DDIO1} - V_{OH}) \times I_{OH}),$$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Symbol	Parameter	Package	Value	Unit
ΘJA	Thermal resistance junction-ambient	SO8N 4.9 × 6 mm	134	°C/W
		TSSOP20 6.4 × 4.4 mm	88
		LQFP32 7 × 7 mm	84
		LQFP48 7 × 7 mm	84
ΘJB	Thermal resistance junction-board	SO8N 4.9 × 6 mm	86	°C/W
		TSSOP20 6.4 × 4.4 mm	57
		LQFP32 7 × 7 mm	76
		LQFP48 7 × 7 mm	76
ΘJC	Thermal resistance junction-board	SO8N 4.9 × 6 mm	30	°C/W
		TSSOP20 6.4 × 4.4 mm	19
		LQFP32 7 × 7 mm	42
		LQFP48 7 × 7 mm	42
Table 73. Package thermal characteristics

6.6.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (still air). Available from www.jedec.org.

STM32G030F6P6

Overview

Features

Pin Configuration

Table 15. Port C alternate function mapping

Table 16. Port D alternate function mapping

Table 17. Port F alternate function mapping

Electrical Characteristics

5.1 Parameter conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

5.1.6 Power supply scheme

5.1.7 Current consumption measurement

5.2 Absolute maximum ratings

Absolute Maximum Ratings

Thermal Information

where:

6.6.1 Reference document