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STM32G030F6

Arm Cortex-M0+ 32-bit MCU

The STM32G030F6 is a arm cortex-m0+ 32-bit mcu from STMicroelectronics. View the full STM32G030F6 datasheet below including key specifications, absolute maximum ratings.

Manufacturer

STMicroelectronics

Key Specifications

ParameterValue
ConnectivityI2C, IrDA, LINbus, SPI, SmartCard, UART/USART
Core ProcessorARM® Cortex®-M0+
Core Size32-Bit
Data ConvertersA/D 13x12b
DigiKey ProgrammableNot Verified
DigiKey ProgrammableNot Verified
Mounting TypeSurface Mount
Number of I/O17
Operating Temperature-40°C ~ 85°C (TA)
Oscillator TypeExternal, Internal
Oscillator TypeExternal, Internal
Package / Case20-TSSOP (0.173", 4.40mm Width)
PeripheralsDMA, I2S, POR, PWM, WDT
Flash Memory Size32KB (32K x 8)
Program Memory TypeFLASH
RAM Size8K x 8 B
Clock Speed64MHz
Supplier Device Package20-TSSOP
Supplier Device Package20-TSSOP
Supply Voltage2V ~ 3.6V

Overview

Part: STM32G030x6/x8 from STMicroelectronics

Type: ARM Cortex-M0+ 32-bit MCU

Description: A 32-bit ARM Cortex-M0+ MCU operating up to 64 MHz, featuring up to 64 KB Flash, 8 KB SRAM, multiple communication interfaces including I2C, USART, and SPI, and a 12-bit ADC, with a 2.0–3.6 V supply voltage.

Operating Conditions:

  • Supply voltage: 2.0 V to 3.6 V
  • Operating temperature: -40°C to 85°C
  • Max CPU frequency: 64 MHz

Absolute Maximum Ratings:

  • Max supply voltage: 4.0 V (VDD)
  • Max junction/storage temperature: 125 °C

Key Specs:

  • CPU: Arm® 32-bit Cortex®-M0+
  • CPU frequency: Up to 64 MHz
  • Flash memory: Up to 64 Kbytes
  • SRAM: 8 Kbytes with HW parity check
  • ADC: 12-bit, 0.4 μs (up to 16 external channels)
  • I/Os: Up to 44 fast I/Os, multiple 5 V-tolerant
  • I2C speed: 1 Mbit/s (Fast-mode Plus)
  • SPI speed: 32 Mbit/s

Features:

  • Low-power modes: Sleep, Stop, Standby
  • 5-channel DMA controller with flexible mapping
  • Calendar RTC with alarm and periodic wakeup
  • Internal 16 MHz RC with PLL option
  • Development support: Serial wire debug (SWD)

Applications:

  • null

Package:

  • SO8N
  • TSSOP20
  • LQFP32
  • LQFP48

Features

  • Includes ST state-of-the-art patented technology
  • Core: Arm ® 32-bit Cortex ® -M0+ CPU, frequency up to 64 MHz
  • -40°C to 85°C operating temperature
  • Memories
  • -8 Kbytes of SRAM with HW parity check
  • -Up to 64 Kbytes of flash memory with protection
  • CRC calculation unit
  • Reset and power management
  • -Power-on/Power-down reset (POR/PDR)
  • -Voltage range: 2.0 V to 3.6 V
  • -Low-power modes: Sleep, Stop, Standby
  • -VBAT supply for RTC and backup registers
  • Clock management
  • -32 kHz crystal oscillator with calibration
  • -4 to 48 MHz crystal oscillator
  • -Internal 16 MHz RC with PLL option
  • -Internal 32 kHz RC oscillator (±5 %)
  • Up to 44 fast I/Os
  • -Multiple 5 V-tolerant I/Os
  • -All mappable on external interrupt vectors
  • 5-channel DMA controller with flexible mapping
  • 12-bit, 0.4 μs ADC (up to 16 ext. channels)
  • -Conversion range: 0 to 3.6V
  • -Up to 16-bit with hardware oversampling
  • 8 timers: 16-bit for advanced motor control, four 16-bit general-purpose, two watchdogs, SysTick timer
  • Calendar RTC with alarm and periodic wakeup from Stop/Standby

Pin Configuration

Figure 3. STM32G030Jx SO8N pinout

Figure 4. STM32G030Fx TSSOP20 pinout

Figure 5. STM32G030KxT LQFP32 pinout

34

Figure 6. STM32G030CxT LQFP48 pinout

Table 11. Terms and symbols used in Pin assignment and description table

ColumnSymbol Definition Terminal name corresponds parenthesis under the pinPin name to its by-default function at reset, unless otherwise name.
Supply pinSupply pin
II
Input
FT
RST Reset pin with embedded weak pull-up resistor
Options for FT I/Os
5 V tolerant I/O
_f_f
I/O structure I/O, Fm+ capable _a NoteI/O, with analog switch function Functions Functions
_e I/O, with switchable diode to V DDIO1Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Pin functionsAlternate functions
selected through GPIOx_AFR registersAdditional functionsAdditional functions
directly selected/enabled through peripheral registers
directly selected/enabled through peripheral registers

Table 12. Pin assignment and description

PinPinPinPin
SO8NTSSOP20LQFP32LQFP48
---1
---2
122-
-333
---4
---5
2446
3557
---8
---9
46610
-7711
-8812
-9913
-101014
---15

Table 12. Pin assignment and description

34

Table 12. Pin assignment and description (continued)

PinPinPinPin
SO8NTSSOP20LQFP32LQFP48
-1111-
-121216
-131317
-141418
5151519
5151620
-151721
---22
---23
---24
---25
---26
---27
5151828
--1929
--2030
---31

Table 12. Pin assignment and description (continued)

Table 12. Pin assignment and description (continued)

PinPinPinPin
SO8NTSSOP20LQFP32LQFP48
--2132
---33
51622-
---34
61723-
7182435
8192536
8192637
---38
---39
---40
---41
-202742
-202843

Table 12. Pin assignment and description (continued)

34

Table 12. Pin assignment and description (continued)

PinPinPinPin
SO8NTSSOP20LQFP32LQFP48
8202944
8203045
---46
1131-
113247
12148
  1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
  • These GPIOs must not be used as current sources (for example to drive a LED).
  • The speed should not exceed 2 MHz with a maximum load of 30 pF
  1. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.
  2. As in SO8N device, the PA0, PA1, and PA2 GPIOs are bonded with NRST on the pin 4, low level applied to any of these GPIOs provokes the device reset. To prevent the risk of spurious resets, keep these GPIOs configured at all times as analog or digital inputs (as opposed to output or alternate function).
  3. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.
  4. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.

Table 13. Port A alternate function mapping

Table 13. Port A alternate function mapping

PortAF0AF1AF2AF3AF4AF5AF6AF7
PA0SPI2_SCKUSART2_CTS------
PA1SPI1_SCK/ I2S1_CKUSART2_RTS _DE_CK----I2C1_SMBAEVENTOUT
PA2SPI1_MOSI/ I2S1_SDUSART2_TX------
PA3SPI2_MISOUSART2_RX-----EVENTOUT
PA4SPI1_NSS/ I2S1_WSSPI2_MOSI--TIM14_CH1--EVENTOUT
PA5SPI1_SCK/ I2S1_CK------EVENTOUT
PA6SPI1_MISO/ I2S1_MCKTIM3_CH1TIM1_BKIN--TIM16_CH1--
PA7SPI1_MOSI/ I2S1_SDTIM3_CH2TIM1_CH1N-TIM14_CH1TIM17_CH1--
PA8MCOSPI2_NSSTIM1_CH1----EVENTOUT
PA9MCOUSART1_TXTIM1_CH2-SPI2_MISO-I2C1_SCLEVENTOUT
PA10SPI2_MOSIUSART1_RXTIM1_CH3--TIM17_BKINI2C1_SDAEVENTOUT
PA11SPI1_MISO/ I2S1_MCKUSART1_CTSTIM1_CH4--TIM1_BKIN2I2C2_SCL-
PA12SPI1_MOSI/ I2S1_SDUSART1_RTS _DE_CKTIM1_ETR--I2S_CKINI2C2_SDA-
PA13SWDIOIR_OUT-----EVENTOUT
PA14SWCLKUSART2_TX-----EVENTOUT
PA15SPI1_NSS/ I2S1_WSUSART2_RX-----EVENTOUT

Table 13. Port A alternate function mapping

Table 14. Port B alternate function mapping

PortAF0AF1AF2AF3AF4AF5AF6AF7
PB0SPI1_NSS/ I2S1_WSTIM3_CH3TIM1_CH2N-----
PB1TIM14_CH1TIM3_CH4TIM1_CH3N----EVENTOUT
PB2-SPI2_MISO-----EVENTOUT
PB3SPI1_SCK/ I2S1_CKTIM1_CH2--USART1_RTS _DE_CK--EVENTOUT
PB4SPI1_MISO/ I2S1_MCKTIM3_CH1--USART1_CTSTIM17_BKIN-EVENTOUT
PB5SPI1_MOSI/ I2S1_SDTIM3_CH2TIM16_BKIN---I2C1_SMBA-
PB6USART1_TXTIM1_CH3TIM16_CH1N-SPI2_MISO-I2C1_SCLEVENTOUT
PB7USART1_RXSPI2_MOSITIM17_CH1N---I2C1_SDAEVENTOUT
PB8-SPI2_SCKTIM16_CH1---I2C1_SCLEVENTOUT
PB9IR_OUT-TIM17_CH1--SPI2_NSSI2C1_SDAEVENTOUT
PB10-----SPI2_SCKI2C2_SCL-
PB11SPI2_MOSI-----I2C2_SDA-
PB12SPI2_NSS-TIM1_BKIN----EVENTOUT
PB13SPI2_SCK-TIM1_CH1N---I2C2_SCLEVENTOUT
PB14SPI2_MISO-TIM1_CH2N---I2C2_SDAEVENTOUT
PB15SPI2_MOSI-TIM1_CH3N----EVENTOUT

Table 14. Port B alternate function mapping

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 18 , Table 19 and Table 20 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.

All voltages are defined with respect to V SS .

Table 18. Voltage characteristics

SymbolRatingsMinMaxUnit
V DDExternal supply voltage-0.34.0V
V BATExternal supply voltage on VBAT pin-0.34.0V
V REF+External voltage on VREF+ pin-0.3Min(V DD + 0.4, 4.0)V
V IN (1)Input voltage on FT_xx-0.3V DD + 4.0 (2)(3)V
V IN (1)Input voltage on any other pin-0.34.0V
  1. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
  2. When an FT_a pin is used by an analog peripheral such as ADC, the maximum V IN is 4 V.

Table 19. Current characteristics

SymbolRatingsMaxUnit
I VDD/VDDACurrent into VDD/VDDA power pin (source) (1)100mA
I VSS/VSSACurrent out of VSS/VSSA ground pin (sink) (2)100mA
I IO(PIN)Output current sunk by any I/O and control pin except FT_f15mA
I IO(PIN)Output current sunk by any FT_f pin20mA
I IO(PIN)Output current sourced by any I/O and control pin15mA

Table 19. Current characteristics

Table 19. Current characteristics (continued)

SymbolRatingsMaxUnit
∑ I IO(PIN)Total output current sunk by sum of all I/Os and control pins80mA
∑ I IO(PIN)Total output current sourced by sum of all I/Os and control pins80mA
I INJ(PIN) (2)Injected current on a FT_xx pin-5 / NA (3)mA
∑ |I INJ(PIN) |Total injected current (sum of all I/Os and control pins) (4)25mA
  1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  2. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 20. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature150°C

Thermal Information

The operating junction temperature T J must never exceed the maximum given in Table 21: General operating conditions

The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:T _ { J } ( max ) = T _ { A } ( max ) + P _ { D } ( max ) × Θ _ { J A }$

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
STM32G030C6STMicroelectronics
STM32G030C8STMicroelectronics
STM32G030C8T6STMicroelectronics48-LQFP
STM32G030F6P6STMicroelectronics20-TSSOP (0.173", 4.40mm Width)
STM32G030J6STMicroelectronics
STM32G030K6STMicroelectronics
STM32G030K8STMicroelectronics
STM32G030X6/X8STMicroelectronics
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