CH32V307/317
32-bit RISC-V MicrocontrollerThe CH32V307/317 is a 32-bit risc-v microcontroller from WCH (WCH-IC). View the full CH32V307/317 datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
WCH (WCH-IC)
Category
32-bit RISC-V Microcontroller
Overview
Part: CH32V307VCT6 — WCH (WCH-IC)
Type: 32-bit RISC-V Microcontroller
Description: Industrial-grade general-purpose microcontroller based on QingKe RISC-V4F core, operating at up to 144 MHz with 480 KB CodeFlash, up to 128 KB SRAM, and extensive peripherals including USB2.0 high-speed, Gigabit Ethernet, and dual 12-bit ADCs/DACs.
Operating Conditions:
- Supply voltage: 3.3V
- Operating temperature: -40 to +85 °C
- CPU main frequency: Max 144MHz
Absolute Maximum Ratings:
Key Specs:
- Core: QingKe 32-bit RISC-V4F
- CPU main frequency: Max 144MHz
- Program memory (CodeFlash): Up to 480KB (zero-wait + non-zero-wait)
- Volatile data storage (SRAM): Up to 128KB
- ADC: 2 units, 12-bit, 16 external channels + 2 internal signals
- DAC: 2 units, 12-bit
- USB: USB2.0 full-speed host/device, USB2.0 high-speed host/device (built-in 480Mbps PHY)
- Ethernet: Gigabit Ethernet MAC controller, 10M PHY transceiver
Features:
- Single-precision floating-point unit (FPU)
- Fast programmable interrupt controller (PFIC)
- Multiple low-power modes: Sleep, Stop, Standby
- Built-in 8MHz RC oscillator and 40kHz RC oscillator
- 2 groups of 18-channel general-purpose DMA controllers
- 4 groups of 16-bit advanced timers for motor control
- 8 USART interfaces (including 5 UARTs)
- 2 I2C interfaces (support SMBus/PMBus)
- 3 SPI interfaces (SPI2, SPI3 for I2S2, I2S3)
- 2 CAN interfaces (2.0B active)
- SDIO host interface
- Digital video port (DVP)
- FSMC memory interface
- 80 GPIO ports, mapping 16 external interrupts
- CRC unit, 96-bit unique ID
- 2-wire serial debug interface (SDI)
Applications:
Package:
- LQFP100
Electrical Characteristics
Table 4-41 ADC characteristics
| Symbol | Parameter | Condition | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| V DDA | Supply voltage | 2.4 | 3.6 | V | ||
| V REF+ | Positive reference voltage | V REF+ cannot be more thanV DDA | 2.4 | V DDA | V | |
| I VREF | Reference current | 160 | 220 | μA | ||
| I DDA | Supply current | 480 | 530 | μA | ||
| f ADC | ADC clock frequency | 14 | MHz | |||
| f S | Sampling rate | 0.05 | 1 | MHz | ||
| f TRIG | External trigger frequency | 16 | 1/f ADC | |||
| V AIN | Conversion voltage range | 0 | V REF+ | V | ||
| R AIN | External input impedance | 50 | kΩ | |||
| R ADC | Sampling switch resistance | 0.6 | 1 | kΩ | ||
| C ADC | Internal sample and capacitor | 8 | pF |
Table 4-41 ADC characteristics
V3.4 78
| CAL | Calibration time | t | 1/f ADC | ||
|---|---|---|---|---|---|
| Iat | Injected trigger conversion latency | t | 2 | 1/f ADC | |
| Iatr | Regular trigger conversion latency | t | 2 | 1/f ADC | |
| t s | Sampling time | 1.5 | 239.5 | 1/f ADC | |
| STAB | Power-on time | t | 1 | us | |
| CONV | Total conversion time (including sampling time) | t | 14 | 252 | 1/f ADC |
Note: Above parameters are guaranteed by design.
Formula: Maximum RAIN
The above formula is used to determine the maximum external impedance so that the error can be less than 1/4 LSB. Where N=12 (representing 12-bit resolution).
Table 4-42 Maximum RAIN when fADC = 14MHz
- T S (cycle) t S (us) Maximum R AIN (kΩ)
- 1.5 0.11 0.4
- 7.5 0.54 5.9
- 13.5 0.96 11.4
- 28.5 2.04 25.2
- 41.5 2.96 37.2
- 55.5 3.96 50
- 71.5 5.11 Invalid
- 239.5 17.1 Invalid
Table 4-43 ADC error
| Symbol | Parameter | Condition | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|---|
| EO | Offset error | f PCLK2 = 56MHz, | ±4 | LSB | ||
| ED | Differential nonlinearity error | f ADC = 14MHz, | ±0.5 | ±3 | LSB | |
| EL | Integral nonlinearity error | R AIN < 10kΩ,V DDA = 3.3V | ±1 | ±4 | LSB |
Cp represents the parasitic capacitance on the PCB and the pad (about 5pF), which may be related to the quality of the pad and PCB layout. A larger Cp value will reduce the conversion accuracy, the solution is to reduce the f ADC value.
V3.4 79
Figure 4-29 ADC typical connection diagram
Figure 4-30 Analog power supply and decoupling circuit reference
Absolute Maximum Ratings
Stresses at or above the absolute maximum ratings listed in the table below may cause permanent damage to the device.
Table 4-1 Absolute maximum ratings
| Symbol | Description | Description | Min. | Max. | Unit |
|---|---|---|---|---|---|
| T A | Ambient temperature during operation | Ambient temperature during operation | -40 | 85 | °C |
| T S | Ambient temperature during storage | Ambient temperature during storage | -40 | 125 | °C |
| V DD -V SS | External main supply voltage (includingV DDA and V DD ) | External main supply voltage (includingV DDA and V DD ) | -0.3 | 4.0 | V |
| V I/O -V SS | I/O supply voltage | I/O supply voltage | -0.3 | 4.0 | V |
| V DD_ETH -V SS | Internal 10/100M Ethernet PHY supply voltage | CH32V317 | -0.3 | 4.0 | V |
| V DDK | Voltage at decoupling end of internal power supply LDO | CH32V317 | -0.2 | 1.5 | V |
| V IN | Input voltage on the FT (5V tolerance) pin | Input voltage on the FT (5V tolerance) pin | V SS -0.3 | 5.5 | V |
| V IN | 10/100M Ethernet PHY differential pin | V SS -0.3 | V DD_ETH +0.3 | V | V |
| V IN | Input voltage onPHY pin of USB and 10M Ethernet | Input voltage onPHY pin of USB and 10M Ethernet | V SS -0.3 | V DD +0.3 | V |
| V IN | Input voltage on other pins | Input voltage on other pins | V SS -0.3 | V IO +0.3 | V |
| \ | △ V DD_x \ | Variations between different main power supply pins | Variations between different main power supply pins | ||
| \ | △ V I/O_x \ | Variations between different I/O power supply pins | Variations between different I/O power supply pins | ||
| \ | △ V SS_x \ | Variations between different ground pins | Variations between different ground pins | ||
| V ESD(HBM) | Electrostatic discharge voltage (HBM, non-contact) | Electrostatic discharge voltage (HBM, non-contact) | 4K | 4K | V |
| V ESD(HBM) | USB pins (PA11, PA12) | USB pins (PA11, PA12) | 3K | 3K | V |
Table 4-1 Absolute maximum ratings
V3.4 51
| I VDD | Total current intoV DD /V DDA /V IO power lines (source) | 150 | mA |
|---|---|---|---|
| I Vss | Total current out ofV SS ground lines (sink) | 150 | mA |
| I I/O | Sink current on any I/O and control pin | 25 | mA |
| I I/O | Source current on any I/O and control pin | -25 | mA |
| I INJ(PIN) | Injected current on NRST pin | +/-5 | mA |
| I INJ(PIN) | Injected current on HSE's OSC_IN pin and LSE's OSC_IN pin | +/-5 | mA |
| I INJ(PIN) | Injected current on other pins | +/-5 | mA |
| ∑I INJ(PIN) | Total injected current on all I/Os and control pins | +/-25 | mA |
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| CH32V303 | WCH | — |
| CH32V305 | WCH | — |
| CH32V307 | WCH | TSSOP20 |
| CH32V307RCT6 | WCH (WCH-IC) | LQFP-64M(10x10) |
| CH32V307VCT6 | WCH (WCH-IC) | LQFP-100(14x14) |
| CH32V307WCU6 | WCH (WCH-IC) | QFN-68(8x8) |
| CH32V30X | WCH | — |
| CH32V317 | WCH | — |
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