TM4C123GH6PGEI7

Part: Tiva TM4C123GH6PM — Texas Instruments

Type: ARM Cortex-M4F Microcontroller

Description: 32-bit ARM Cortex-M4F MCU with FPU, operating from a 3.15–3.63 V supply, with integrated serial communications, motion control, analog peripherals and a Hibernation module.

Operating Conditions:

• Supply voltage (VDD): 3.15–3.63 V (3.3 V nominal)
• Analog supply voltage (VDDA): 2.97–3.63 V (3.3 V nominal)
• Core supply voltage (VDDC): 1.08–1.32 V (1.2 V nominal, with LDO in operation)
• GPIO input high-level voltage: 0.65 × VDD to 5.5 V

Absolute Maximum Ratings:

• Max VDD, VDDA and VBAT supply voltage: 4 V
• Max VBAT ramp rate: 0.7 V/μs
• GPIO input voltage: -0.3 to 5.5 V (PD4, PD5, PB0 and PB1 as GPIO: -0.3 to VDD + 0.3 V)
• Max current per output pin: 25 mA
• Max junction temperature: 150 °C
• Storage temperature (unpowered): -65 to 150 °C
• ESD: 2.0 kV HBM, 500 V CDM

Key Specs:

• VDD supply: 3.15 / 3.3 / 3.63 V (min/nom/max)
• VDDA supply: 2.97 / 3.3 / 3.63 V (min/nom/max)
• VDDC supply: 1.08 / 1.2 / 1.32 V (min/nom/max); same range in Deep-sleep mode
• GPIO VIH min 0.65 × VDD, VIL max 0.35 × VDD, hysteresis min 0.2 V
• GPIO VOH min 2.4 V; VOL max 0.4 V
• GPIO drive: 2, 4 or 8 mA at VOH = 2.4 V / VOL = 0.4 V; 8-mA drive sinks 18 mA at VOL = 1.2 V
• Cumulative GPIO current per package side: 30 mA (left), 35 mA (bottom), 40 mA (right), 40 mA (top); based on design simulation, not production tested

Features:

• ARM Cortex-M4F processor core with floating-point unit (FPU) and memory protection unit (MPU)
• On-chip SRAM, ROM, Flash and EEPROM
• Serial communications peripherals
• Hibernation module with real-time clock and battery-backed memory
• Micro DMA (μDMA) controller
• Advanced motion control and analog peripherals
• JTAG and ARM Serial Wire Debug

Applications:

Package:

The TM4C123GH6PM microcontroller component features and general function are discussed in more detail in the following section.

When using the Device controller portion of the USB controller in a system that also provides Host functionality, the power to VBUS must be disabled to allow the external Host controller to supply power. Usually, the USB0EPEN signal is used to control the external regulator and should be negated to avoid having two devices driving the USB0VBUS power pin on the USB connector.

When the USB controller is acting as a Host, it is in control of two signals that are attached to an external voltage supply that provides power to VBUS. The Host controller uses the USB0EPEN signal to enable or disable power to the USB0VBUS pin on the USB connector. An input pin, USB0PFLT , provides feedback when there has been a power fault on VBUS. The USB0PFLT signal can be configured to either automatically negate the USB0EPEN signal to disable power, and/or it can generate an interrupt to the interrupt controller to allow software to handle the power fault condition. The polarity and actions related to both USB0EPEN and USB0PFLT are fully configurable in the USB controller. The controller also provides interrupts on Device insertion and removal to allow the Host controller code to respond to these external events.

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Device reliability may be adversely affected by exposure to absolute-maximum ratings for extended periods.

Note: The device is not guaranteed to operate properly at the maximum ratings.

Table 24-1. Absolute Maximum Ratings

Important: This device contains circuitry to protect the I/Os against damage due to high-static voltages; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (see 'Connections for Unused Signals' on page 1356).

Table 24-2. ESD Absolute Maximum Ratings

For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the V OL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package with the total number of high-current GPIO outputs not exceeding four for the entire package.

Table 24-5. Recommended DC Operating Conditions

a. These values are valid when LDO is in operation.

b. There are peripheral timing restrictions for SSI and LPC in Deep-sleep mode. Please refer to those peripheral characteristic sections for more information.

Table 24-6. Recommended GPIO Pad Operating Conditions

a. I O specifications reflect the maximum current where the corresponding output voltage meets the V OH /V OL thresholds. I O current can exceed these limits (subject to absolute maximum ratings).

Table 24-7. GPIO Current Restrictions a

a. Based on design simulations, not tested in production.

b. Sum of sink and source current for GPIOs as shown in Table 24-8 on page 1361.

Table 24-8. GPIO Package Side Assignments

a. For more details about thermal metrics and definitions, see the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953).

b. Junction to ambient thermal resistance (Θ JA ), junction to board thermal resistance (Θ JB ), and junction to case thermal resistance (Θ JC ) numbers are determined by a package simulator.

• c. T PCB is the temperature of the board acquired by following the steps listed in the EAI/JESD 51-8 standard summarized in the Semiconductor and IC Package Thermal Metrics Application Report (literature number SPRA953).
• d. Because Θ JA is highly variable and based on factors such as board design, chip/pad size, altitude, and external ambient temperature, it is recommended that equations containing Ψ JT and Ψ JB be used for best results.

e. T B is temperature of the board.

f. Θ JB is not a pure reflection of the internal resistance of the package because it includes the resistance of the testing board and environment. It is recommended that equations containing Ψ JT and Ψ JB be used for best results.

MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996

NOTES: A. All linear dimensions are in millimeters.

• B. This drawing is subject to change without notice.
• C. Falls within JEDEC MS-026
• D. May also be thermally enhanced plastic with leads connected to the die pads.