STM8S103F3P6

Part: STM8S103F3P6 (STM8S103F2/F3/K3 family) — STMicroelectronics

Type: 8-bit Microcontroller (STM8 core)

Description: 16 MHz STM8S 8-bit MCU with up to 8 Kbyte Flash, 640 byte data EEPROM, 1 Kbyte RAM, 10-bit ADC, 3 timers, UART, SPI and I²C, operating from 2.95 to 5.5 V.

Operating Conditions:

• Supply voltage: 2.95–5.5 V
• Max CPU clock: 16 MHz

Absolute Maximum Ratings:

• Max supply voltage (VDDx − VSS): 6.5 V
• Input voltage on true open drain pins: VSS − 0.3 to 6.5 V
• Input voltage on any other pin: VSS − 0.3 to VDD + 0.3 V
• Total current into VDD power lines (source): 100 mA
• Total current out of VSS ground lines (sink): 80 mA
• Output current sunk/sourced by any I/O or control pin: 20 mA / −20 mA
• Injected current per pin: ±4 mA; total injected current: ±20 mA
• Storage temperature: −65 to 150 °C
• Max junction temperature: 150 °C

Key Specs:

• Core: 16 MHz advanced STM8, Harvard architecture, 3-stage pipeline
• Memory: 8 Kbyte Flash (20 years retention at 55 °C after 10 kcycle), 640 byte data EEPROM (300 kcycle endurance), 1 Kbyte RAM
• ADC: 10-bit, ±1 LSB, up to 5 multiplexed channels
• I/Os: up to 28 on the 32-pin package, including 21 high-sink outputs
• SPI: up to 8 Mbit/s
• I²C: up to 400 kbit/s
• Timers: 16-bit advanced control timer (4 CAPCOM channels, 3 complementary outputs), 16-bit general purpose timer (3 CAPCOM channels), 8-bit basic timer
• Interrupts: 32 interrupts, up to 27 external interrupts on 6 vectors

Features:

• 4 master clock sources: crystal oscillator, external clock input, internal 16 MHz RC, internal 128 kHz RC
• Clock security system with clock monitor
• Low-power modes: wait, active-halt, halt
• Individual peripheral clock gating
• Permanently active low-consumption power-on and power-down reset
• Auto wake-up timer, window watchdog and independent watchdog
• UART with synchronous clock output, SmartCard, IrDA and LIN master mode
• 96-bit unique ID
• Highly robust I/O design, immune against current injection

Applications:

• General-purpose embedded control

Package:

• TSSOP20
• SO20
• UFQFPN20 (3x3 mm)
• LQFP32 (7x7 mm)
• UFQFPN32 (5x5 mm)
• SDIP32

• Clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
• Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.
• Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
• Master clock sources: four different clock sources can be used to drive the master clock:
• -1-16 MHz high-speed external crystal (HSE)
• -Up to 16 MHz high-speed user-external clock (HSE user-ext)
• -16 MHz high-speed internal RC oscillator (HSI)
• -128 kHz low-speed internal RC (LSI)
• Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
• Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.
• Configurable main clock output (CCO): This outputs an external clock for use by the application.

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

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Table 4. Legend/abbreviations for pin description tables

Table 4. Legend/abbreviations for pin description tables

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Subject to general operating conditions for V DD , f MASTER , and T A unless otherwise specified.

Table 45. ADC characteristics

Table 45. ADC characteristics

Table 46. ADC accuracy with R AIN < 10 k Ω , V DD = 5 V

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Table 47. ADC accuracy with R AIN < 10 k Ω , V DD = 3.3 V

1. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I INJ(PIN) and Σ I INJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.
2. Example of an actual transfer curve
3. The ideal transfer curve
4. End point correlation line
5. EO = Offset error: deviation between the first actual transition and the first ideal one.
6. ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
7. EG = Gain error: deviation between the last ideal transition and the last actual one.
8. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line.
9. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.

Figure 43. ADC accuracy characteristics

Figure 44. Typical application with ADC

1. Legend: R AIN = external resistance, C AIN = capacitors, C samp = internal sample and hold capacitor.

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Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics , Table 17: Current characteristics and Table 18: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and a functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device's reliability.

The device's mission profile (application conditions) is compliant with the JEDEC JESD47 Qualification Standard, the extended mission profiles are available on demand.

Table 16. Voltage characteristics

Table 17. Current characteristics

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Table 17. Current characteristics (continued)

1. Guaranteed by characterization results.
2. All power (V DD ) and ground (V SS ) pins must always be connected to the external supply.
3. I INJ must never be exceeded. This condition is implicitly insured if V IN maximum is respected. If V IN maximum cannot be respected, the injection current must be limited externally to the I INJ(PIN) value. A positive injection is induced by V IN > V DD while a negative injection is induced by V IN < V SS . For true opendrain pads, there is no positive injection current allowed and the corresponding V IN maximum must always be respected.
4. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and Σ I INJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
5. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with Σ I INJ(PIN) maximum current injection on four I/O port pins of the device.

Table 18. Thermal characteristics

The maximum junction temperature (T Jmax ) of the device must never exceed the values specified in Table 19: General operating conditions , otherwise the functionality of the device cannot be guaranteed.

The maximum junction temperature T Jmax , in degrees Celsius, may be calculated using the following equation:

$$T_{Jmax} = T_{Amax} + (P_{Dmax} \times \Theta_{JA})$$

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.