STM8L151M8

Part: STM8L151x6/8, STM8L152x6/8 — STMicroelectronics

Type: 8-bit Ultra-Low-Power MCU

Description: 8-bit STM8 ultra-low-power MCU at up to 16 MHz with up to 64 KB Flash, 2 KB data EEPROM and 4 KB RAM, 1.65–3.6 V supply, RTC, LCD (STM8L152 only), 12-bit ADC and DAC.

Operating Conditions:

• Supply voltage: 1.65–3.6 V (BOR disabled); 1.8–3.6 V (BOR enabled)
• Operating temperature: -40 to 85 °C (suffix 6; suffix 7 to 105 °C and suffix 3 to 125 °C)
• Max system clock: 16 MHz (1.65 V ≤ VDD < 3.6 V)
• VDDA: 1.8–3.6 V when ADC or DAC is used

Absolute Maximum Ratings:

• Max supply voltage (VDD − VSS): 4.0 V
• Total current into VDD: 80 mA; total current out of VSS: 80 mA
• Output current sunk by any other I/O: 25 mA; sourced: -25 mA
• Max junction temperature: 150 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Run consumption: 200 μA/MHz + 330 μA
• Low-power run: 5.9 μA; low-power wait: 3 μA
• Active-halt with full RTC: 1.4 μA; Halt: 400 nA
• Wake-up from Halt: 4.7 μs
• I/O leakage: 50 nA per I/O
• 12-bit ADC up to 1 Msps, 28 channels; 2× 12-bit DAC
• Junction temperature range (suffix 6): -40 to 105 °C
• Power dissipation at TA = 85 °C (suffix 6): 526 mW (LQFP80), 416 mW (LQFP64), 625 mW (UFQFPN48), 307 mW (LQFP48), 317 mW (WLCSP32)

Features:

• Advanced STM8 core, Harvard architecture, 3-stage pipeline, 16 CISC MIPS peak
• Up to 64 KB Flash, up to 2 KB data EEPROM with ECC and RWW, up to 4 KB RAM
• 5 low-power modes
• BOR with five programmable thresholds, POR/PDR, PVD
• 32 kHz and 1–16 MHz crystal oscillators, internal 16 MHz and 38 kHz RC
• Low-power RTC with calendar, alarm and anti-tamper detection
• LCD 8x40 or 4x44 with step-up converter (STM8L152)
• 2 ultra-low-power comparators
• Timers: three 16-bit general purpose, one 16-bit advanced control, one 8-bit, window and independent watchdogs, beeper
• 2 SPI, fast I2C 400 kHz (SMBus/PMBus), 3 USARTs (ISO 7816, IrDA)
• Up to 67 I/Os, up to 16 capacitive sensing channels
• DMA with 4 channels plus 1 memory-to-memory channel
• SWIM debug, USART bootloader, 96-bit unique ID

Applications:

• Ultra-low-power battery-powered devices
• LCD display and touch-sensing applications

Package:

• LQFP80 (14x14 mm)
• LQFP64 (10x10 mm)
• LQFP48 (7x7 mm)
• UFQFPN48 (7x7 mm)
• WLCSP32

• Operating conditions
• -Operating power supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
• -Temp. range: -40 to 85, 105 or 125 °C
• Low-power features
• -5 low-power modes: Wait, Low-power run (5.9 μA), Low-power wait (3 μA), Activehalt with full RTC (1.4 μA), Halt (400 nA)
• -Consumption: 200 μA/MHz+330 μA
• -Fast wake up from Halt mode (4.7 μs)
• -Ultra low leakage per I/0: 50 nA
• Advanced STM8 core
• -Harvard architecture and 3-stage pipeline
• -Max freq: 16 MHz, 16 CISC MIPS peak
• -Up to 40 external interrupt sources
• Reset and supply management
• -Low-power, ultra safe BOR reset with five programmable thresholds
• -Ultra-low-power POR/PDR
• -Programmable voltage detector (PVD)
• Clock management
• -32 kHz and 1-16 MHz crystal oscillators
• -Internal 16 MHz factory-trimmed RC and 38 kHz low consumption RC
• -Clock security system
• Low-power RTC
• -BCD calendar with alarm interrupt
• -Digital calibration with +/- 0.5ppm accuracy
• -Advanced anti-tamper detection
• LCD: 8x40 or 4x44 w/ step-up converter
• DMA
• -4 ch. for ADC, DACs, SPIs, I 2 C, USARTs, Timers, 1 ch. for memory-to-memory
• 2x12-bit DAC (dual mode) with output buffer
• 12-bit ADC up to 1 Msps/28 channels
• -Temp. sensor and internal ref. voltage

Table 1. Device summary

Table 1. Device summary

Figure 3. STM8L151M8 80-pin package pinout (without LCD)

1. Pin 22 is reserved and must be tied to V DD .
2. The above figure shows the package top view.
3. The above figure shows the package top view.

Figure 4. STM8L152M8 80-pin package pinout (with LCD)

Figure 5. STM8L151R8 and STM8L151R6 64-pin pinout (without LCD)

1. Pin 18 is reserved and must be tied to V DD .
2. The above figure shows the package top view.
3. The above figure shows the package top view.

Figure 6. STM8L152R8 and STM8L152R6 64-pin pinout (with LCD)

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Figure 7. STM8L151C8 48-pin pinout (without LCD)

1. Pin 13 is reserved and must be tied to V DD .
2. The above figure shows the package top view.
3. The above figure shows the package top view.

Figure 8. STM8L152C8 48-pin pinout (with LCD)

Figure 9. STM8L152K8 32-ball ballout

Warning:

For the 32-pin STM8L152K8 devices, some active I/O pins are not bonded out of the package. Effectively, all ports available on 48-pin devices must be considered as active ports also for 32-pin devices - see Table 5: High-density and medium+ density STM8L15x pin description for more details. To avoid spurious effects, users have to configure active ports as input pull-up. A small increase in consumption (typ. < 300 μ A) may occur during the power up and reset phase until these ports are properly configured.

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Table 4. Legend/abbreviation

Table 5. High-density and medium+ density STM8L15x pin description

Table 5. High-density and medium+ density STM8L15x pin description

Table 5. High-density and medium+ density STM8L15x pin description (continued)

Table 5. High-density and medium+ density STM8L15x pin description (continued)

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In the following table, data are guaranteed by design.

Table 50. DAC characteristics

1. Resistive load between DACOUT and GNDA
2. Output on PF0 or PF1
3. Capacitive load at DACOUT pin
4. It gives the output excursion of the DAC

In the following table, data based on characterization results.

Table 51. DAC accuracy

1. Difference between two consecutive codes - 1 LSB.
2. In 48-pin package devices the DAC2 output buffer must be kept off and no load must be applied on the DAC_OUT2 output.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.
4. Difference between the value measured at Code (0x800) and the ideal value = V REF+ /2.
5. Difference between the value measured at Code (0x001) and the ideal value.
6. Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and 0xFFF when buffer is ON, and from Code giving 0.2 V and (V DDA -0.2) V when buffer is OFF.

In the following table, data are guaranteed by design.

Table 52. DAC output on PB4-PB5-PB6 (1)

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Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics , Table 16: Current characteristics , and Table 17: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect the device's reliability.

The device's mission profile (application conditions) is compliant with the JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 15. Voltage characteristics

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Table 16. Current characteristics

Table 17. Thermal characteristics

Table 17. Thermal characteristics

The maximum chip junction temperature (T Jmax ) must never exceed the values given in Table 18: General operating conditions on page 71 .

The maximum chip-junction temperature, T Jmax , in degree Celsius, may be calculated using the following equation:

$$T_{Jmax} = T_{Amax} + (P_{Dmax} \times \Theta_{JA})$$

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.