STM32U535NE

Part: STM32U535xx (STM32U535RET6 — package/variant per ordering code) — STMicroelectronics

Type: Ultra-low-power Arm Cortex-M33 MCU with TrustZone and FPU

Description: Ultra-low-power 32-bit Arm Cortex-M33 MCU with TrustZone and FPU at up to 160 MHz (240 DMIPS), with up to 512 KB flash and 274 KB SRAM, running from a 1.71–3.6 V supply.

Operating Conditions:

• Supply voltage (VDD): 1.71–3.6 V (1.71–2.7 V when HSLV = 1)
• Operating temperature: -40 to +85 °C (suffix 6, maximum power dissipation; up to 105 °C in low-power dissipation state). Suffix 3 extends to 125 °C
• Max AHB clock: 160 MHz (Range 1), 110 MHz (Range 2), 55 MHz (Range 3), 25 MHz (Range 4)
• Junction temperature (suffix 6): -40 to 105 °C

Absolute Maximum Ratings:

• Max external main supply voltage (VDDX - VSS): 4.0 V (-0.3 V min)
• Max VDDIOx - VSS: 4.0 V (HSLV = 0), 2.75 V (HSLV = 1)
• Max input voltage on FT_c pins: 5.5 V
• Max input voltage on other pins: 4.0 V
• Max current into each VDD pin: 100 mA; total into all VDD lines: 200 mA
• Max current sunk by any I/O: 20 mA
• Max junction temperature: 140 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• VCORE (internal regulator on): 1.21 V typ Range 1, 1.1 V Range 2, 1.0 V Range 3, 0.9 V Range 4
• VDDA: 1.62–3.6 V with ADC in use; 1.8–3.6 V with VREFBUF in use
• VDDIO2: 1.08–3.6 V when PG[15:2] I/Os are used
• VDDUSB: 3.0–3.6 V when USB is used
• VBAT: 1.65–3.6 V
• Run mode: 16.3 μA/MHz at 3.3 V
• Stop 2: 3.0 μA with 16 KB SRAM; Stop 3: 1.4 μA with 16 KB SRAM
• Standby: 200 nA (370 nA with RTC); Shutdown: 90 nA
• CoreMark: 651 (4.07 CoreMark/MHz)

Features:

• Arm Cortex-M33 with TrustZone, MPU, DSP and FPU
• 8 KB instruction cache and 4 KB data cache (ART Accelerator)
• Up to 512 KB flash with ECC (2 banks); 274 KB SRAM
• Octo-SPI memory interface
• Security: secure boot and firmware install, HASH, TRNG, 512-byte OTP, active tampers
• LDO and SMPS step-down converter
• Up to 82 I/Os
• Up to 17 timers and 2 watchdogs
• Up to 19 communication peripherals: USB FS, FDCAN, 4 I2C, 5 USART, 3 SPI, SAI, SDMMC
• 14-bit and 12-bit ADCs at 2.5 Msps, 2 DACs, 1 op-amp, 1 comparator
• CORDIC, FMAC, touch sensing (up to 20 channels)
• LPBAM autonomous low-power mode
• SWD, JTAG and ETM debug

Applications:

Package:

• LQFP48 (7 x 7 mm), LQFP64 (10 x 10 mm), LQFP100 (14 x 14 mm)
• UFQFPN48 (7 x 7 mm)
• WLCSP56 and WLCSP72 (3.38 x 3.38 mm)
• UFBGA64 (5 x 5 mm), UFBGA100 (7 x 7 mm)

• Single bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
• -Peripheral-to-memory
• -Memory-to-peripheral
• -Memory-to-memory
• -Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Transfers arbitration based on a 4-grade programmed priority at channel level:
• -One high-priority traffic class, for time-sensitive channels (queue 3)
• -Three low-priority traffic classes, with a weighted round-robin allocation for non time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete, or half-transfer complete, or data transfer error, or user setting error, and/or update linked-list item error, or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable per event

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• Four concurrent DMA channels:
• -Intra-channel DMA transfers chaining via programmable linked-list into memory, supporting two execution modes: run-to-completion and link step mode
• -Intra-channel and inter-channel DMA transfers chaining via programmable DMA input triggers connection to DMA task completion events
• Per linked-list item within a channel:
• -Separately programmed source and destination transfers
• -Programmable data handling between source and destination: byte-based padding or truncation, sign extension and left/right realignment
• -Programmable number of data bytes to be transferred from the source, defining the block level
• -Linear source and destination addressing: either fixed or contiguously incremented addressing, programmed at a block level, between successive single transfers
• -Programmable DMA request and trigger selection
• -Programmable DMA half-transfer and transfer complete events generation
• -Pointer to the next linked-list item and its data structure in memory, with automatic update of the DMA linked-list control registers
• Debug:
• -Channel suspend and resume support
• -Channel status reporting and event flags
• TrustZone support
• -Support for secure and nonsecure DMA transfers, independently at a first channel level, and independently at a source/destination and link sub-levels
• -Secure and nonsecure interrupts reporting, resulting from any of the respectively secure and nonsecure channels
• -TrustZone-aware AHB slave port, protecting any DMA secure resource (register, register field) from a nonsecure access
• Privileged/unprivileged support:
• -Support for privileged and unprivileged DMA transfers, independently at channel level
• -Privileged-aware AHB slave port

Table 13. LPDMA1 channels implementation and usage

Table 13. LPDMA1 channels implementation and usage

Table 25. Legend/abbreviations used in the pinout table

Table 25. Legend/abbreviations used in the pinout table

Pinout, pin description, and alternate functions

Pinout, pin description, and alternate functions

DS14217 Rev 2

• 108/300 Pin number Pin number Pin number structure Notes Alternate functions Additional functions
• 108/300 LQFP48 SMPS UFQFPN48 SMPS WLCSP56 SMPS LQFP64 SMPS UFBGA64 SMPS WLCSP72 SMPS LQFP100 SMPS UFBGA100 SMPS LQFP48 UFQFPN48 LQFP64 UFBGA64 LQFP100 UFBGA100 Pin name (function after reset) Pin type structure Notes Alternate functions Additional functions
• 33 C3 45 C7 C4 71 D11 33 45 B8 71 A12 PA12 I/O FT_u - TIM1_ETR, SPI1_MOSI, OCTOSPI1_NCS, USART1_RTS_DE, FDCAN1_TX, USB_DP(boot), EVENTOUT -
• 34 C5 46 C6 D5 72 C12 34 46 A8 72 A11 PA13 (JTMS/ SWDIO) I/O FT (4) JTMS/SWDIO, IR_OUT, USB_NOE, SAI1_SD_B, EVENTOUT -
• • B2 47 G7 B3 - - - 47 D5 - - VSS S - - - -
• • A1 48 B8 B1 73 E10 - 48 E5 73 C11 VDDUSB S - - - -
• 35 - - - - 74 C8 35 - - 74 F12 VSS S - - - -
• 36 - - H8 A2 75 C10 36 - - 75 G2 VDD S - - - -
• 37 A5 49 C5 E8 76 C11 37 49 A7 76 A10 PA14 (JTCK/ SWCLK) I/O FT (4) JTCK/SWCLK, LPTIM1_CH1, I2C1_SMBA, I2C4_SMBA, USB_SOF, SAI1_FS_B, EVENTOUT -
• 38 A3 50 C4 D7 77 B12 38 50 A6 77 A9 PA15 (JTDI) I/O FT (4) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS, SPI3_NSS, USART3_RTS_DE, UART4_RTS_DE, EVENTOUT -
• • • 51 A7 - 78 A12 - 51 B7 78 B11 PC10 I/O FT_ha - TRACED1, LPTIM3_ETR, ADF1_CCK1, SPI3_SCK, USART3_TX(boot), UART4_TX, TSC_G3_IO2, DCMI_D8/PSSI_D8, LPGPIO1_P8, SDMMC1_D2, EVENTOUT -

DS14217 Rev 2

1. Function availability depends on the chosen device.
2. PC13, PC14, and PC15 are supplied through the power switch (by V SW ). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs in output mode is limited:

• The speed must not exceed 2 MHz with a maximum load of 30 pF.
• These GPIOs must not be used as current sources (for example to drive a LED).

1. After a backup domain power-up, PC13, PC14, and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
2. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.
3. Power supply is VDDIO2.

The definition and values of output AC characteristics are given in Figure 35: Output AC characteristics definition and in the table below respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 32 .

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode, and FT_o I/Os (1) ) (2)(3)(4)

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode, and FT_o I/Os (1) ) (2)(3)(4)

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode, and FT_o I/Os (1) ) (2)(3)(4) (continued)

Table 96. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode, and FT_o I/Os (1) ) (2)(3)(4) (continued)

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Stresses above the absolute maximum ratings listed in Table 29 , Table 30 and Table 31 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

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Table 29. Voltage characteristics (1)(2)

1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. VDDIO1 or V DDIO2 , V DDIO1 = V DD .
3. VIN maximum must always be respected. Refer to Table 30 for the maximum allowed injected current values.
4. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
5. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
6. Including VREF- pin.

Table 30. Current characteristics

Table 30. Current characteristics

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
2. Positive injection (when V IN > V DDIOx ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
3. A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 29 for the minimum allowed input voltage values.
4. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) is the absolute sum of the negative injected currents (instantaneous values).

Table 31. Thermal characteristics

Table 31. Thermal characteristics

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The maximum chip-junction temperature, T J max, in degrees Celsius, can be calculated using the following equation:

T J max = T A max + (P D max × Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.