STM32G474RBT3

Part: STM32G474xB/xC/xE — STMicroelectronics

Type: Arm Cortex-M4 32-bit MCU with FPU

Description: 170 MHz (213 DMIPS) Arm Cortex-M4 MCU with FPU, up to 512 KB Flash and 128 KB SRAM, 1.71–3.6 V supply, rich analog (5 ADCs, 7 DACs, 7 comparators, 6 op-amps) and a 184 ps resolution high-resolution timer.

Operating Conditions:

• Supply voltage (VDD): 1.71–3.6 V
• Operating temperature: -40 to 85 °C (suffix 6; suffix 3 version is -40 to 125 °C)
• Max CPU/AHB/APB clock: 170 MHz
• Analog supply (VDDA): 1.62–3.6 V with ADC in use; 1.8–3.6 V with DAC/OPAMP/COMP; 2.4–3.6 V with VREFBUF
• VBAT: 1.55–3.6 V

Absolute Maximum Ratings:

• Max supply voltage (VDD – VSS): 4.0 V (min -0.3 V)
• Max input voltage on FT_c pins: 5.5 V
• Max current into sum of all VDD lines: 150 mA
• Max current into each VDD pin: 100 mA
• Max output current sunk or sourced by any I/O pin: 20 mA
• Max junction temperature: 150 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Core clock: up to 170 MHz (0-wait-state Flash execution via ART Accelerator)
• VDD range: 1.71–3.6 V
• Junction temperature range: -40 to 105 °C (suffix 6), -40 to 130 °C (suffix 3)
• Maximum I/O input voltage (all I/O except TT_xx and FT_c): MIN(MIN(VDD, VDDA)+3.6 V, 5.5 V)
• Total output current sunk or sourced by all I/Os: 100 mA each
• Injected current on FT_xxx, TT_xx, NRST pins: -5/0 mA; total ±25 mA
• Memory: 512 KB Flash with ECC; 96 KB SRAM plus 32 KB CCM SRAM
• Up to 107 fast I/Os

Features:

• Arm Cortex-M4 with FPU, MPU, DSP instructions and ART Accelerator
• CORDIC and FMAC math accelerators
• 5 × 12-bit ADCs (0.25 μs, up to 42 channels, up to 16-bit with oversampling)
• 7 × 12-bit DAC channels, 7 × rail-to-rail comparators, 6 × op-amps with PGA mode
• Internal voltage reference buffer (2.048 V, 2.5 V, 2.95 V)
• HRTIM with 184 ps resolution and 12 PWM channels, 17 timers in total
• 3 × FDCAN, 4 × I2C Fast mode plus, 5 × USART/UART, 1 × LPUART, 4 × SPI, SAI, USB 2.0 full-speed, UCPD
• FSMC and Quad-SPI memory interfaces
• Low-power modes: sleep, stop, standby, shutdown; VBAT supply for RTC and backup registers
• 16-channel DMA, RNG, CRC unit, 96-bit unique ID
• SWD, JTAG and Embedded Trace Macrocell debug

Applications:

• Motor control and digital power conversion

Package:

• UFQFPN48
• LQFP48
• LQFP64
• LQFP80
• LQFP100
• LQFP128
• WLCSP81
• TFBGA100
• UFBGA121

• Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions
• Operating conditions:
• -VDD , V DDA voltage range: 1.71 V to 3.6 V
• Mathematical hardware accelerators
• -CORDIC for trigonometric functions acceleration
• -FMAC: filter mathematical accelerator
• Memories
• -512 Kbytes of Flash memory with ECC support, two banks read-while-write, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP
• -96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes
• -Routine booster: 32 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)
• -External memory interface for static memories FSMC supporting SRAM, PSRAM, NOR and NAND memories
• -Quad-SPI memory interface
• Reset and supply management
• -Power-on/power-down reset (POR/PDR/BOR)
• -Programmable voltage detector (PVD)
• -Low-power modes: sleep, stop, standby and shutdown
• -VBAT supply for RTC and backup registers
• Clock management
• -4 to 48 MHz crystal oscillator
• -32 kHz oscillator with calibration
• -Internal 16 MHz RC with PLL option (± 1%)

DS12288 Rev 5

• channels, dead time generation and emergency stop
• -1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop
• -2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop
• -2 x watchdog timers (independent, window)
• -1 x SysTick timer: 24-bit downcounter
• -2 x 16-bit basic timers
• -1 x low-power timer
• Calendar RTC with alarm, periodic wakeup from stop/standby
• Communication interfaces
• -3 x FDCAN controller supporting flexible data rate
• -4 x I 2 C Fast mode plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, wakeup from stop
• -5 x USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)
• -1 x LPUART
• -4 x SPIs, 4 to 16 programmable bit frames, 2 x with multiplexed half duplex I 2 S interface
• -1 x SAI (serial audio interface)
• -USB 2.0 full-speed interface with LPM and BCD support
• -IRTIM (infrared interface)
• -USB Type-C™ /USB power delivery controller (UCPD)
• True random number generator (RNG)
• CRC calculation unit, 96-bit unique ID
• Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell™

Table 1. Device summary

Table 1. Device summary

The definition and values of input/output AC characteristics are given in Figure 26 and Table 56 , respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 17: General operating conditions .

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Table 56. I/O (except FT_c) AC characteristics (1) (2)

Table 56. I/O (except FT_c) AC characteristics (1) (2)

Table 56. I/O (except FT_c) AC characteristics (1) (2) (continued)

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm ® based 32-bit MCUs" for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. This value represented the I/O capability but maximum system frequency is 170 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
5. The maximum frequency is defined with the following conditions:

• 45%<Duty cycle<55%

• (Tr+ Tf)

≤

2/3 T.

Table 57. I/O FT_c AC characteristics (1) (2)

1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register. Refer to the reference manual RM0440 "STM32G4 Series advanced Arm ® based 32-bit MCUs" for a description of GPIO Port configuration register.
2. Guaranteed by design.

200

Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics , Table 15: Current characteristics and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 14. Voltage characteristics (1)

Table 14. Voltage characteristics (1)

1. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum allowed injected current values.
2. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
3. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
4. Include VREF- pin.
5. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
6. Positive injection (when V IN > V DD ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
7. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14: Voltage characteristics for the minimum allowed input voltage values.
8. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).

Table 15. Current characteristics

Table 16. Thermal characteristics

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The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.