Part: STM32F411xC/xE — STMicroelectronics

Type: ARM Cortex-M4 MCU

Description: 32-bit ARM Cortex-M4 MCU with FPU, up to 100 MHz, 512 KB Flash, 128 KB SRAM, USB OTG FS, 1 ADC, and 13 communication interfaces.

Operating Conditions:

• Supply voltage: 1.7–3.6 V
• Operating temperature: -40 to +85 °C (suffix-dependent — see Table 14 for grade-specific ranges)
• Max HCLK frequency: 100 MHz (Power Scale1)
• Analog operating voltage (ADC limited to 2.4 MSPS): 2.4–3.6 V

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max continuous current: 160 mA (Total current into sum of all VDD_x power lines)
• Max junction/storage temperature: 125 °C (Junction), 150 °C (Storage)

Key Specs:

• Core: ARM 32-bit Cortex-M4 CPU with FPU
• Max CPU frequency: 100 MHz
• Flash memory: up to 512 Kbytes
• SRAM: 128 Kbytes
• ADC: 1x 12-bit, 2.4 MSPS, up to 16 channels
• I/O ports: Up to 81 with interrupt capability, up to 77 5 V-tolerant
• Run mode current: 100 μA/MHz (peripheral off)
• Stop mode current: 42 μA Typ @ 25°C (Flash in Stop mode)
• Standby mode current: 2.4 μA @25 °C / 1.7 V without RTC

Features:

• Adaptive real-time accelerator (ART Accelerator™)
• Batch Acquisition Mode (BAM)
• Memory protection unit
• Up to 13 communication interfaces (I2C, USART, SPI/I2S, SDIO, USB OTG FS)
• General-purpose DMA: 16-stream controllers
• Up to 11 timers (16-bit, 32-bit, watchdog, SysTick)
• CRC calculation unit
• 96-bit unique ID
• RTC with subsecond accuracy and hardware calendar

Applications:

Package:

• WLCSP49 (3.034 x 3.22 mm, 0.4mm pitch)
• UFQFPN48 (7 x 7 mm, 0.5 mm pitch)
• LQFP64 (10 x 10 mm, 64-pin)
• LQFP100 (14 x 14 mm, 100-pin)
• UFBGA100 (7 x 7 mm, 0.5 mm pitch)

• Dynamic Efficiency Line with BAM (Batch Acquisition Mode)
• Core: ARM ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit,
• 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -up to 512 Kbytes of Flash memory
• -128 Kbytes of SRAM
• Clock, reset and supply management
• -1.7 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Power consumption
• -Run: 100 μA/MHz (peripheral off)
• -Stop (Flash in Stop mode, fast wakeup time): 42 μA Typ @ 25C; 65 μA max @25 °C
• -Stop (Flash in Deep power down mode, fast wakeup time): down to 10 μA @ 25 °C; 30 μA max @25 °C
• -Standby: 2.4 μA @25 °C / 1.7 V without RTC; 12 μA @85 °C @1.7 V
• -VBAT supply for RTC: 1 μA @25 °C
• 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
• General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
• Up to 11 timers: up to six 16-bit, two 32-bit timers up to 100 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog

November 2014

DocID026289 Rev 3

STM32F411VEH6 – LQFP100 Pinout

Pin	Name	Type	I/O Structure	Description / Alternate Functions	Additional Functions
1	VBAT	S	-	Battery supply	-
2	PC13	I/O	TC	RTC_AF1 / EVENTOUT	-
3	PC14-OSC32_IN	I/O	TC	OSC32_IN / EVENTOUT	-
4	PC15-OSC32_OUT	I/O	TC	OSC32_OUT / EVENTOUT	-
5	PH0-OSC_IN	I/O	TC	OSC_IN / EVENTOUT	-
6	PH1-OSC_OUT	I/O	TC	OSC_OUT / EVENTOUT	-
7	NRST	I	NRST	Reset pin (active low)	-
8	VSSA/VREF-	S	-	Analog ground / Reference ground	-
9	VDDA/VREF+	S	-	Analog supply / Reference supply	-
10	PA0-WKUP	I/O	TC	TIM2_CH1/TIM2_ETR, TIM5_CH1, USART2_CTS, EVENTOUT	ADC1_0, WKUP1
11	PA1	I/O	FT	TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, EVENTOUT	ADC1_1
12	PA2	I/O	FT	TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, EVENTOUT	ADC1_2
13	PA3	I/O	FT	TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, EVENTOUT	ADC1_3
14	PA4	I/O	TC	SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT	ADC1_4
15	PA5	I/O	TC	TIM2_CH1/TIM2_ETR, SPI1_SCK/I2S1_CK, EVENTOUT	ADC1_5
16	PA6	I/O	FT	TIM1_BKIN, TIM3_CH1, SPI1_MISO, I2S2_MCK, SDIO_CMD, EVENTOUT	ADC1_6
17	PA7	I/O	FT	TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SD, EVENTOUT	ADC1_7
18	PC4	I/O	FT	EVENTOUT	ADC1_14
19	PC5	I/O	FT	EVENTOUT	ADC1_15
20	PB0	I/O	FT	TIM1_CH2N, TIM3_CH3, SPI5_SCK/I2S5_CK, EVENTOUT	ADC1_8
21	PB1	I/O	FT	TIM1_CH3N, TIM3_CH4, SPI5_NSS/I2S5_WS, EVENTOUT	ADC1_9
22	PB2	I/O	FT	EVENTOUT	BOOT1
23	PE7	I/O	FT	TIM1_ETR, EVENTOUT	-
24	PE8	I/O	FT	TIM1_CH1N, EVENTOUT	-
25	PE9	I/O	FT	TIM1_CH1, EVENTOUT	-
26	PE10	I/O	FT	TIM1_CH2N, EVENTOUT	-
27	VSS	S	-	Ground	-
28	VDD	S	-	Supply	-
29	PE11	I/O	FT	TIM1_CH2, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, EVENTOUT	-
30	PE12	I/O	FT	TIM1_CH3N, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, EVENTOUT	-
31	PE13	I/O	FT	TIM1_CH3, SPI4_MISO, SPI5_MISO, EVENTOUT	-
32	PE14	I/O	FT	TIM1_CH4, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, EVENTOUT	-
33	PE15	I/O	FT	TIM1_BKIN, EVENTOUT	-
34	PB10	I/O	TC	TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, SDIO_D7, EVENTOUT	-
35	PB11	I/O	TC	TIM2_CH4, I2C2_SDA, I2S2_CKIN, EVENTOUT	-
36	PB12	I/O	TC	TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, SPI3_SCK/I2S3_CK, EVENTOUT	-
37	PB13	I/O	TC	TIM1_CH1N, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, EVENTOUT	-
38	PB14	I/O	TC	TIM1_CH2N, SPI2_MISO, I2S2ext_SD, SDIO_D6, EVENTOUT	-
39	PB15	I/O	TC	RTC_50Hz, TIM1_CH3N, SPI2_MOSI/I2S2_SD, SDIO_CK, EVENTOUT	-
40	PD8	I/O	TC	EVENTOUT	-
41	PD9	I/O	TC	EVENTOUT	-
42	PD10	I/O	TC	EVENTOUT	-
43	PD11	I/O	TC	EVENTOUT	-
44	PD12	I/O	TC	TIM4_CH1, EVENTOUT	-
45	PD13	I/O	TC	TIM4_CH2, EVENTOUT	-
46	PD14	I/O	TC	TIM4_CH3, EVENTOUT	-
47	PD15	I/O	TC	TIM4_CH4, EVENTOUT	-
48	PC6	I/O	TC	TIM3_CH1, I2S2_MCK, USART6_TX, SDIO_D6, EVENTOUT	-
49	PC7	I/O	TC	TIM3_CH2, SPI2_SCK/I2S2_CK, I2S3_MCK, USART6_RX, SDIO_D7, EVENTOUT	-
50	PC8	I/O	TC	TIM3_CH3, USART6_CK, SDIO_D0, EVENTOUT	-
51	PC9	I/O	TC	TIM3_CH4, I2C3_SDA, I2S2_CKIN, SDIO_D1, EVENTOUT	-
52	PA8	I/O	TC	TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF, SDIO_D1, EVENTOUT	-
53	PA9	I/O	TC	TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS, SDIO_D2, EVENTOUT	-
54	PA10	I/O	TC	TIM1_CH3, USART1_RX, USB_FS_ID, EVENTOUT	-
55	PA11	I/O	TC	TIM1_CH4, USART1_CTS, USART6_TX, USB_FS_DM, EVENTOUT	-
56	PA12	I/O	TC	TIM1_ETR, USART1_RTS, USART6_RX, USB_FS_DP, EVENTOUT	-
57	PA13	I/O	TC	JTMS-SWDIO, EVENTOUT	-
58	VCAP_1	S	-	Decoupling capacitor pin	-
59	VSS	S	-	Ground	-
60	VDD	S	-	Supply	-
61	PA14	I/O	TC	JTCK-SWCLK, EVENTOUT	-
62	PA15	I/O	TC	JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART1_TX, EVENTOUT	-
63	PC10	I/O	TC	SPI3_SCK/I2S3_CK, SDIO_D2, EVENTOUT	-
64	PC11	I/O	TC	I2S3ext_SD, SPI3_MISO, SDIO_D3, EVENTOUT	-
65	PC12	I/O	TC	SPI3_MOSI/I2S3_SD, SDIO_CK, EVENTOUT	-
66	PD0	I/O	TC	EVENTOUT	-
67	PD1	I/O	TC	EVENTOUT	-
68	PD2	I/O	TC	TIM3_ETR, SDIO_CMD, EVENTOUT	-
69	PD3	I/O	TC	SPI2_SCK/I2S2_CK, USART2_CTS, EVENTOUT	-
70	PD4	I/O	TC	USART2_RTS, EVENTOUT	-
71	PD5	I/O	TC	USART2_TX, EVENTOUT	-
72	PD6	I/O	TC	SPI3_MOSI/I2S3_SD, USART2_RX, EVENTOUT	-
73	PD7	I/O	TC	USART2_CK, EVENTOUT	-
74	PB3	I/O	TC	JTDO-SWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX, I2C2_SDA, EVENTOUT	-
75	PB4	I/O	TC	JTRST, TIM3_CH1, SPI1_MISO, I2S3ext_SD, I2C3_SDA, SDIO_D0, EVENTOUT	-
76	PB5	I/O	TC	TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, SDIO_D3, EVENTOUT	-
77	PB6	I/O	TC	TIM4_CH1, I2C1_SCL, USART1_TX, EVENTOUT	-
78	PB7	I/O	TC	TIM4_CH2, I2C1_SDA, USART1_RX, SDIO_D0, EVENTOUT	-
79	BOOT0	I	B	Boot pin (selects boot source)	-
80	PB8	I/O	TC	TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, I2C3_SDA, SDIO_D4, EVENTOUT	-
81	PB9	I/O	TC	TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C2_SDA, SDIO_D5, EVENTOUT	-
82	VSS	S	-	Ground	-
83	VDD	S	-	Supply	-
84	PC0	I/O	TC	EVENTOUT	ADC1_10
85	PC1	I/O	TC	EVENTOUT	ADC1_11
86	PC2	I/O	TC	SPI2_MISO, I2S2ext_SD, EVENTOUT	ADC1_12
87	PC3	I/O	TC	SPI2_MOSI/I2S2_SD, EVENTOUT	ADC1_13
88	PE0	I/O	TC	TIM4_ETR, EVENTOUT	-
89	PE1	I/O	TC	EVENTOUT	-
90	PE2	I/O	TC	TRACECLK, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, EVENTOUT	-
91	PE3	I/O	TC	TRACED0, EVENTOUT	-
92	PE4	I/O	TC	TRACED1, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, EVENTOUT	-
93	PE5	I/O	TC	TRACED2, TIM9_CH1, SPI4_MISO, SPI5_MISO, EVENTOUT	-
94	PE6	I/O	TC	TRACED3, TIM9_CH2, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, EVENTOUT	-
95	VSS	S	-	Ground	-
96	VDD	S	-	Supply	-
97	PH0	I/O	TC	OSC_IN (when used as oscillator)	-
98	PH1	I/O	TC	OSC_OUT (when used as oscillator)	-
99	BYPASS_REG	S	-	Regulator bypass / internal reset control	-
100	VSS	S	-	Ground	-

Notes

• PC13, PC14, PC15: Limited output capability (3 mA max sink current). Speed limited to 2 MHz with max 30 pF load. Not suitable as current source (e.g., LED drive).
• PA0-WKUP: When BYPASS_REG is set to VDD (regulator off/internal reset ON), PA0 is used as internal Reset (active low).
• FT pins: 5 V tolerant except in analog mode or oscillator mode (PH0, PH1, PC14, PC15).
• BOOT0 (Pin 79): Dedicated boot pin; selects boot source on reset.
• VCAP_1 (Pin 58): Decoupling capacitor pin for internal regulator.
• All I/Os are floating inputs during and after reset unless otherwise specified.

The definition and values of input/output AC characteristics are given in Figure 31 and Table 55 , respectively.

Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .

Table 55. I/O AC characteristics (1)(2)

OSPEEDRy [1:0] bit value (1)	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
00	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 2.70 V	-	-	4	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 1.7 V	-	-	2	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	8	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	4	MHz
00	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD = 1.7 V to 3.6 V	-	-	100	ns
01	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 2.70 V	-	-	25	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 1.7 V	-	-	12.5	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	50	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	20	MHz
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD ≥ 2.7 V	-	-	10	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD ≥ 1.7 V	-	-	20	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	6	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	10	ns
10	f max(IO)out	Maximum frequency (3)	C L = 40 pF, V DD ≥ 2.70 V	-	-	50 (4)	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 40 pF, V DD ≥ 1.7 V	-	-	25	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	100 (4)	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	50 (4)	MHz
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 40 pF, V DD ≥ 2.70 V	-	-	6	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 40 pF, V DD ≥ 1.7 V	-	-	10	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	4	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	6	ns
11	t f(IO)out / t	max(IO)out Maximum frequency (3)	C L = 30 pF, V DD ≥ 2.70 V	-	-	100 (4)
11	t f(IO)out / t	max(IO)out Maximum frequency (3)	C L = 30 pF, V DD ≥ 1.7 V	-	-	50 (4)	MHz
11	t f(IO)out / t	Output high to low level fall time and output low to high level rise time	C L = 30 pF, V DD ≥ 2.70 V C L = 30 pF, V DD ≥ 1.7 V	- -	- -	4 6
11	r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	2.5	ns
11	t f(IO)out / t	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	4
-	t EXTIpw	Pulse width of external signals detected by the EXTI controller		10	-	-	ns

119

1. For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.

Figure 31. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 11. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
V DD -V SS	External main supply voltage (including V DDA ,V DD and V BAT ) (1)	-0.3	4.0	V
V IN	Input voltage on FT pins (2)	V SS -0.3	V DD +4.0	V
V IN	Input voltage on any other pin	V SS -0.3	4.0	V
V IN	Input voltage for BOOT0	V SS	9.0	V
\	∆ V DDx \		Variations between different V DD power pins	-
\	V SSX - V SS \		Variations between all the different ground pins	-
V ESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 6.3.14: Absolute maximum ratings (electrical	see Section 6.3.14: Absolute maximum ratings (electrical

Table 12. Current characteristics

Table 12. Current characteristics

Symbol	Ratings	Max.	Unit
Σ I VDD	Total current into sum of all V DD_x power lines (source) (1)	160	mA
Σ I VSS	Total current out of sum of all V SS_x ground lines (sink) (1)	-160	mA
I VDD	Maximum current into each V DD_x power line (source) (1)	100	mA
I VSS	Maximum current out of each V SS_x ground line (sink) (1)	-100	mA
I IO	Output current sunk by any I/O and control pin	25	mA
I IO	Output current sourced by any I/O and control pin	-25	mA
Σ I IO	Total output current sunk by sum of all I/O and control pins (2)	120	mA
Σ I IO	Total output current sourced by sum of all I/Os and control pins (2)	-120	mA
I INJ(PIN) (3)	Injected current on FT pins (4)	-5/+0	mA
I INJ(PIN) (3)	Injected current on NRST and B pins (4)	-5/+0	mA
Σ I INJ(PIN)	Total injected current (sum of all I/O and control pins) (5)	±25	mA

1. This current consumption must be correctly distributed over all I/Os and control pins.

2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics .

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	125	°C
T LEAD	Maximum lead temperature during soldering (WLCSP49, LQFP64/100, UFQFPN48, UFBGA100)	see note (1)	°C

119

The maximum chip junction temperature (T J max) must never exceed the values given in Table 12: General operating conditions on page 43 .

The maximum chip-junction temperature, T J max., in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (PD max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.