STM32F411CEU6

life.augmented

Manufacturer

STMicroelectronics

Overview

Part: STM32F411xC STM32F411xE

Type: ARM® Cortex®-M4 32b MCU+FPU

Key Specs:

  • Core frequency: up to 100 MHz
  • Flash memory: up to 512 Kbytes
  • SRAM: 128 Kbytes
  • DMIPS: 125 DMIPS
  • Application supply: 1.7 V to 3.6 V
  • ADC: 1×12-bit, 2.4 MSPS
  • Run power consumption: 100 μA/MHz (peripheral off)

Features:

  • Dynamic Efficiency Line with BAM (Batch Acquisition Mode)
  • ARM® 32-bit Cortex®-M4 CPU with FPU
  • Adaptive real-time accelerator (ART Accelerator™)
  • Memory protection unit
  • POR, PDR, PVD and BOR
  • 4-to-26 MHz crystal oscillator
  • Internal 16 MHz factory-trimmed RC
  • 32 kHz oscillator for RTC with calibration
  • Internal 32 kHz RC with calibration
  • General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
  • Up to 11 timers: up to six 16-bit, two 32-bit, two watchdog, and a SysTick timer
  • Serial wire debug (SWD) & JTAG interfaces
  • Cortex®-M4 Embedded Trace Macrocell™
  • Up to 81 I/O ports with interrupt capability
  • Up to 78 fast I/Os up to 100 MHz
  • Up to 77 5 V-tolerant I/Os
  • Up to 13 communication interfaces: 3 x I²C, 3 USARTs, 5 SPI/I2Ss, SDIO, USB 2.0 full-speed device/host/OTG
  • CRC calculation unit
  • 96-bit unique ID
  • RTC: subsecond accuracy, hardware calendar
  • All packages are ECOPACK®2

Applications:

  • null

Package:

  • WLCSP49
  • LQFP64/100
  • UFQFPN48
  • UFBGA100

Features

  • Dynamic Efficiency Line with BAM (Batch Acquisition Mode)
  • Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit, 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
    • up to 512 Kbytes of Flash memory
    • 128 Kbytes of SRAM
  • · Clock, reset and supply management
    • 1.7 V to 3.6 V application supply and I/Os
    • POR, PDR, PVD and BOR
    • 4-to-26 MHz crystal oscillator
    • Internal 16 MHz factory-trimmed RC
    • 32 kHz oscillator for RTC with calibration
    • Internal 32 kHz RC with calibration
  • Power consumption
    • Run: 100 μA/MHz (peripheral off)
    • Stop (Flash in Stop mode, fast wakeup time): 42 μA Typ @ 25C; 65 μA max @25 °C
    • Stop (Flash in Deep power down mode, fast wakeup time): down to 10 μA @ 25 °C; 30 μA max @25 °C
    • Standby: 2.4 $\mu A$ @25 °C / 1.7 V without RTC; 12 $\mu A$ @85 °C @1.7 V
    • VRAT supply for RTC: 1 μA @25 °C
  • 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
  • General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
  • Up to 11 timers: up to six 16-bit, two 32-bit timers up to 100 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog

timers (independent and window) and a SysTick timer

  • Debug mode
    • Serial wire debug (SWD) & JTAG interfaces
    • Cortex®-M4 Embedded Trace Macrocell™
  • Up to 81 I/O ports with interrupt capability
    • Up to 78 fast I/Os up to 100 MHz
    • Up to 77 5 V-tolerant I/Os
  • Up to 13 communication interfaces
    • Up to 3 x I2C interfaces (SMBus/PMBus)
    • Up to 3 USARTs (2 x 12.5 Mbit/s, 1 x 6.25 Mbit/s), ISO 7816 interface, LIN, IrDA, modem control)
    • Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or I2S audio protocol, SPI2 and SPI3 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock
    • SDIO interface (SD/MMC/eMMC)
    • Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with on-chip PHY
  • · CRC calculation unit
  • 96-bit unique ID
  • RTC: subsecond accuracy, hardware calendar
  • All packages (WLCSP49, LQFP64/100, UFQFPN48, UFBGA100) are ECOPACK®2

Table 1. Device summary

ReferencePart number
STM32F411xCSTM32F411CC,
STM32F411RC, STM32F411VC
STM32F411xESTM32F411CE,
STM32F411RE, STM32F411VE

Pin Configuration

Figure 9. STM32F411xC/xE WLCSP49 pinout

| $ | 9'' | 966 | %227 | 3% | 3% | 3$ | 3$ | |----|---------------|---------------|------|-----|-----|-------|-----|--| | % | 9%$7 | 3'5
B21 | 3% | 3% | 3$ | 9'' | 966 | | & | 3&
26&B,1 | 3&
26&B287 | 3% | 3% | 3$ | 3$ | 3$ | | ' | 3+
26&B,1 | 3+
26&B287 | 3& | 3% | 966 | 3$ | 3$ | | ( | 1567 | 966$
95() | 3$ | 3$ | 3% | 3% | 3% | | ) | 9''$
95() | 3$ | 3$ | 3$ | 3$ | 9'' | 3% | | * | 3$ | 3$ | 3% | 3% | 3% | 9&$3 | 3% |

  1. The above figure shows the package bump side.

Figure 10. STM32F411xC/xE UFQFPN48 pinout

  1. The above figure shows the package top view.

577

Figure 11. STM32F411xC/xE LQFP64 pinout

  1. The above figure shows the package top view.

Figure 12. STM32F411xC/xE LQFP100 pinout

  1. The above figure shows the package top view.

Figure 13. STM32F411xC/xE UFBGA100 pinout

| | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | |---|------------------|-------------|-------|---------|-------|-------|-------------|-------|----------|--------|--------|--------|---| | | | | | | | | | | | | Α | PE3 | PE1 | (PB8) | (BOO)10 | (PD7) | (PD5) | PB4 | (PBЗ) | PA15 | (PA14) | (PA13) | (PA12) | | B | PE4 | PE2 | PB9 | PB7 | PB6 | PD6 | PD4 | PD3 | PD1 | C12 | PC10 | PA11 | | C | C13
NILTA | PE5 | (PE0) | VDD | PB5 | |

- | PD2 | PD0 | PC11 | VCAP2 | PA10 | | D | FC14
OSC32_II | N PE6 | vss | | | |
| | | PA9 | PA8 | PC9 | | E | C15)
OSC32_ | OUT | BYPAS | SS_REG | | |
| | | PC8 | PC7 | PC6 | | F | PHO N | VSS | | | | |

- | | | | VSS | VSS | | G | PH1
OSC O | UT (VDD) | | | | | — —
| | | | VDD | (DD) | _ | | H | PCO | NRS | PDR | ON | | |
| | | (D15) | PD14 | PD13 | | J | VSSA | PC1 | PC2 | | | |

| | | (D12) | PD11 | PD10 | | K | VREI)- | PC3 | PA2 | PA5 | PC4 | |
| PD9 | (PB11) | PB15 | PB14 | (PB13) | | L | VREP+ | PA0
WKUP | (PA3) | PA6 | PC5 | (PB2) | PE8 | PE10 | PE12 | PB10 | VCAP1 | PB12 | | M | (/DDA) | (PA1) | PA4 | PA7 | (PB0) | (PB1) | PE7 | PE9 | (PE11) | PE13 | PE1 | PE15 | | | | | | | | |
| | | | | MS331 |

  1. This figure shows the package top view

Table 7. Legend/abbreviations used in the pinout table

NameAbbreviationDefinition
Pin nameUnless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
SSupply pin
Pin typeIInput only pin
I/OInput/ output pin
FT5 V tolerant I/O
TCStandard 3.3 V I/O
I/O structureBDedicated BOOT0 pin
NRSTBidirectional reset pin with embedded weak pull-up resistor
NotesUnless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions		Functions selected through GPIOx_AFR registers
Additional
functions		Functions directly selected/enabled through peripheral registers

Table 8. STM32F411xC/xE pin definitions

| | | Pin number | |--------|--------|------------|---------|-----------|------------------------------------------|----------|---------------|-------|-----------------------------------------------------------------|----------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | 1 | B2 | PE2 | I/O | FT | - | TRACECLK,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
EVENTOUT | - | | - | - | - | 2 | A1 | PE3 | I/O | FT | - | TRACED0,
EVENTOUT | - | | - | - | - | 3 | B1 | PE4 | I/O | FT | - | TRACED1,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
EVENTOUT | - | | - | - | - | 4 | C2 | PE5 | I/O | FT | - | TRACED2,
TIM9_CH1,
SPI4_MISO,
SPI5_MISO,
EVENTOUT | - |

Table 8. STM32F411xC/xE pin definitions (continued)

| | Pir | numb | oer | |--------|--------|---------|---------|-----------|------------------------------------------------------|----------|---------------|---------------|-------------------------------------------------------------------------------|------------------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset) (1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | 5 | D2 | PE6 | I/O | FT | - | TRACED3,
TIM9_CH2,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
EVENTOUT | - | | - | - | - | - | D3 | VSS | S | - | - | - | - | | - | - | - | - | C4 | VDD | S | - | - | - | - | | 1 | 1 | B7 | 6 | E2 | VBAT | S | 1 | - | - | - | | 2 | 2 | D5 | 7 | C1 | PC13-
ANTI_TAMP | I/O | FT | (2)(3) | - | RTC_AMP1,
RTC_OUT, RTC_TS | | 3 | 3 | C7 | 8 | D1 | PC14-
OSC32_IN | I/O | FT | (2)(3)
(4) | - | OSC32_IN | | 4 | 4 | C6 | 9 | E1 | PC15-
OSC32_OUT | I/O | FT | - | - | OSC32_OUT | | - | - | - | 10 | F2 | VSS | S | - | - | - | - | | - | ı | ı | 11 | G2 | VDD | S | - | ı | - | - | | 5 | 5 | D7 | 12 | F1 | PH0 - OSC_IN | I/O | FT | ı | - | OSC_IN | | 6 | 6 | D6 | 13 | G1 | PH1 -
OSC_OUT | I/O | FT | - | - | OSC_OUT | | 7 | 7 | E7 | 14 | H2 | NRST | I/O | FT | - | EVENTOUT | - | | - | 8 | - | 15 | H1 | PC0 | I/O | FT | - | EVENTOUT | ADC1_10 | | - | 9 | - | 16 | J2 | PC1 | I/O | FT | - | EVENTOUT | ADC1_11 | | - | 10 | - | 17 | J3 | PC2 | I/O | FT | - | SPI2_MISO,
I2S2ext_SD,
EVENTOUT | ADC1_12 | | - | 11 | - | 18 | K2 | PC3 | I/O | FT | - | SPI2_MOSI/I2S2_SD,
EVENTOUT | ADC1_13 | | - | - | - | 19 | - | VDD | S | - | - | - | - | | 8 | 12 | E6 | 20 | J1 | VSSA | S | - | - | - | - | | _ | 1 | 1 | - | K1 | VREF- | S | - | 1 | - | - | | 9 | 13 | F7 | 21 | L1 | VREF+ | S | - | ı | - | - | | - | - | - | 22 | M1 | VDDA | S | - | - | - | - |

Table 8. STM32F411xC/xE pin definitions (continued)

| | | Pin number | |--------|--------|------------|---------|-----------|------------------------------------------|----------|---------------|-------|-----------------------------------------------------------------------------|----------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | 10 | 14 | F6 | 23 | L2 | PA0-WKUP | I/O | TC | (5) | TIM2_CH1/TIM2_ET,
TIM5_CH1,
USART2_CTS,
EVENTOUT | ADC1_0, WKUP1 | | 11 | 15 | G7 | 24 | M2 | PA1 | I/O | FT | - | TIM2_CH2,
TIM5_CH2,
SPI4_MOSI/I2S4_SD,
USART2_RTS,
EVENTOUT | ADC1_1 | | 12 | 16 | E5 | 25 | K3 | PA2 | I/O | FT | - | TIM2_CH3,
TIM5_CH3,
TIM9_CH1,
I2S2_CKIN,
USART2_TX,
EVENTOUT | ADC1_2 | | 13 | 17 | E4 | 26 | L3 | PA3 | I/O | FT | - | TIM2_CH4,
TIM5_CH4,
TIM9_CH2,
I2S2_MCK,
USART2_RX,
EVENTOUT | ADC1_3 | | - | 18 | - | 27 | - | VSS | S | - | - | - | - | | - | - | - | - | E3 | BYPASS_REG | S | - | - | - | - | | - | 19 | - | 28 | - | VDD | I | FT | - | EVENTOUT | - | | 14 | 20 | G6 | 29 | M3 | PA4 | I/O | TC | - | SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
EVENTOUT | ADC1_4 | | 15 | 21 | F5 | 30 | K4 | PA5 | I/O | TC | - | TIM2_CH1/TIM2_ET,
SPI1_SCK/I2S1_CK,
EVENTOUT | ADC1_5 | | 16 | 22 | F4 | 31 | L4 | PA6 | I/O | FT | - | TIM1_BKIN,
TIM3_CH1,
SPI1_MISO,
I2S2_MCK,
SDIO_CMD,
EVENTOUT | ADC1_6 | | 17 | 23 | F3 | 32 | M4 | PA7 | I/O | FT | - | TIM1_CH1N,
TIM3_CH2,
SPI1_MOSI/I2S1_SD,
EVENTOUT | ADC1_7 |

Table 8. STM32F411xC/xE pin definitions (continued)

| | | Pin number | |--------|--------|------------|---------|-----------|------------------------------------------|----------|---------------|-------|-------------------------------------------------------------------|----------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | 24 | - | 33 | K5 | PC4 | I/O | FT | - | EVENTOUT | ADC1_14 | | - | 25 | - | 34 | L5 | PC5 | I/O | FT | - | EVENTOUT | ADC1_15 | | 18 | 26 | G5 | 35 | M5 | PB0 | I/O | FT | - | TIM1_CH2N,
TIM3_CH3,
SPI5_SCK/I2S5_CK,
EVENTOUT | ADC1_8 | | 19 | 27 | G4 | 36 | M6 | PB1 | I/O | FT | - | TIM1_CH3N,
TIM3_CH4,
SPI5_NSS/I2S5_WS,
EVENTOUT | ADC1_9 | | 20 | 28 | G3 | 37 | L6 | PB2 | I/O | FT | - | EVENTOUT | BOOT1 | | - | - | - | 38 | M7 | PE7 | I/O | FT | - | TIM1_ETR,
EVENTOUT | - | | - | - | - | 39 | L7 | PE8 | I/O | FT | - | TIM1_CH1N,
EVENTOUT | - | | - | - | - | 40 | M8 | PE9 | I/O | FT | - | TIM1_CH1,
EVENTOUT | - | | - | - | - | 41 | L8 | PE10 | I/O | FT | - | TIM1_CH2N,
EVENTOUT | - | | - | - | - | 42 | M9 | PE11 | I/O | FT | - | TIM1_CH2,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
EVENTOUT | - | | - | - | - | 43 | L9 | PE12 | I/O | FT | - | TIM1_CH3N,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
EVENTOUT | - | | - | - | - | 44 | M10 | PE13 | I/O | FT | - | TIM1_CH3,
SPI4_MISO,
SPI5_MISO,
EVENTOUT | - | | - | - | - | 45 | M11 | PE14 | I/O | FT | - | TIM1_CH4,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
EVENTOUT | - | | - | - | - | 46 | M12 | PE15 | I/O | FT | - | TIM1_BKIN,
EVENTOUT | - |

Table 8. STM32F411xC/xE pin definitions (continued)

| | | Pin number | |--------|--------|------------|---------|-----------|------------------------------------------|----------|---------------|-------|-----------------------------------------------------------------------------------------------------|----------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | 21 | 29 | E3 | 47 | L10 | PB10 | I/O | FT | - | TIM2_CH3,
I2C2_SCL,
SPI2_SCK/I2S2_CK,
I2S3_MCK, SDIO_D7,
EVENTOUT | - | | - | - | - | - | K9 | PB11 | I/O | FT | - | TIM2_CH4,
I2C2_SDA,
I2S2_CKIN,
EVENTOUT | - | | 22 | 30 | G2 | 48 | L11 | VCAP1 | S | - | - | - | - | | 23 | 31 | D3 | 49 | F12 | VSS | S | - | - | - | - | | 24 | 32 | F2 | 50 | G12 | VDD | S | - | - | - | - | | 25 | 33 | E2 | 51 | L12 | PB12 | I/O | FT | - | TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SPI4_NSS/I2S4_WS,
SPI3_SCK/I2S3_CK,
EVENTOUT | - | | 26 | 34 | G1 | 52 | K12 | PB13 | I/O | FT | - | TIM1_CH1N,
SPI2_SCK/I2S2_CK,
SPI4_SCK/I2S4_CK,
EVENTOUT | - | | 27 | 35 | F1 | 53 | K11 | PB14 | I/O | FT | - | TIM1_CH2N,
SPI2_MISO,
I2S2ext_SD,
SDIO_D6,
EVENTOUT | - | | 28 | 36 | E1 | 54 | K10 | PB15 | I/O | FT | - | RTC_50Hz,
TIM1_CH3N,
SPI2_MOSI/I2S2_SD,
SDIO_CK,
EVENTOUT | RTC_REFIN | | - | - | - | 55 | - | PD8 | I/O | FT | - | - | - | | - | - | - | 56 | K8 | PD9 | I/O | FT | - | - | - | | - | - | - | 57 | J12 | PD10 | I/O | FT | - | - | - | | - | - | - | 58 | J11 | PD11 | I/O | FT | - | - | - | | - | - | - | 59 | J10 | PD12 | I/O | FT | - | TIM4_CH1,
EVENTOUT | - |

Table 8. STM32F411xC/xE pin definitions (continued)

| | | Pin number | |--------|--------|------------|---------|-----------|------------------------------------------|----------|---------------|-------|------------------------------------------------------------------------------------|----------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | 60 | H12 | PD13 | I/O | FT | - | TIM4_CH2,
EVENTOUT | - | | - | - | - | 61 | H11 | PD14 | I/O | FT | - | TIM4_CH3,
EVENTOUT | - | | - | - | - | 62 | H10 | PD15 | I/O | FT | - | TIM4_CH4,
EVENTOUT | - | | - | 37 | - | 63 | E12 | PC6 | I/O | FT | - | TIM3_CH1,
I2S2_MCK,
USART6_TX,
SDIO_D6,
EVENTOUT | - | | - | 38 | - | 64 | E11 | PC7 | I/O | FT | - | TIM3_CH2,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
USART6_RX,
SDIO_D7,
EVENTOUT | - | | - | 39 | - | 65 | E10 | PC8 | I/O | FT | - | TIM3_CH3,
USART6_CK,
SDIO_D0,
EVENTOUT | - | | - | 40 | - | 66 | D12 | PC9 | I/O | FT | - | MCO_2, TIM3_CH4,
I2C3_SDA,
I2S2_CKIN,
SDIO_D1,
EVENTOUT | - | | 29 | 41 | D1 | 67 | D11 | PA8 | I/O | FT | - | MCO_1, TIM1_CH1,
I2C3_SCL,
USART1_CK,
USB_FS_SOF,
SDIO_D1,
EVENTOUT | - | | 30 | 42 | D2 | 68 | D10 | PA9 | I/O | FT | - | TIM1_CH2,
I2C3_SMBA,
USART1_TX,
USB_FS_VBUS,
SDIO_D2,
EVENTOUT | OTG_FS_VBUS |

Table 8. STM32F411xC/xE pin definitions (continued)

| | | Pin number | |--------|--------|------------|---------|-----------|------------------------------------------|--------------------------------------------------------------------------------------------------------|---------------|-------|-----------------------------------------------------------------------------------------------------|----------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | 31 | 43 | C2 | 69 | C12 | PA10 | I/O | FT | - | TIM1_CH3,
SPI5_MOSI/I2S5_SD,
USART1_RX,
USB_FS_ID,
EVENTOUT | - | | 32 | 44 | C1 | 70 | B12 | PA11 | I/O | | - | TIM1_CH4,
SPI4_MISO,
USART1_CTS,
USART6_TX,
USB_FS_DM,
EVENTOUT | - | | 33 | 45 | C3 | 71 | A12 | PA12 | FT
TIM1_ETR,
SPI5_MISO,
USART1_RTS,
I/O
FT
-
USART6_RX,
USB_FS_DP,
EVENTOUT | | - | | 34 | 46 | B3 | 72 | A11 | PA13 | I/O | FT | - | JTMS-SWDIO,
EVENTOUT | - | | - | - | - | 73 | C11 | VCAP2 | S | - | - | - | - | | 35 | 47 | B1 | 74 | F11 | VSS | S | - | - | - | - | | 36 | 48 | B2 | 75 | G11 | VDD | S | - | - | - | - | | 37 | 49 | A1 | 76 | A10 | PA14 | I/O | FT | - | JTCK-SWCLK,
EVENTOUT | - | | 38 | 50 | A2 | 77 | A9 | PA15 | I/O | FT | - | JTDI,
TIM2_CH1/TIM2_ETR
,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART1_TX,
EVENTOUT | - | | - | 51 | - | 78 | B11 | PC10 | I/O | FT | - | SPI3_SCK/I2S3_CK,
SDIO_D2,
EVENTOUT | - | | - | 52 | - | 79 | C10 | PC11 | I/O | FT | - | I2S3ext_SD,
SPI3_MISO,
SDIO_D3,
EVENTOUT | - | | - | 53 | - | 80 | B10 | PC12 | I/O | FT | - | SPI3_MOSI/I2S3_SD,
SDIO_CK,
EVENTOUT | - |

Table 8. STM32F411xC/xE pin definitions (continued)

| | | Pin number | |--------|--------|------------|---------|-----------|------------------------------------------|------------------------------------------|---------------|-------|---------------------------------------------------------------------------------------------------------|----------------------| | UQFN48 | LQFP64 | WLCSP49 | LQFP100 | UFBGA100L | Pin name
(function after
reset)(1) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | | - | - | - | 81 | C9 | PD0 | I/O | FT | - | EVENTOUT | - | | - | - | - | 82 | B9 | PD1 | I/O | FT | - | EVENTOUT | - | | - | 54 | - | 83 | C8 | PD2 | I/O | FT | - | TIM3_ETR,
SDIO_CMD,
EVENTOUT | - | | - | - | - | 84 | B8 | PD3 | I/O | FT | - | SPI2_SCK/I2S2_CK,
USART2_CTS,
EVENTOUT | - | | - | - | - | 85 | B7 | PD4 | I/O | FT | - | USART2_RTS,
EVENTOUT | - | | - | - | - | 86 | A6 | PD5 | USART2_TX,
I/O
FT
-
EVENTOUT | | | - | | - | - | - | 87 | B6 | PD6 | I/O | FT | - | SPI3_MOSI/I2S3_SD,
USART2_RX,
EVENTOUT | - | | - | - | - | 88 | A5 | PD7 | I/O | FT | - | USART2_CK,
EVENTOUT | - | | 39 | 55 | A3 | 89 | A8 | PB3 | I/O | FT | - | JTDO-SWO,
TIM2_CH2,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
USART1_RX,
I2C2_SDA,
EVENTOUT | - | | 40 | 56 | A4 | 90 | A7 | PB4 | I/O | FT | - | JTRST, TIM3_CH1,
SPI1_MISO,
SPI3_MISO,
I2S3ext_SD,
I2C3_SDA, SDIO_D0,
EVENTOUT | - | | 41 | 57 | B4 | 91 | C5 | PB5 | I/O | TC | - | TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
SDIO_D3,
EVENTOUT | - | | 42 | 58 | C4 | 92 | B5 | PB6 | I/O | FT | - | TIM4_CH1,
I2C1_SCL,
USART1_TX,
EVENTOUT | - |

43 59 D4 93 B4 PB7 I/O FT - TIM4_CH2, I2C1_SDA, USART1_RX, SDIO_D0, EVENTOUT - 44 60 A5 94 A4 BOOT0 I B - - - 45 61 B5 95 A3 PB8 I/O FT - TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, I2C3_SDA, SDIO_D4, EVENTOUT - 46 62 C5 96 B3 PB9 I/O FT - TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C2_SDA, SDIO_D5, EVENTOUT - - - - 97 C3 PE0 I/O FT - TIM4_ETR, EVENTOUT - - - - 98 A2 PE1 I/O FT - EVENTOUT - 47 63 A6 99 - VSS S - - - - - - B6 - H3 PDR_ON I FT - - - Pin number Pin name (function after reset)(1) Pin type I/O structure Notes Alternate functions Additional functions UQFN48 LQFP64 WLCSP49 LQFP100 UFBGA100L

Table 8. STM32F411xC/xE pin definitions (continued)

48 64 A7 100 - VDD S - - - -

1. Function availability depends on the chosen device.

2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F411xx reference manual.

4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

5. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low)

Table 9. Alternate function mapping

AF00AF01AF02AF03AF04AF05AF06AF07AF08AF09AF10AF11AF12AF13AF14AF15
PortSYS_AFTIM1/TIM2TIM3/
TIM4/ TIM5		TIM9/
TIM10/
TIM11		I2C1/I2C2/
I2C3		SPI1/I2S1S
PI2/
I2S2/SPI3/
I2S3		SPI2/I2S2/
SPI3/
I2S3/SPI4/
I2S4/SPI5/
I2S5		SPI3/I2S3/
USART1/
USART2		USART612C2/
12C3		OTG1_FSSDIO
PA0-TIM2_CH1/
TIM2_ETR		TIM5_CH1----USART2_
CTS		-------EVENT
OUT
PA1-TIM2_CH2TIM5_CH2--SPI4_MOSI
/I2S4_SD		-USART2_
RTS		-------EVENT
OUT
PA2-TIM2_CH3TIM5_CH3TIM9_CH1-I2S2_CKIN-USART2_
TX		-------EVENT
OUT
PA3-TIM2_CH4TIM5_CH4TIM9_CH2-I2S2_MCK-USART2_
RX		-------EVENT
OUT
PA4-----SPI1_NSS/I
2S1_WS		SPI3_NSS/I2
S3_WS		USART2_
CK		-------EVENT
OUT
PA5-TIM2_CH1/
TIM2_ETR		---SPI1_SCK/I
2S1_CK		---------EVENT
OUT
PA6-TIM1_BKINTIM3_CH1--SPI1_MISOI2S2_MCK-----SDIO_
CMD		--EVENT
OUT
PA7-TIM1_CH1NTIM3_CH2--SPI1_MOSI
/I2S1_SD		---------EVENT
OUT
PA8MCO_1TIM1_CH1--I2C3_SCL--USART1_
CK		--USB_FS_
SOF		-SDIO_
D1		--EVENT
OUT
PA9-TIM1_CH2--I2C3_SMB
A		--USART1_
TX		--USB_FS_
VBUS		-SDIO_
D2		--EVENT
OUT
PA10-TIM1_CH3----SPI5_MOSI/I
2S5_SD		USART1_
RX		--USB_FS_I
D		----EVENT
OUT
PA11-TIM1_CH4----SPI4_MISOUSART1_
CTS		USART6_
TX		-USB_FS_
DM		----EVENT
OUT
PA12-TIM1_ETR----SPI5_MISOUSART1_
RTS		USART6_
RX		-USB_FS_
DP		----EVENT
OUT

Pinouts and pin description

| | | | | | T | able 9. A | Iternate f | unction ma | apping (c | ontinue | d) | |--------|------|----------------|-----------------------|---------------------|--------------------------|--------------------|------------------------------------------|---------------------------------------------------------|---------------------------------|---------|---------------|---------|------|-------------|------|------|--------------| | | | AF00 | AF01 | AF02 | AF03 | AF04 | AF05 | AF06 | AF07 | AF08 | AF09 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | | | Port | SYS_AF | TIM1/TIM2 | TIM3/
TIM4/ TIM5 | TIM9/
TIM10/
TIM11 | I2C1/I2C2/
I2C3 | SPI1/I2S1S
PI2/
I2S2/SPI3/
I2S3 | SPI2/I2S2/
SPI3/
I2S3/SPI4/
I2S4/SPI5/
I2S5 | SPI3/I2S3/
USART1/
USART2 | USART6 | 12C2/
12C3 | OTG1_FS | | SDIO | | | PA13 | JTMS-
SWDIO | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | Port A | PA14 | JTCK-
SWCLK | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PA15 | JTDI | TIM2_CH1/
TIM2_ETR | - | - | - | SPI1_NSS/I
2S1_WS | SPI3_NSS/I2
S3_WS | USART1_
TX | - | - | - | - | - | - | - | EVENT
OUT | | | PB0 | - | TIM1_CH2N | TIM3_CH3 | - | - | - | SPI5_SCK/I2
S5_CK | | - | - | - | - | - | - | - | EVENT
OUT | | | PB1 | - | TIM1_CH3N | TIM3_CH4 | - | - | - | SPI5_NSS/I2
S5_WS | | - | - | - | - | - | - | - | EVENT
OUT | | | PB2 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PB3 | JTDO-
SWO | TIM2_CH2 | - | - | - | SPI1_SCK/I
2S1_CK | SPI3_SCK/I2
S3_CK | USART1_
RX | - | I2C2_SDA | - | - | - | - | - | EVENT
OUT | | Port B | PB4 | JTRST | | TIM3_CH1 | - | - | SPI1_MISO | SPI3_MISO | I2S3ext_S
D | - | I2C3_SDA | | | SDIO_
D0 | - | - | EVENT
OUT | | Por | PB5 | - | - | TIM3_CH2 | - | I2C1_SMB
A | SPI1_MOSI
/I2S1_SD | SPI3_MOSI/I
2S3_SD | | - | - | - | - | SDIO_
D3 | - | - | EVENT
OUT | | | PB6 | - | - | TIM4_CH1 | - | I2C1_SCL | - | - | USART1_
TX | - | - | - | ı | | 1 | ı | EVENT
OUT | | | PB7 | - | - | TIM4_CH2 | - | I2C1_SDA | - | - | USART1_
RX | - | - | - | - | SDIO_
D0 | - | - | EVENT
OUT | | | PB8 | - | - | TIM4_CH3 | TIM10_CH1 | I2C1_SCL | - | SPI5_MOSI/I
2S5_SD | - | - | I2C3_SDA | - | ı | SDIO_
D4 | ı | ı | EVENT
OUT | | | PB9 | - | - | TIM4_CH4 | TIM11_CH1 | I2C1_SDA | SPI2_NSS/I
2S2_WS | - | - | - | I2C2_SDA | - | ı | SDIO_
D5 | - | - | EVENT
OUT |

Table 9. Alternate function mapping (continued)

AF00AF01AF02AF03AF04AF05AF06AF07AF08AF09AF10AF11AF12AF13AF14AF15
PortSYS_AFTIM1/TIM2TIM3/
TIM4/ TIM5		TIM9/
TIM10/
TIM11		I2C1/I2C2/
I2C3		SPI1/I2S1S
PI2/
I2S2/SPI3/
I2S3		SPI2/I2S2/
SPI3/
I2S3/SPI4/
I2S4/SPI5/
I2S5		SPI3/I2S3/
USART1/
USART2		USART6I2C2/
I2C3		OTG1_FSSDIO
PB10-TIM2_CH3--I2C2_SCLSPI2_SCK/I
2S2_CK		12S3_MCK-----SDIO_
D7		--EVENT
OUT
PB11-TIM2_CH4--I2C2_SDAI2S2_CKIN---------EVENT
OUT
ďPB12-TIM1_BKIN--I2C2_SMB
A		SPI2_NSS/I
2S2_WS		SPI4_NSS/I2
S4_WS		SPI3_SCK
/I2S3_CK		-------EVENT
OUT
D TPB13-TIM1_CH1N---SPI2_SCK/I
2S2_CK		SPI4_SCK/I2
S4_CK		--------EVENT
OUT
PB14-TIM1_CH2N---SPI2_MISOI2S2ext_SD-----SDIO_
D6		--EVENT
OUT
PB15RTC_50H
z		TIM1_CH3N---SPI2_MOSI
/I2S2_SD		------SDIO_
CK		--EVENT
OUT

Pinouts and pin description

| | | | | T | able 9. A | lternate f | unction ma | apping (d | continue | d) | |------|--------|-----------|---------------------|--------------------------|--------------------|------------------------------------------|---------------------------------------------------------|---------------------------------|---------------|---------------|---------|------|-------------|------|------|--------------------------| | | AF00 | AF01 | AF02 | AF03 | AF04 | AF05 | AF06 | AF07 | AF08 | AF09 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | | Port | SYS_AF | TIM1/TIM2 | TIM3/
TIM4/ TIM5 | TIM9/
TIM10/
TIM11 | I2C1/I2C2/
I2C3 | SPI1/I2S1S
PI2/
I2S2/SPI3/
I2S3 | SPI2/I2S2/
SPI3/
I2S3/SPI4/
I2S4/SPI5/
I2S5 | SPI3/I2S3/
USART1/
USART2 | USART6 | I2C2/
I2C3 | OTG1_FS | | SDIO | | PC0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVEN
OUT | | PC1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVEN
OUT | | PC2 | - | - | - | - | - | SPI2_MISO | I2S2ext_SD | - | - | - | - | - | - | - | - | EVEN
OUT | | PC3 | - | - | - | - | - | SPI2_MOSI
/I2S2_SD | - | - | - | - | - | - | - | - | - | EVEN
OUT | | PC4 | - | - | - | - | - | | - | - | - | - | - | - | - | - | - | EVEN
OUT | | PC5 | - | - | - | - | - | | - | - | - | - | - | - | - | - | - | EVEN
OUT | | PC6 | - | - | TIM3_CH1 | - | - | I2S2_MCK | - | - | USART6_
TX | - | - | - | SDIO_
D6 | - | - | EVEN
OUT | | PC7 | - | - | TIM3_CH2 | - | - | SPI2_SCK/I
2S2_CK | I2S3_MCK | - | USART6_
RX | - | - | - | SDIO_
D7 | - | - | EVEN
OUT | | PC8 | - | - | TIM3_CH3 | - | - | - | - | - | USART6_
CK | - | - | - | SDIO_
D0 | - | - | EVEN
OUT | | PC9 | MCO_2 | - | TIM3_CH4 | - | I2C3_SDA | I2S2_CKIN | - | - | | - | - | - | SDIO_
D1 | - | - | EVEN
OUT | | PC10 | - | - | - | - | - | - | SPI3_SCK/I2
S3_CK | - | - | - | - | - | SDIO_
D2 | - | - | EVEN OUT | | PC11 | - | - | - | - | - | I2S3ext_SD | SPI3_MISO | - | - | - | - | - | SDIO_
D3 | - | - | EVEN ® | | PC12 | - | - | - | - | - | - | SPI3_MOSI/I
2S3_SD | - | - | - | - | - | SDIO_
CK | - | - | EVEN -
OUT | | PC13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | DC14 |

Table 9. Alternate function mapping (continued)

AF00AF01AF02AF03AF04AF05AF06AF07AF08AF09AF10AF11AF12AF13AF14AF15
PortSYS_AFTIM1/TIM2TIM3/
TIM4/ TIM5		TIM9/
TIM10/
TIM11		I2C1/I2C2/
I2C3		SPI1/I2S1S
PI2/
I2S2/SPI3/
I2S3		SPI2/I2S2/
SPI3/
I2S3/SPI4/
I2S4/SPI5/
I2S5		SPI3/I2S3/
USART1/
USART2		USART6I2C2/
I2C3		OTG1_FSSDIO
PC15---ı----------ı-
PD0---1--ı-----ı-ıEVENT
OUT
PD1---1--1-------ıEVENT
OUT
PD2--TIM3_ETR---------SDIO_
CMD		EVENT
OUT
PD3-----SPI2_SCK/I
2S2_CK		USART2_
CTS		------1EVENT
OUT
PD4-------USART2_
RTS		-------EVENT
OUT
D PD5-------USART2_
TX		-------EVENT
OUT
PD6-----SPI3_MOSI
/I2S3_SD		-USART2_
RX		-------EVENT
OUT
PD7-------USART2_
CK		-------EVENT
OUT
PD8--------------ıEVENT
OUT
PD9--------------ıEVENT
OUT
PD10---------------EVENT
OUT
PD11---------------EVENT
OUT

Pinouts and pin description

| | Table 9. Alternate function mapping (continued) | |--------|-------------------------------------------------|--------------|-----------|---------------------|--------------------------|--------------------|------------------------------------------|---------------------------------------------------------|---------------------------------|--------|---------------|---------|------|------|------|------|--------------| | | | AF00 | AF01 | AF02 | AF03 | AF04 | AF05 | AF06 | AF07 | AF08 | AF09 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | | | Port | SYS_AF | TIM1/TIM2 | TIM3/
TIM4/ TIM5 | TIM9/
TIM10/
TIM11 | I2C1/I2C2/
I2C3 | SPI1/I2S1S
PI2/
I2S2/SPI3/
I2S3 | SPI2/I2S2/
SPI3/
I2S3/SPI4/
I2S4/SPI5/
I2S5 | SPI3/I2S3/
USART1/
USART2 | USART6 | I2C2/
I2C3 | OTG1_FS | | SDIO | | | PD12 | - | - | TIM4_CH1 | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | t D | PD13 | - | - | TIM4_CH2 | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | Port D | PD14 | - | - | TIM4_CH3 | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PD15 | - | - | TIM4_CH4 | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE0 | - | - | TIM4_ETR | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE1 | - | - | | - | - | - | - | - | - | - | - | - | ı | - | ı | EVENT
OUT | | | PE2 | TRACECL
K | - | - | - | - | SPI4_SCK/I
2S4_CK | SPI5_SCK/I2
S5_CK | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE3 | TRACED0 | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | EVENT
OUT | | | PE4 | TRACED1 | - | - | - | - | SPI4_NSS/I
2S4_WS | SPI5_NSS/I2
S5_WS | - | - | - | - | - | - | - | - | EVENT
OUT | | Port E | PE5 | TRACED2 | - | - | TIM9_CH1 | - | SPI4_MISO | SPI5_MISO | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE6 | TRACED3 | - | - | TIM9_CH2 | - | SPI4_MOSI
/I2S4_SD | SPI5_MOSI/I
2S5_SD | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE7 | - | TIM1_ETR | - | - | - | - | - | - | - | - | - | - | - | - | ı | EVENT
OUT | | | PE8 | - | TIM1_CH1N | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT | | | PE9 | - | TIM1_CH1 | - | - | - | - | - | - | - | - | - | - | - | - | 1 | EVENT
OUT | | | PE10 | - | TIM1_CH2N | - | - | - | - | - | - | - | - | - | - | - | - | - | EVENT
OUT |

Table 9. Alternate function mapping (continued)

AF00AF01AF02AF03AF04AF05AF06AF07AF08AF09AF10AF11AF12AF13AF14AF15
PortSYS_AFTIM1/TIM2TIM3/
TIM4/ TIM5		TIM9/
TIM10/
TIM11		I2C1/I2C2/
I2C3		SPI1/I2S1S
PI2/
I2S2/SPI3/
I2S3		SPI2/I2S2/
SPI3/
I2S3/SPI4/
I2S4/SPI5/
I2S5		SPI3/I2S3/
USART1/
USART2		USART6I2C2/
I2C3		OTG1_FSSDIO
PE11-TIM1_CH2---SPI4_NSS/I
2S4_WS		SPI5_NSS/I2
S5_WS		--------EVENT
OUT
PE12-TIM1_CH3N---SPI4_SCK/I
2S4_CK		SPI5_SCK/I2
S5_CK		--------EVENT
OUT
1
(		PE13-TIM1_CH3---SPI4_MISOSPI5_MISO--------EVENT
OUT
PE14-TIM1_CH4---SPI4_MOSI
/I2S4_SD		SPI5_MOSI/I
2S5_SD		--------EVENT
OUT
PE15-TIM1_BKIN-------------EVENT
OUT
-PH0----------------
ĊPH1-_--------------

cID026289 Rev

Electrical Characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at $T_A = 25$ °C and $T_A = T_A$ max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean $\pm 3 \sigma$ ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on $T_A$ = 25 °C, $V_{DD}$ = 3.3 V (for the 1.7 V $\leq$ VDD $\leq$ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean $\pm 2 \sigma$ ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 15.

MCU pin

Figure 15. Pin loading conditions

MS19011V2

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 16.

Figure 16. Input voltage measurement

6.1.6 Power supply scheme

VBA7 Backup circuitry VRAT = (OSC32K.RTC. Power 1.65 to 3.6V switch Wakeup logic Backup registers) 10 GPIOs Logic VCAP 1 Kernel logic VCAP (CPU, digital & RAM) $2 \times 2.2 ,\mu\text{F}$ or $1 \times 4.7 ,\mu\text{F}$ VDD VDD Voltage 1/2/...4/5 regulator 6 × 100 nF VSS + 1 × 4.7 µF 1/2/...4/5 Flash memory BYPASS REG Reset PDR ON controller VDD VDDA VREF VREF+ Analog: 100 nF 100 nF VREF ADC RCs, + 1 µF PLL VSSA MS31488V1

Figure 17. Power supply scheme

    1. To connect PDR_ON pin, refer to Section 3.15: Power supply supervisor.
    1. The 4.7 $\mu F$ ceramic capacitor must be connected to one of the $V_{DD}$ pin.
    1. VCAP_2 pad is only available on LQFP100 and UFBGA100 packages.
    1. $V_{DDA}=V_{DD}$ and $V_{SSA}=V_{SS}$ .

Caution:

Each power supply pair (for example $V_{DD}/V_{SS}$ , $V_{DDA}/V_{SSA}$ ) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

6.1.7 Current consumption measurement

AI 6"!4 6$$ 6$$! ) $$?6"!4 ) $$

Figure 18. Current consumption measurement scheme

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

SymbolRatingsMinMaxUnit
VDD–VSSExternal main supply voltage (including VDDA, VDD and
(1)
VBAT)		–0.34.0
Input voltage on FT pins(2)VSS–0.3VDD+4.0V
VINInput voltage on any other pinVSS–0.34.0
Input voltage for BOOT0VSS9.0
ΔVDDxVariations between different VDD power pins-50mV
VSSX −VSSVariations between all the different ground pins-50
VESD(HBM)Electrostatic discharge voltage (human body model)see Section 6.3.14:
Absolute maximum
ratings (electrical
sensitivity)
Table 11. Voltage characteristics

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current.

Table 12. Current characteristics

SymbolRatingsMax.Unit
ΣIVDDTotal current into sum of all VDD_x power lines (source)(1)160
Σ IVSSTotal current out of sum of all VSS_x ground lines (sink)(1)-160
IVDDMaximum current into each VDD_x power line (source)(1)100
IVSSMaximum current out of each VSS_x ground line (sink)(1)-100
Output current sunk by any I/O and control pin25
IIOOutput current sourced by any I/O and control pin-25mA
Total output current sunk by sum of all I/O and control pins (2)120
ΣIIOTotal output current sourced by sum of all I/Os and control pins(2)-120
Injected current on FT pins (4)–5/+0
IINJ(PIN) (3)Injected current on NRST and B pins (4)
ΣIINJ(PIN)Total injected current (sum of all I/O and control pins)(5)±25
    1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.
  • 2. This current consumption must be correctly distributed over all I/Os and control pins.
    1. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
    1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
    1. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

SymbolRatingsValueUnit
TSTGStorage temperature range–65 to +150
TJMaximum junction temperature125
TLEADMaximum lead temperature during soldering
(WLCSP49, LQFP64/100, UFQFPN48,
UFBGA100)		see note (1)°C

1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011).

Thermal Information

The maximum chip junction temperature (TJmax) must never exceed the values given in Table 12: General operating conditions on page 43.

The maximum chip-junction temperature, TJ max., in degrees Celsius, may be calculated using the following equation:

TJ max = TA max + (PD max x ΘJA)

Where:

  • TA max is the maximum ambient temperature in °C,
  • ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
  • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
  • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$$P_{I/O} \max = \sum (V_{OL} \times I_{OL}) + \sum ((V_{DD} - V_{OH}) \times I_{OH}),$$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

7.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.

Get structured datasheet data via API

Get started free