STM32F411XC/XE

Part: STM32F411xC / STM32F411xE (ordered as STM32F411CEU6) — STMicroelectronics

Type: ARM Cortex-M4 32-bit MCU with FPU

Description: 32-bit ARM Cortex-M4 MCU with FPU at up to 100 MHz (125 DMIPS), with up to 512 KB Flash, 128 KB SRAM, USB OTG FS, 1×12-bit 2.4 MSPS ADC and a 1.7–3.6 V supply.

Operating Conditions:

• Supply voltage: 1.7–3.6 V (VDD; 1.7 V minimum requires an external power supply supervisor)
• Operating temperature: -40 to 85 °C (6 suffix, max power dissipation; suffix-dependent, 7 suffix is -40 to 105 °C; low power dissipation state extends the ranges to 105 °C / 125 °C)
• Max HCLK: 100 MHz (Power Scale 1); 84 MHz (Scale 2); 64 MHz (Scale 3)
• VDDA: 1.7–2.4 V (ADC limited to 1.2 Msamples/s); 2.4–3.6 V (ADC up to 2.4 Msamples/s)
• VBAT: 1.65–3.6 V

Absolute Maximum Ratings:

• Max supply voltage (VDD–VSS): 4.0 V (min -0.3 V)
• Input voltage on FT pins: VDD + 4.0 V max; on other pins: 4.0 V max; BOOT0: 9.0 V max
• Max current per VDD/VSS line: 100 mA / -100 mA
• Total current into all VDD lines: 160 mA; out of all VSS lines: -160 mA
• Output current per I/O pin: 25 mA sunk / -25 mA sourced
• Total I/O output current: 120 mA sunk / -120 mA sourced
• Storage temperature: -65 to +150 °C
• Max junction temperature: 125 °C

Key Specs:

• Core clock (fHCLK): up to 100 MHz (Scale 1); APB1 up to 50 MHz, APB2 up to 100 MHz
• Operating supply (VDD): 1.7–3.6 V
• Junction temperature range: -40 to 105 °C (6 suffix), -40 to 125 °C (7 suffix)
• Input voltage on RST and FT pins: up to 5.5 V (2 V ≤ VDD ≤ 3.6 V); 5.2 V (VDD ≤ 2 V)
• Regulator ON, internal 1.2 V rail (V12) at Scale 1: 1.26–1.38 V (typ 1.32 V)
• Run mode: 100 μA/MHz (peripherals off)
• Stop mode: 42 μA typ at 25 °C (65 μA max at 25 °C); Standby: 2.4 μA at 25 °C / 1.7 V without RTC
• VBAT supply for RTC: 1 μA at 25 °C

Features:

• Cortex-M4 core with FPU, MPU, DSP instructions and ART Accelerator for 0-wait-state Flash execution
• Up to 512 KB Flash and 128 KB SRAM
• Batch Acquisition Mode (BAM) for low-power sensor data collection
• 1×12-bit, 2.4 MSPS ADC with up to 16 channels
• 16-stream DMA with FIFOs and burst support
• Up to 11 timers (six 16-bit, two 32-bit, two watchdogs, SysTick)
• Up to 13 communication interfaces: 3× I2C, 3× USART, 5× SPI/I2S, SDIO, USB 2.0 OTG FS with on-chip PHY
• Up to 81 I/Os with interrupt capability, up to 77 5 V-tolerant
• 4–26 MHz crystal oscillator, internal 16 MHz RC, 32 kHz RTC oscillator, internal 32 kHz RC
• POR, PDR, PVD and BOR supervisors
• SWD and JTAG debug, Cortex-M4 Embedded Trace Macrocell
• CRC unit, 96-bit unique ID, RTC with hardware calendar
• ECOPACK 2 packages

Applications:

• Sensor hub applications
• Low-power batch data acquisition
• USB OTG full-speed connected devices
• Audio applications using I2S

Package:

• WLCSP49 (3.034 × 3.22 mm, 0.4 mm pitch)
• UFQFPN48 (7 × 7 mm, 0.5 mm pitch)
• LQFP64 (10 × 10 mm)
• LQFP100 (14 × 14 mm)
• UFBGA100 (7 × 7 mm, 0.5 mm pitch)

• Dynamic Efficiency Line with BAM (Batch Acquisition Mode)
• Core: ARM ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit,
• 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -up to 512 Kbytes of Flash memory
• -128 Kbytes of SRAM
• Clock, reset and supply management
• -1.7 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Power consumption
• -Run: 100 μA/MHz (peripheral off)
• -Stop (Flash in Stop mode, fast wakeup time): 42 μA Typ @ 25C; 65 μA max @25 °C
• -Stop (Flash in Deep power down mode, fast wakeup time): down to 10 μA @ 25 °C; 30 μA max @25 °C
• -Standby: 2.4 μA @25 °C / 1.7 V without RTC; 12 μA @85 °C @1.7 V
• -VBAT supply for RTC: 1 μA @25 °C
• 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
• General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
• Up to 11 timers: up to six 16-bit, two 32-bit timers up to 100 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog

November 2014

DocID026289 Rev 3

Figure 9. STM32F411xC/xE WLCSP49 pinout

1. The above figure shows the package bump side.

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Figure 10. STM32F411xC/xE UFQFPN48 pinout

1. The above figure shows the package top view.

Figure 11. STM32F411xC/xE LQFP64 pinout

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Figure 12. STM32F411xC/xE LQFP100 pinout

1. The above figure shows the package top view.

Figure 13. STM32F411xC/xE UFBGA100 pinout

1. This figure shows the package top view

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Table 7. Legend/abbreviations used in the pinout table

Table 8. STM32F411xC/xE pin definitions

Table 8. STM32F411xC/xE pin definitions

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1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

• These I/Os must not be used as a current source (e.g. to drive an LED).
• The speed should not exceed 2 MHz with a maximum load of 30 pF.

1. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F411xx reference manual.
2. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
3. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low)

The definition and values of input/output AC characteristics are given in Figure 31 and Table 55 , respectively.

Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .

Table 55. I/O AC characteristics (1)(2)

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1. For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.

Figure 31. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 11. Voltage characteristics

Table 12. Current characteristics

1. This current consumption must be correctly distributed over all I/Os and control pins.

2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics .

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

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The maximum chip junction temperature (T J max) must never exceed the values given in Table 12: General operating conditions on page 43 .

The maximum chip-junction temperature, T J max., in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (PD max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.