Part: STM32F411xC/xE — STMicroelectronics

Type: ARM Cortex-M4 MCU

Description: 32-bit ARM Cortex-M4 MCU with FPU, up to 100 MHz, 512 KB Flash, 128 KB SRAM, USB OTG FS, 1 ADC, and 13 communication interfaces.

Operating Conditions:

• Supply voltage: 1.7–3.6 V
• Operating temperature: -40 to +85 °C (suffix-dependent — see Table 14 for grade-specific ranges)
• Max HCLK frequency: 100 MHz (Power Scale1)
• Analog operating voltage (ADC limited to 2.4 MSPS): 2.4–3.6 V

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max continuous current: 160 mA (Total current into sum of all VDD_x power lines)
• Max junction/storage temperature: 125 °C (Junction), 150 °C (Storage)

Key Specs:

• Core: ARM 32-bit Cortex-M4 CPU with FPU
• Max CPU frequency: 100 MHz
• Flash memory: up to 512 Kbytes
• SRAM: 128 Kbytes
• ADC: 1x 12-bit, 2.4 MSPS, up to 16 channels
• I/O ports: Up to 81 with interrupt capability, up to 77 5 V-tolerant
• Run mode current: 100 μA/MHz (peripheral off)
• Stop mode current: 42 μA Typ @ 25°C (Flash in Stop mode)
• Standby mode current: 2.4 μA @25 °C / 1.7 V without RTC

Features:

• Adaptive real-time accelerator (ART Accelerator™)
• Batch Acquisition Mode (BAM)
• Memory protection unit
• Up to 13 communication interfaces (I2C, USART, SPI/I2S, SDIO, USB OTG FS)
• General-purpose DMA: 16-stream controllers
• Up to 11 timers (16-bit, 32-bit, watchdog, SysTick)
• CRC calculation unit
• 96-bit unique ID
• RTC with subsecond accuracy and hardware calendar

Applications:

Package:

• WLCSP49 (3.034 x 3.22 mm, 0.4mm pitch)
• UFQFPN48 (7 x 7 mm, 0.5 mm pitch)
• LQFP64 (10 x 10 mm, 64-pin)
• LQFP100 (14 x 14 mm, 100-pin)
• UFBGA100 (7 x 7 mm, 0.5 mm pitch)

• Dynamic Efficiency Line with BAM (Batch Acquisition Mode)
• Core: ARM ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit,
• 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -up to 512 Kbytes of Flash memory
• -128 Kbytes of SRAM
• Clock, reset and supply management
• -1.7 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Power consumption
• -Run: 100 μA/MHz (peripheral off)
• -Stop (Flash in Stop mode, fast wakeup time): 42 μA Typ @ 25C; 65 μA max @25 °C
• -Stop (Flash in Deep power down mode, fast wakeup time): down to 10 μA @ 25 °C; 30 μA max @25 °C
• -Standby: 2.4 μA @25 °C / 1.7 V without RTC; 12 μA @85 °C @1.7 V
• -VBAT supply for RTC: 1 μA @25 °C
• 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
• General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
• Up to 11 timers: up to six 16-bit, two 32-bit timers up to 100 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog

November 2014

DocID026289 Rev 3

STM32F411VCT6 – LQFP100 Pinout

Pin	Name	Type	I/O Structure	Description / Alternate Functions
1	VBAT	S	-	Battery supply
2	PC13	I/O	TC	RTC_TAMP1 / RTC_TS / RTC_OUT / RTC_OUT2
3	PC14-OSC32_IN	I/O	TC	OSC32_IN
4	PC15-OSC32_OUT	I/O	TC	OSC32_OUT
5	PH0-OSC_IN	I/O	TC	OSC_IN
6	PH1-OSC_OUT	I/O	TC	OSC_OUT
7	NRST	I	NRST	Reset pin (active low)
8	PC0	I/O	TC	ADC1_10
9	PC1	I/O	TC	ADC1_11
10	PC2	I/O	TC	SPI2_MISO / I2S2ext_SD, ADC1_12
11	PC3	I/O	TC	SPI2_MOSI / I2S2_SD, ADC1_13
12	PA0-WKUP	I/O	TC	TIM2_CH1 / TIM2_ETR, TIM5_CH1, USART2_CTS, ADC1_0, WKUP1
13	PA1	I/O	FT	TIM2_CH2, TIM5_CH2, SPI4_MOSI / I2S4_SD, USART2_RTS, ADC1_1
14	PA2	I/O	FT	TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, ADC1_2
15	PA3	I/O	FT	TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, ADC1_3
16	VSS	S	-	Ground
17	VDD	S	-	Supply voltage
18	PA4	I/O	TC	SPI1_NSS / I2S1_WS, SPI3_NSS / I2S3_WS, USART2_CK, ADC1_4
19	PA5	I/O	TC	TIM2_CH1 / TIM2_ETR, SPI1_SCK / I2S1_CK, ADC1_5
20	PA6	I/O	FT	TIM1_BKIN, TIM3_CH1, SPI1_MISO, I2S2_MCK, SDIO_CMD, ADC1_6
21	PA7	I/O	FT	TIM1_CH1N, TIM3_CH2, SPI1_MOSI / I2S1_SD, ADC1_7
22	PC4	I/O	FT	ADC1_14
23	PC5	I/O	FT	ADC1_15
24	PB0	I/O	FT	TIM1_CH2N, TIM3_CH3, SPI5_SCK / I2S5_CK, ADC1_8
25	PB1	I/O	FT	TIM1_CH3N, TIM3_CH4, SPI5_NSS / I2S5_WS, ADC1_9
26	PB2	I/O	FT	BOOT1
27	PE7	I/O	FT	TIM1_ETR
28	PE8	I/O	FT	TIM1_CH1N
29	PE9	I/O	FT	TIM1_CH1
30	PE10	I/O	FT	TIM1_CH2N
31	PE11	I/O	FT	TIM1_CH2, SPI4_NSS / I2S4_WS, SPI5_NSS / I2S5_WS
32	PE12	I/O	FT	TIM1_CH3N, SPI4_SCK / I2S4_CK, SPI5_SCK / I2S5_CK
33	PE13	I/O	FT	TIM1_CH3, SPI4_MISO, SPI5_MISO
34	PE14	I/O	FT	TIM1_CH4, SPI4_MOSI / I2S4_SD, SPI5_MOSI / I2S5_SD
35	PE15	I/O	FT	TIM1_BKIN
36	PB10	I/O	TC	TIM2_CH3, I2C2_SCL, SPI2_SCK / I2S2_CK, I2S3_MCK, SDIO_D7
37	PB11	I/O	TC	TIM2_CH4, I2C2_SDA, I2S2_CKIN
38	BYPASS_REG	S	-	Regulator bypass capacitor
39	VSS	S	-	Ground
40	VDD	S	-	Supply voltage
41	PB12	I/O	TC	TIM1_BKIN, I2C2_SMBA, SPI2_NSS / I2S2_WS, SPI4_NSS / I2S4_WS, SPI3_SCK / I2S3_CK
42	PB13	I/O	TC	TIM1_CH1N, SPI2_SCK / I2S2_CK, SPI4_SCK / I2S4_CK
43	PB14	I/O	TC	TIM1_CH2N, SPI2_MISO, I2S2ext_SD, SDIO_D6
44	PB15	I/O	TC	RTC_50Hz, TIM1_CH3N, SPI2_MOSI / I2S2_SD, SDIO_CK
45	PD8	I/O	TC	USART3_TX
46	PD9	I/O	TC	USART3_RX
47	PD10	I/O	TC	-
48	PD11	I/O	TC	-
49	PD12	I/O	TC	TIM4_CH1
50	PD13	I/O	TC	TIM4_CH2
51	PD14	I/O	TC	TIM4_CH3
52	PD15	I/O	TC	TIM4_CH4
53	PC6	I/O	TC	TIM3_CH1, I2S2_MCK, USART6_TX, SDIO_D6
54	PC7	I/O	TC	TIM3_CH2, SPI2_SCK / I2S2_CK, I2S3_MCK, USART6_RX, SDIO_D7
55	PC8	I/O	TC	TIM3_CH3, USART6_CK, SDIO_D0
56	PC9	I/O	TC	TIM3_CH4, I2C3_SDA, I2S2_CKIN, SDIO_D1
57	PA8	I/O	TC	TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF, SDIO_D1
58	PA9	I/O	TC	TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS, SDIO_D2
59	PA10	I/O	TC	TIM1_CH3, USART1_RX, USB_FS_ID
60	PA11	I/O	TC	TIM1_CH4, USART1_CTS, USART6_TX, USB_FS_DM
61	PA12	I/O	TC	TIM1_ETR, USART1_RTS, USART6_RX, USB_FS_DP
62	PA13	I/O	TC	JTMS-SWDIO
63	VSS	S	-	Ground
64	VDD	S	-	Supply voltage
65	PA14	I/O	TC	JTCK-SWCLK
66	PA15	I/O	TC	JTDI, TIM2_CH1 / TIM2_ETR, SPI1_NSS / I2S1_WS, SPI3_NSS / I2S3_WS, USART1_TX
67	PC10	I/O	TC	SPI3_SCK / I2S3_CK, USART3_TX, SDIO_D2
68	PC11	I/O	TC	I2S3ext_SD, SPI3_MISO, USART3_RX, SDIO_D3
69	PC12	I/O	TC	SPI3_MOSI / I2S3_SD, USART3_CK, SDIO_CK
70	PD0	I/O	TC	-
71	PD1	I/O	TC	-
72	PD2	I/O	TC	TIM3_ETR, USART3_RX, SDIO_CMD
73	PD3	I/O	TC	SPI2_SCK / I2S2_CK, USART2_CTS
74	PD4	I/O	TC	USART2_RTS
75	PD5	I/O	TC	USART2_TX
76	PD6	I/O	TC	SPI3_MOSI / I2S3_SD, USART2_RX
77	PD7	I/O	TC	USART2_CK
78	PB3	I/O	TC	JTDO-SWO, TIM2_CH2, SPI1_SCK / I2S1_CK, SPI3_SCK / I2S3_CK, USART1_RX, I2C2_SDA, SDIO_D0
79	PB4	I/O	TC	JTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, SDIO_D0
80	PB5	I/O	TC	TIM3_CH2, I2C1_SMBA, SPI1_MOSI / I2S1_SD, SPI3_MOSI / I2S3_SD, SDIO_D3
81	PB6	I/O	TC	TIM4_CH1, I2C1_SCL, USART1_TX
82	PB7	I/O	TC	TIM4_CH2, I2C1_SDA, USART1_RX, SDIO_D0
83	BOOT0	I	B	Boot configuration pin
84	PB8	I/O	TC	TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI / I2S5_SD, I2C3_SDA, SDIO_D4
85	PB9	I/O	TC	TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS / I2S2_WS, I2C2_SDA, SDIO_D5
86	VSS	S	-	Ground
87	VDD	S	-	Supply voltage
88	PE0	I/O	TC	TIM4_ETR
89	PE1	I/O	TC	-
90	PE2	I/O	TC	TRACECLK, SPI4_SCK / I2S4_CK, SPI5_SCK / I2S5_CK
91	PE3	I/O	TC	TRACED0
92	PE4	I/O	TC	TRACED1, SPI4_NSS / I2S4_WS, SPI5_NSS / I2S5_WS
93	PE5	I/O	TC	TRACED2, TIM9_CH1, SPI4_MISO, SPI5_MISO
94	PE6	I/O	TC	TRACED3, TIM9_CH2, SPI4_MOSI / I2S4_SD, SPI5_MOSI / I2S5_SD
95	VSS	S	-	Ground
96	VDD	S	-	Supply voltage
97	PD10	I/O	TC	-
98	PD11	I/O	TC	-
99	PD12	I/O	TC	TIM4_CH1
100	PD13	I/O	TC	TIM4_CH2

Notes

• PC13, PC14, PC15: Limited output capability (3 mA max sink current). Speed limited to 2 MHz with max 30 pF load. Not suitable as current source (e.g., LED drive).
• FT pins: 5V-tolerant except in analog or oscillator mode (PC14, PC15, PH0, PH1).
• PA0-WKUP: In UFBGA100 with BYPASS_REG tied to VDD, PA0 functions as internal Reset (active low).
• BOOT1 (PB2): Selects boot source during reset.
• All I/Os are floating inputs after reset unless otherwise specified.
• Alternate functions selected via GPIOx_AFR registers; additional functions via peripheral registers.

The definition and values of input/output AC characteristics are given in Figure 31 and Table 55 , respectively.

Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .

Table 55. I/O AC characteristics (1)(2)

OSPEEDRy [1:0] bit value (1)	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
00	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 2.70 V	-	-	4	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 1.7 V	-	-	2	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	8	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	4	MHz
00	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD = 1.7 V to 3.6 V	-	-	100	ns
01	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 2.70 V	-	-	25	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 1.7 V	-	-	12.5	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	50	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	20	MHz
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD ≥ 2.7 V	-	-	10	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD ≥ 1.7 V	-	-	20	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	6	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	10	ns
10	f max(IO)out	Maximum frequency (3)	C L = 40 pF, V DD ≥ 2.70 V	-	-	50 (4)	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 40 pF, V DD ≥ 1.7 V	-	-	25	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	100 (4)	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	50 (4)	MHz
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 40 pF, V DD ≥ 2.70 V	-	-	6	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 40 pF, V DD ≥ 1.7 V	-	-	10	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	4	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	6	ns
11	t f(IO)out / t	max(IO)out Maximum frequency (3)	C L = 30 pF, V DD ≥ 2.70 V	-	-	100 (4)
11	t f(IO)out / t	max(IO)out Maximum frequency (3)	C L = 30 pF, V DD ≥ 1.7 V	-	-	50 (4)	MHz
11	t f(IO)out / t	Output high to low level fall time and output low to high level rise time	C L = 30 pF, V DD ≥ 2.70 V C L = 30 pF, V DD ≥ 1.7 V	- -	- -	4 6
11	r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	2.5	ns
11	t f(IO)out / t	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	4
-	t EXTIpw	Pulse width of external signals detected by the EXTI controller		10	-	-	ns

119

1. For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.

Figure 31. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 11. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
V DD -V SS	External main supply voltage (including V DDA ,V DD and V BAT ) (1)	-0.3	4.0	V
V IN	Input voltage on FT pins (2)	V SS -0.3	V DD +4.0	V
V IN	Input voltage on any other pin	V SS -0.3	4.0	V
V IN	Input voltage for BOOT0	V SS	9.0	V
\	∆ V DDx \		Variations between different V DD power pins	-
\	V SSX - V SS \		Variations between all the different ground pins	-
V ESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 6.3.14: Absolute maximum ratings (electrical	see Section 6.3.14: Absolute maximum ratings (electrical

Table 12. Current characteristics

Table 12. Current characteristics

Symbol	Ratings	Max.	Unit
Σ I VDD	Total current into sum of all V DD_x power lines (source) (1)	160	mA
Σ I VSS	Total current out of sum of all V SS_x ground lines (sink) (1)	-160	mA
I VDD	Maximum current into each V DD_x power line (source) (1)	100	mA
I VSS	Maximum current out of each V SS_x ground line (sink) (1)	-100	mA
I IO	Output current sunk by any I/O and control pin	25	mA
I IO	Output current sourced by any I/O and control pin	-25	mA
Σ I IO	Total output current sunk by sum of all I/O and control pins (2)	120	mA
Σ I IO	Total output current sourced by sum of all I/Os and control pins (2)	-120	mA
I INJ(PIN) (3)	Injected current on FT pins (4)	-5/+0	mA
I INJ(PIN) (3)	Injected current on NRST and B pins (4)	-5/+0	mA
Σ I INJ(PIN)	Total injected current (sum of all I/O and control pins) (5)	±25	mA

1. This current consumption must be correctly distributed over all I/Os and control pins.

2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics .

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	125	°C
T LEAD	Maximum lead temperature during soldering (WLCSP49, LQFP64/100, UFQFPN48, UFBGA100)	see note (1)	°C

119

The maximum chip junction temperature (T J max) must never exceed the values given in Table 12: General operating conditions on page 43 .

The maximum chip-junction temperature, T J max., in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (PD max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.