STM32F411VET6

Part: STM32F411xC/xE — STMicroelectronics

Type: ARM Cortex-M4 MCU

Description: 32-bit ARM Cortex-M4 MCU with FPU, up to 100 MHz, 512 KB Flash, 128 KB SRAM, USB OTG FS, 1 ADC, and 13 communication interfaces.

Operating Conditions:

• Supply voltage: 1.7–3.6 V
• Operating temperature: -40 to +85 °C (suffix-dependent — see Table 14 for grade-specific ranges)
• Max HCLK frequency: 100 MHz (Power Scale1)
• Analog operating voltage (ADC limited to 2.4 MSPS): 2.4–3.6 V

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max continuous current: 160 mA (Total current into sum of all VDD_x power lines)
• Max junction/storage temperature: 125 °C (Junction), 150 °C (Storage)

Key Specs:

• Core: ARM 32-bit Cortex-M4 CPU with FPU
• Max CPU frequency: 100 MHz
• Flash memory: up to 512 Kbytes
• SRAM: 128 Kbytes
• ADC: 1x 12-bit, 2.4 MSPS, up to 16 channels
• I/O ports: Up to 81 with interrupt capability, up to 77 5 V-tolerant
• Run mode current: 100 μA/MHz (peripheral off)
• Stop mode current: 42 μA Typ @ 25°C (Flash in Stop mode)
• Standby mode current: 2.4 μA @25 °C / 1.7 V without RTC

Features:

• Adaptive real-time accelerator (ART Accelerator™)
• Batch Acquisition Mode (BAM)
• Memory protection unit
• Up to 13 communication interfaces (I2C, USART, SPI/I2S, SDIO, USB OTG FS)
• General-purpose DMA: 16-stream controllers
• Up to 11 timers (16-bit, 32-bit, watchdog, SysTick)
• CRC calculation unit
• 96-bit unique ID
• RTC with subsecond accuracy and hardware calendar

Applications:

Package:

• WLCSP49 (3.034 x 3.22 mm, 0.4mm pitch)
• UFQFPN48 (7 x 7 mm, 0.5 mm pitch)
• LQFP64 (10 x 10 mm, 64-pin)
• LQFP100 (14 x 14 mm, 100-pin)
• UFBGA100 (7 x 7 mm, 0.5 mm pitch)

• Dynamic Efficiency Line with BAM (Batch Acquisition Mode)
• Core: ARM ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 100 MHz, memory protection unit,
• 125 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -up to 512 Kbytes of Flash memory
• -128 Kbytes of SRAM
• Clock, reset and supply management
• -1.7 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Power consumption
• -Run: 100 μA/MHz (peripheral off)
• -Stop (Flash in Stop mode, fast wakeup time): 42 μA Typ @ 25C; 65 μA max @25 °C
• -Stop (Flash in Deep power down mode, fast wakeup time): down to 10 μA @ 25 °C; 30 μA max @25 °C
• -Standby: 2.4 μA @25 °C / 1.7 V without RTC; 12 μA @85 °C @1.7 V
• -VBAT supply for RTC: 1 μA @25 °C
• 1×12-bit, 2.4 MSPS A/D converter: up to 16 channels
• General-purpose DMA: 16-stream DMA controllers with FIFOs and burst support
• Up to 11 timers: up to six 16-bit, two 32-bit timers up to 100 MHz, each with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, two watchdog

November 2014

DocID026289 Rev 3

Figure 9. STM32F411xC/xE WLCSP49 pinout

1. The above figure shows the package bump side.

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Figure 10. STM32F411xC/xE UFQFPN48 pinout

1. The above figure shows the package top view.

Figure 11. STM32F411xC/xE LQFP64 pinout

Figure 11. STM32F411xC/xE LQFP64 pinout

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Figure 12. STM32F411xC/xE LQFP100 pinout

1. The above figure shows the package top view.

Figure 13. STM32F411xC/xE UFBGA100 pinout

Figure 13. STM32F411xC/xE UFBGA100 pinout

1. This figure shows the package top view

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Table 7. Legend/abbreviations used in the pinout table

Name	Abbreviation	Definition
Pin name	Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name	Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
Pin type	S	Supply pin
Pin type	I	Input only pin
Pin type	I/O	Input/ output pin
I/O structure	FT	5 V tolerant I/O
I/O structure	TC	Standard 3.3 V I/O
I/O structure	B	Dedicated BOOT0 pin
I/O structure	NRST	Bidirectional reset pin with embedded weak pull-up resistor
Notes	Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset	Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions	Functions selected through GPIOx_AFR registers	Functions selected through GPIOx_AFR registers
Additional functions	Functions directly selected/enabled through peripheral registers	Functions directly selected/enabled through peripheral registers

Table 8. STM32F411xC/xE pin definitions

Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L
-	-	-	1	B2
-	-	-	2	A1
-	-	-	3	B1
-	-	-	4	C2

Table 8. STM32F411xC/xE pin definitions

Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L
-	-	-	5	D2
-	-	-	-	D3
-	-	-	-	C4
1	1	B7	6	E2
2	2	D5	7	C1
3	3	C7	8	D1
4	4	C6	9	E1
-	-	-	10	F2
-	-	-	11	G2
5	5	D7	12	F1
6	6	D6	13	G1
7	7	E7	14	H2
-	8	-	15	H1
-	9	-	16	J2
-	10	-	17	J3
-	11	-	18	K2
-	-	-	19	-
8	12	E6	20	J1
-	-	-	-	K1
9	13	F7	21	L1
-	-	-	22	M1

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Pin number	Pin number	Pin number	Pin number	Pin number						Additional
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L	Pin name (function after reset) (1)	Pin type	I/O structure	Notes	Alternate functions	functions
10	14	F6	23	L2	PA0-WKUP	I/O	TC	(5)	TIM2_CH1/TIM2_ET, TIM5_CH1, USART2_CTS, EVENTOUT	ADC1_0, WKUP1
11	15	G7	24	M2	PA1	I/O	FT	-	TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, EVENTOUT	ADC1_1
12	16	E5	25	K3	PA2	I/O	FT	-	TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, EVENTOUT	ADC1_2
13	17	E4	26	L3	PA3	I/O	FT	-	TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, EVENTOUT	ADC1_3
-	18	-	27	-	VSS	S	-	-	-	-
-	-	-	-	E3	BYPASS_REG	S	-	-	-	-
-	19	-	28	-	VDD	I	FT	-	EVENTOUT	-
14	20	G6	29	M3	PA4	I/O	TC	-	SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT	ADC1_4
15	21	F5	30	K4	PA5	I/O	TC	-	TIM2_CH1/TIM2_ET, SPI1_SCK/I2S1_CK, EVENTOUT	ADC1_5
16	22	F4	31	L4	PA6	I/O	FT	-	TIM1_BKIN, TIM3_CH1, SPI1_MISO, I2S2_MCK, SDIO_CMD, EVENTOUT	ADC1_6
17	23	F3	32	M4	PA7	I/O	FT	-	TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SD, EVENTOUT	ADC1_7
Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L	Pin name (function after reset) (1)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	24	-	33	K5	PC4	I/O	FT	-	EVENTOUT	ADC1_14
-	25	-	34	L5	PC5	I/O	FT	-	EVENTOUT	ADC1_15
18	26	G5	35	M5	PB0	I/O	FT	-	TIM1_CH2N, TIM3_CH3, SPI5_SCK/I2S5_CK, EVENTOUT	ADC1_8
19	27	G4	36	M6	PB1	I/O	FT	-	TIM1_CH3N, TIM3_CH4, SPI5_NSS/I2S5_WS, EVENTOUT	ADC1_9
20	28	G3	37	L6	PB2	I/O	FT	-	EVENTOUT	BOOT1
-	-	-	38	M7	PE7	I/O	FT	-	TIM1_ETR, EVENTOUT	-
-	-	-	39	L7	PE8	I/O	FT	-	TIM1_CH1N, EVENTOUT	-
-	-	-	40	M8	PE9	I/O	FT	-	TIM1_CH1, EVENTOUT	-
-	-	-	41	L8	PE10	I/O	FT	-	TIM1_CH2N, EVENTOUT	-
-	-	-	42	M9	PE11	I/O	FT	-	TIM1_CH2, SPI4_NSS/I2S4_WS, SPI5_NSS/I2S5_WS, EVENTOUT	-
-	-	-	43	L9	PE12	I/O	FT	-	TIM1_CH3N, SPI4_SCK/I2S4_CK, SPI5_SCK/I2S5_CK, EVENTOUT	-
-	-	-	44	M10	PE13	I/O	FT	-	TIM1_CH3, SPI4_MISO, SPI5_MISO, EVENTOUT	-
-	-	-	45	M11	PE14	I/O	FT	-	TIM1_CH4, SPI4_MOSI/I2S4_SD, SPI5_MOSI/I2S5_SD, EVENTOUT	-
-	-	-	46	M12	PE15	I/O	FT	-	TIM1_BKIN, EVENTOUT	-

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Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L
21	29	E3	47	L10
-	-	-	-	K9
22	30	G2	48	L11
23	31	D3	49	F12
24	32	F2	50	G12
25	33	E2	51	L12
26	34	G1	52	K12
27	35	F1	53	K11
28	36	E1	54	K10
-	-	-	55	-
-	-	-	56	K8
-	-	-	57	J12
-	-	-	58	J11
-	-	-	59	J10
Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L
-	-	-	60	H12
-	-	-	61	H11
-	-	-	62	H10
-	37	-	63	E12
-	38	-	64	E11
-	39	-	65	E10
-	40	-	66	D12
29	41	D1	67	D11
30	42	D2	68	D10

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Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L
31	43	C2	69	C12
32	44	C1	70	B12
33	45	C3	71	A12
34	46	B3	72	A11
-	-	-	73	C11
35	47	B1	74	F11
36	48	B2	75	G11
37	49	A1	76	A10
38	50	A2	77	A9
-	51	-	78	B11
-	52	-	79	C10
-	53	-	80	B10
Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L
-	-	-	81	C9
-	-	-	82	B9
-	54	-	83	C8
-	-	-	84	B8
-	-	-	85	B7
-	-	-	86	A6
-	-	-	87	B6
-	-	-	88	A5
39	55	A3	89	A8
40	56	A4	90	A7
41	57	B4	91	C5
42	58	C4	92	B5

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Pin number	Pin number	Pin number	Pin number	Pin number
UQFN48	LQFP64	WLCSP49	LQFP100	UFBGA100L
43	59	D4	93	B4
44	60	A5	94	A4
45	61	B5	95	A3
46	62	C5	96	B3
-	-	-	97	C3
-	-	-	98	A2
47	63	A6	99	-
-	-	B6	-	H3
48	64	A7	100	-

1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

• These I/Os must not be used as a current source (e.g. to drive an LED).
• The speed should not exceed 2 MHz with a maximum load of 30 pF.

1. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F411xx reference manual.
2. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
3. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low)

The definition and values of input/output AC characteristics are given in Figure 31 and Table 55 , respectively.

Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .

Table 55. I/O AC characteristics (1)(2)

OSPEEDRy [1:0] bit value (1)	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
00	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 2.70 V	-	-	4	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 1.7 V	-	-	2	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	8	MHz
00	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	4	MHz
00	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD = 1.7 V to 3.6 V	-	-	100	ns
01	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 2.70 V	-	-	25	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 50 pF, V DD ≥ 1.7 V	-	-	12.5	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	50	MHz
01	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	20	MHz
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD ≥ 2.7 V	-	-	10	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 50 pF, V DD ≥ 1.7 V	-	-	20	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	6	ns
01	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	10	ns
10	f max(IO)out	Maximum frequency (3)	C L = 40 pF, V DD ≥ 2.70 V	-	-	50 (4)	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 40 pF, V DD ≥ 1.7 V	-	-	25	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 2.70 V	-	-	100 (4)	MHz
10	f max(IO)out	Maximum frequency (3)	C L = 10 pF, V DD ≥ 1.7 V	-	-	50 (4)	MHz
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 40 pF, V DD ≥ 2.70 V	-	-	6	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 40 pF, V DD ≥ 1.7 V	-	-	10	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	4	ns
10	t f(IO)out / t r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	6	ns
11	t f(IO)out / t	max(IO)out Maximum frequency (3)	C L = 30 pF, V DD ≥ 2.70 V	-	-	100 (4)
11	t f(IO)out / t	max(IO)out Maximum frequency (3)	C L = 30 pF, V DD ≥ 1.7 V	-	-	50 (4)	MHz
11	t f(IO)out / t	Output high to low level fall time and output low to high level rise time	C L = 30 pF, V DD ≥ 2.70 V C L = 30 pF, V DD ≥ 1.7 V	- -	- -	4 6
11	r(IO)out	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 2.70 V	-	-	2.5	ns
11	t f(IO)out / t	Output high to low level fall time and output low to high level rise time	C L = 10 pF, V DD ≥ 1.7 V	-	-	4
-	t EXTIpw	Pulse width of external signals detected by the EXTI controller		10	-	-	ns

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1. For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.

Figure 31. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 11. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
V DD -V SS	External main supply voltage (including V DDA ,V DD and V BAT ) (1)	-0.3	4.0	V
V IN	Input voltage on FT pins (2)	V SS -0.3	V DD +4.0	V
V IN	Input voltage on any other pin	V SS -0.3	4.0	V
V IN	Input voltage for BOOT0	V SS	9.0	V
\	∆ V DDx \		Variations between different V DD power pins	-
\	V SSX - V SS \		Variations between all the different ground pins	-
V ESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 6.3.14: Absolute maximum ratings (electrical	see Section 6.3.14: Absolute maximum ratings (electrical

Table 12. Current characteristics

Table 12. Current characteristics

Symbol	Ratings	Max.	Unit
Σ I VDD	Total current into sum of all V DD_x power lines (source) (1)	160	mA
Σ I VSS	Total current out of sum of all V SS_x ground lines (sink) (1)	-160	mA
I VDD	Maximum current into each V DD_x power line (source) (1)	100	mA
I VSS	Maximum current out of each V SS_x ground line (sink) (1)	-100	mA
I IO	Output current sunk by any I/O and control pin	25	mA
I IO	Output current sourced by any I/O and control pin	-25	mA
Σ I IO	Total output current sunk by sum of all I/O and control pins (2)	120	mA
Σ I IO	Total output current sourced by sum of all I/Os and control pins (2)	-120	mA
I INJ(PIN) (3)	Injected current on FT pins (4)	-5/+0	mA
I INJ(PIN) (3)	Injected current on NRST and B pins (4)	-5/+0	mA
Σ I INJ(PIN)	Total injected current (sum of all I/O and control pins) (5)	±25	mA

1. This current consumption must be correctly distributed over all I/Os and control pins.

2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics .

3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

4. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	125	°C
T LEAD	Maximum lead temperature during soldering (WLCSP49, LQFP64/100, UFQFPN48, UFBGA100)	see note (1)	°C

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The maximum chip junction temperature (T J max) must never exceed the values given in Table 12: General operating conditions on page 43 .

The maximum chip-junction temperature, T J max., in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (PD max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.