STM32F405ZG

Part: STM32F407VGT6 (STM32F405xx/STM32F407xx family) — STMicroelectronics

Type: ARM Cortex-M4 32-bit MCU with FPU

Description: 32-bit Arm Cortex-M4 MCU with FPU at up to 168 MHz (210 DMIPS), up to 1 MB Flash and 192+4 KB SRAM, with USB OTG HS/FS, Ethernet, 3 ADCs and 17 timers.

Operating Conditions:

• Supply voltage: 1.8–3.6 V (VDD); VBAT 1.65–3.6 V
• Operating temperature: -40 to 85 °C (suffix 6; suffix 7 is -40 to 105 °C at maximum power dissipation)
• Max HCLK: 168 MHz (VOS = 1), 144 MHz (VOS = 0); APB1 42 MHz, APB2 84 MHz

Absolute Maximum Ratings:

• Max supply voltage (VDD–VSS): 4.0 V
• Max input voltage on five-volt tolerant pin: VDD + 4 V; on any other pin: 4.0 V
• Total current into VDD power lines: 240 mA; out of VSS lines: 240 mA
• Max current sunk or sourced by any I/O pin: 25 mA
• Max junction temperature: 125 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• VDD operating range: 1.8–3.6 V
• VDDA: 1.8–2.4 V (ADC limited to 1.2 Msamples), 2.4–3.6 V (ADC up to 1.4 Msamples); must be at the same potential as VDD
• VBAT backup supply: 1.65–3.6 V
• Max HCLK: 168 MHz (VOS = 1), 144 MHz (VOS = 0)
• Internal 1.2 V regulator output (VCAP): 1.20–1.32 V at 168 MHz, 1.08–1.20 V at 144 MHz
• Input voltage on RST and FT pins: up to 5.5 V (2 V ≤ VDD ≤ 3.6 V), 5.2 V (VDD ≤ 2 V)
• Power dissipation at TA = 85 °C (suffix 6): 435 mW (LQFP64), 465 mW (LQFP100), 500 mW (LQFP144), 526 mW (LQFP176), 513 mW (UFBGA176), 543 mW (WLCSP90)
• Junction temperature range: -40 to 105 °C (suffix 6), -40 to 125 °C (suffix 7)

Features:

• Arm Cortex-M4 with FPU, MPU, DSP instructions and ART Accelerator for 0-wait-state Flash execution
• Up to 1 MB Flash, up to 192+4 KB SRAM (including 64 KB CCM), 512 bytes OTP
• Flexible static memory controller (FSMC) for Compact Flash, SRAM, PSRAM, NOR and NAND
• 3×12-bit 2.4 MSPS ADCs (up to 24 channels), 2×12-bit DACs
• 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers
• Up to 15 communication interfaces: 3×I²C, 4 USARTs/2 UARTs, 3 SPIs (2 with I²S), 2×CAN, SDIO
• USB 2.0 OTG FS and USB 2.0 OTG HS/FS, 10/100 Ethernet MAC with IEEE 1588v2, 8- to 14-bit camera interface
• True random number generator, CRC unit, 96-bit unique ID, RTC with hardware calendar
• SWD/JTAG debug and Cortex-M4 Embedded Trace Macrocell
• Sleep, Stop and Standby low-power modes; VBAT supply for RTC and backup registers
• POR, PDR, PVD and BOR supervisors
• 4–26 MHz crystal oscillator, internal 16 MHz RC (1% accuracy), 32 kHz RTC oscillator
• Up to 140 I/O ports with interrupt capability, up to 138 5 V-tolerant I/Os

Applications:

Package:

• LQFP64 (10 × 10 mm)
• LQFP100 (14 × 14 mm)
• LQFP144 (20 × 20 mm)
• LQFP176 (24 × 24 mm)
• UFBGA176 (10 × 10 mm)
• WLCSP90 (4.223 × 3.969 mm)

• Includes ST state-of-the-art patented technology
• Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -Up to 1 Mbyte of flash memory
• -Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data RAM
• -512 bytes of OTP memory
• -Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
• LCD parallel interface, 8080/6800 modes
• Clock, reset, and supply management
• -1.8 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC (1% accuracy)
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Low-power operation
• -Sleep, Stop, and Standby modes
• -VBAT supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• -10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

DS8626 Rev 11

• 8- to 14-bit parallel camera interface up to 54 Mbytes/s
• True random number generator
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar
• All packages are ECOPACK2 compliant

Table 1. Device summary

Table 1. Device summary

Figure 12. STM32F40xxx LQFP64 pinout

Figure 13. STM32F40xxx LQFP100 pinout

1. The above figure shows the package top view.

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Figure 14. STM32F40xxx LQFP144 pinout

1. The above figure shows the package top view.

Figure 15. STM32F40xxx LQFP176 pinout

1. The above figure shows the package top view.

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The definition and values of input/output AC characteristics are given in Figure 37 and Table 50 , respectively.

Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .

Table 50. I/O AC characteristics (1)(2)

Table 50. I/O AC characteristics (1)(2)

Table 50. I/O AC characteristics (1)(2) (continued)

1. The maximum frequency is defined in Figure 37 .
2. For maximum frequencies above 50 MHz, the compensation cell should be used.

Figure 37. I/O AC characteristics definition

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Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 11. Voltage characteristics

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Table 12. Current characteristics

1. Positive injection is not possible on these I/Os. A negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
2. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
3. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.