STM32F407VGT6

STM32F405xx STM32F407xx

Manufacturer

STMicroelectronics

Overview

Part 1: Markdown Summary

Part: STM32F405xx STM32F407xx from STMicroelectronics

Type: Arm® Cortex®-M4 32b MCU+FPU

Key Specs:

  • CPU Frequency: up to 168 MHz
  • Flash Memory: Up to 1 Mbyte
  • SRAM: Up to 192+4 Kbytes
  • DMIPS: 210 DMIPS
  • Application Supply: 1.8 V to 3.6 V
  • ADC: 3×12-bit, 2.4 MSPS
  • DAC: 2×12-bit

Features:

  • Arm® 32-bit Cortex®-M4 CPU with FPU, ART Accelerator, MPU, DSP instructions
  • Up to 1 Mbyte of flash memory
  • Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM data RAM
  • 512 bytes of OTP memory
  • Flexible static memory controller (FSMC)
  • LCD parallel interface, 8080/6800 modes
  • Clock, reset, and supply management (POR, PDR, PVD, BOR, various oscillators)
  • Low-power operation (Sleep, Stop, Standby modes, VBAT supply for RTC)
  • 3×12-bit, 2.4 MSPS A/D converters (up to 24 channels, 7.2 MSPS in triple interleaved mode)
  • 2×12-bit D/A converters
  • 16-stream DMA controller with FIFOs and burst support
  • Up to 17 timers (twelve 16-bit, two 32-bit)
  • Serial wire debug (SWD) & JTAG interfaces, Cortex-M4 Embedded Trace Macrocell™
  • Up to 140 I/O ports with interrupt capability, up to 138 5 V-tolerant I/Os
  • Up to 15 communication interfaces (I2C, USART/UART, SPI, CAN, SDIO)
  • USB 2.0 full-speed device/host/OTG controller with on-chip PHY
  • USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
  • 10/100 Ethernet MAC with dedicated DMA, supports IEEE 1588v2 hardware, MII/RMII
  • 8- to 14-bit parallel camera interface up to 54 Mbytes/s
  • True random number generator
  • CRC calculation unit
  • 96-bit unique ID
  • RTC: subsecond accuracy, hardware calendar
  • All packages are ECOPACK2 compliant

Applications:

  • null

Package:

  • null

Features

  • Includes ST state-of-the-art patented technology
  • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
    • Up to 1 Mbyte of flash memory
    • Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM
    • 512 bytes of OTP memory
    • Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
  • LCD parallel interface, 8080/6800 modes
  • Clock, reset, and supply management
    • 1.8 V to 3.6 V application supply and I/Os
    • POR, PDR, PVD and BOR
    • 4-to-26 MHz crystal oscillator
    • Internal 16 MHz factory-trimmed RC (1% accuracy)
    • 32 kHz oscillator for RTC with calibration
    • Internal 32 kHz RC with calibration
  • Low-power operation
    • Sleep, Stop, and Standby modes
    • VBAT supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM
  • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
  • 2×12-bit D/A converters
  • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support

  • Up to 17 timers: up to twelve 16-bit and two 32 bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

  • Debug mode

    • Serial wire debug (SWD) & JTAG interfaces
    • Cortex-M4 Embedded Trace Macrocell™

  • Up to 140 I/O ports with interrupt capability

    • Up to 136 fast I/Os up to 84 MHz
    • Up to 138 5 V-tolerant I/Os

  • Up to 15 communication interfaces

    • Up to 3 × I2C interfaces (SMBus/PMBus)
    • Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)
    • Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock
    • 2 × CAN interfaces (2.0B Active)
    • SDIO interface

  • Advanced connectivity

    • USB 2.0 full-speed device/host/OTG controller with on-chip PHY
    • USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
    • 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

  • 8- to 14-bit parallel camera interface up to 54 Mbytes/s

  • True random number generator

  • • CRC calculation unit

  • 96-bit unique ID

  • RTC: subsecond accuracy, hardware calendar

  • All packages are ECOPACK2 compliant

Table 1. Device summary

ReferencePart number
STM32F405xxSTM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE
STM32F407xxSTM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE,
STM32F407IE

Pin Configuration

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 4948 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC14 PC15 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0_WKUP PA1 PA2 VDD PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD LQFP64 ai18493b PC13 PH0 PH1 VSS

Figure 12. STM32F40xxx LQFP64 pinout

  1. The above figure shows the package top view.

Figure 13. STM32F40xxx LQFP100 pinout

  1. The above figure shows the package top view.

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\ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \ 441 \$ PE2 d 1 108 | VDD 107 | VSS 106 | VCAP_2 PE3 🗆 2 PE4 🗆 3 PE5 4 105 PĂ T3 PE6 ☐ 5 104 🗖 PA 12 VBAT ☐ 6 103 PA11 PC13 ☐ 7 102 PA 10 PC14 🗆 8 101 PA9 PC15 🗖 9 100 PA8 PF0 ☐ 10 99 | PC9 98 | PC8 PF1 ☐ 11 PF2 ☐ 12 97 | PC7 PF3 13 96 PC6 PF4 🗖 14 95 | VDD 94 VSS 93 PG8 PF5 🗖 15 VSS □ 16 VDD □ 17 PF6 □ 18 92 🗖 PG7 91 □ PG6 LQFP144 PF7 🗖 19 90 | PG5 89 | PG4 88 | PG3 PF8 d 20 PF9 21 87 | PG2 PF10 d 22 PH0 🗖 23 86 PD15 PH1 🗖 24 85 | PD14 84 | VDD NRST 25 PC0 ☐ 26 83 ( \subseteq V_{SS} ) PC1 | 27 82 | PD13 PC2 ☐ 28 81 PD12 80 PD11 PC3 ☐ 29 79 □PD10 78 □PD9 77 □PD8 76 □PB15 VDD □ 30 VSSA VREF+□ 32 VDDA□ 33 PA0□ 34 75 PB14 PA1□ 35 74 PB13 73 PB12 PA2□ 36 $\frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times \frac{1}{2} \times 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Figure 14. STM32F40xxx LQFP144 pinout

  1. The above figure shows the package top view.

47/

Figure 15. STM32F40xxx LQFP176 pinout

  1. The above figure shows the package top view.

Figure 16. STM32F40xxx UFBGA176 ballout

123
3		456789101112131415
APE3PE2PE1PE0PB8PB5PG14PG13PB4PB3PD7PC12PA15PA14PA13
BPE4PE5PE6PB9PB7PB6PG15PG12PG11PG10PD6PD0PC11PC10PA12
CVBATPI7PI6PI5VDDPDR_ONVDDVDDVDDPG9PD5PD1PI3PI2PA11
DPC13PI8PI9PI4VSSBOOT0VSSVSSVSSPD4PD3PD2PH15PI1PA10
EPC14PF0PI10PI11PH13PH14PI0PA9
FPC15VSSVDDPH2VSSVSSVSSVSSVSSVSSVCAP_2PC9PA8
GPH0VSSVDDPH3VSSVSSVSSVSSVSSVSSVDDPC8PC7
HPH1PF2PF1PH4VSSVSSVSSVSSVSSVSSVDDPG8PC6
JNRSTPF3PF4PH5VSSVSSVSSVSSVSSVDDVDDPG7PG6
KPF7PF6PF5VDDVSSVSSVSSVSSVSSPH12PG5PG4PG3
LPF10PF9PF8BYPASS_
REG		PH11PH10PD15PG2
MVSSAPC0PC1PC2PC3PB2PG1VSSVSSVCAP_1PH6PH8PH9PD14PD13
NVREF-PA1PA0PA4PC4PF13PG0VDDVDDVDDPE13PH7PD12PD11PD10
PVREF+PA2PA6PA5PC5PF12PF15PE8PE9PE11PE14PB12PB13PD9PD8
RVDDAPA3PA7PB1PB0PF11PF14PE7PE10PE12PE15PB10PB11PB14PB15

1. This figure shows the package top view.

10 4 2 8 7 5 1 PA14 VBAT PC13 PDR_ON вooтo PB4 PD7 PD4 PC12 VDD PC14 PI1 VCAP_2 PC15 PD2 VDD PB3 PD6 PA15 B PB7 C PA0 VSS PB9 PB6 PD5 PD1 PC11 PI0 PA12 PA11 PB5 PC10 PA13 PA10 PB8 PC3 VDD VSS VDD E PC0 VSS PC9 PC8 PC7 VSS F PH0 PH1 VDD PE10 PE14 VCAP_1 PC6 PD14 PD15 PA1 G NRST VDDA PB0 PE13 PE15 PD12 PD11 PA6 PB1 PE12 PB10 PB15 PE9 PE11 PB11 PB12 PB14 PA7 PB2 PB13 MS30402V1

Figure 17. STM32F40xxx WLCSP90 ballout

Table 6. Legend/abbreviations used in the pinout table

NameAbbreviationDefinition
Pin namespecified in brackets below the pin name, the pin function during and after as the actual pin name
SSupply pin
Pin typeIInput only pin
I/OInput / output pin
FT5 V tolerant I/O
I/O structureTTa3.3 V tolerant I/O directly connected to ADC
i/O structureBDedicated BOOT0 pin
RSTBidirectional reset pin with embedded weak pull-up resistor
NotesUnless otherwisespecified by a note, all I/Os are set as floating inputs during and after reset
Alternate functionsFunctions selectedd through GPIOx_AFR registers
Additional functionsFunctions directlyselected/enabled through peripheral registers

1. This figure shows the package bump view.

Table 7. STM32F40xxx pin and ball definitions(1)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|------------|----------------------------------------------------------|------------------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | - | 1 | 1 | A2 | 1 | PE2 | I/O | FT | - | TRACECLK/ FSMC_A23 /
ETH_MII_TXD3 /
EVENTOUT | - | | - | - | 2 | 2 | A1 | 2 | PE3 | I/O | FT | - | TRACED0/FSMC_A19 /
EVENTOUT | - | | - | - | 3 | 3 | B1 | 3 | PE4 | I/O | FT | - | TRACED1/FSMC_A20 /
DCMI_D4/ EVENTOUT | - | | - | - | 4 | 4 | B2 | 4 | PE5 | I/O | FT | - | TRACED2 / FSMC_A21 /
TIM9_CH1 / DCMI_D6 /
EVENTOUT | - | | - | - | 5 | 5 | B3 | 5 | PE6 | I/O | FT | - | TRACED3 / FSMC_A22 /
TIM9_CH2 / DCMI_D7 /
EVENTOUT | - | | 1 | A10 | 6 | 6 | C1 | 6 | VBAT | S | - | - | - | - | | - | - | - | - | D2 | 7 | PI8 | I/O | FT | (3)(
4) | - | RTC_TAMP1,
RTC_TAMP2,
RTC_TS | | 2 | A9 | 7 | 7 | D1 | 8 | PC13 | I/O | FT | (3)
(4) | - | RTC_OUT,
RTC_TAMP1,
RTC_TS | | 3 | B10 | 8 | 8 | E1 | 9 | PC14/OSC32_IN
(PC14) | I/O | FT | (3)(
4) | - | OSC32_IN(5) | | 4 | B9 | 9 | 9 | F1 | 10 | PC15/
OSC32_OUT
(PC15) | I/O | FT | (3)(
4) | - | OSC32_OUT(5) | | - | - | - | - | D3 | 11 | PI9 | I/O | FT | - | CAN1_RX / EVENTOUT | - | | - | - | - | - | E3 | 12 | PI10 | I/O | FT | - | ETH_MII_RX_ER /
EVENTOUT | - | | - | - | - | - | E4 | 13 | PI11 | I/O | FT | - | OTG_HS_ULPI_DIR /
EVENTOUT | - | | - | - | - | - | F2 | 14 | VSS | S | - | - | - | - | | - | - | - | - | F3 | 15 | VDD | S | - | - | - | - | | - | - | - | 10 | E2 | 16 | PF0 | I/O | FT | - | FSMC_A0 / I2C2_SDA /
EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|---------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | - | - | 11 | H3 | 17 | PF1 | I/O | FT | - | FSMC_A1 / I2C2_SCL /
EVENTOUT | - | | - | - | - | 12 | H2 | 18 | PF2 | I/O | FT | - | FSMC_A2 / I2C2_SMBA /
EVENTOUT | - | | - | - | - | 13 | J2 | 19 | PF3 | I/O | FT | (5) | FSMC_A3/EVENTOUT | ADC3_IN9 | | - | - | - | 14 | J3 | 20 | PF4 | I/O | FT | (5) | FSMC_A4/EVENTOUT | ADC3_IN14 | | - | - | - | 15 | K3 | 21 | PF5 | I/O | FT | (5) | FSMC_A5/EVENTOUT | ADC3_IN15 | | - | C9 | 10 | 16 | G2 | 22 | VSS | S | - | - | - | - | | - | B8 | 11 | 17 | G3 | 23 | VDD | S | - | - | - | - | | - | - | - | 18 | K2 | 24 | PF6 | I/O | FT | (5) | TIM10_CH1 /
FSMC_NIORD/
EVENTOUT | ADC3_IN4 | | - | - | - | 19 | K1 | 25 | PF7 | I/O | FT | (5) | TIM11_CH1/FSMC_NREG/
EVENTOUT | ADC3_IN5 | | - | - | - | 20 | L3 | 26 | PF8 | I/O | FT | (5) | TIM13_CH1 /
FSMC_NIOWR/
EVENTOUT | ADC3_IN6 | | - | - | - | 21 | L2 | 27 | PF9 | I/O | FT | (5) | TIM14_CH1 / FSMC_CD/
EVENTOUT | ADC3_IN7 | | - | - | - | 22 | L1 | 28 | PF10 | I/O | FT | (5) | FSMC_INTR/ EVENTOUT | ADC3_IN8 | | 5 | F10 | 12 | 23 | G1 | 29 | PH0/OSC_IN
(PH0) | I/O | FT | - | EVENTOUT | OSC_IN(5) | | 6 | F9 | 13 | 24 | H1 | 30 | PH1/OSC_OUT
(PH1) | I/O | FT | - | EVENTOUT | OSC_OUT(5) | | 7 | G10 | 14 | 25 | J1 | 31 | NRST | I/O | RST | - | - | - | | 8 | E10 | 15 | 26 | M2 | 32 | PC0 | I/O | FT | (5) | OTG_HS_ULPI_STP/
EVENTOUT | ADC123_IN10 | | 9 | - | 16 | 27 | M3 | 33 | PC1 | I/O | FT | (5) | ETH_MDC/ EVENTOUT | ADC123_IN11 | | 10 | D10 | 17 | 28 | M4 | 34 | PC2 | I/O | FT | (5) | SPI2_MISO /
OTG_HS_ULPI_DIR /
ETH_MII_TXD2
/I2S2ext_SD/ EVENTOUT | ADC123_IN12 |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|---------------------------------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | 11 | E9 | 18 | 29 | M5 | 35 | PC3 | I/O | FT | (5) | SPI2_MOSI / I2S2_SD /
OTG_HS_ULPI_NXT /
ETH_MII_TX_CLK/
EVENTOUT | ADC123_IN13 | | - | - | 19 | 30 | - | 36 | VDD | S | - | - | - | - | | 12 | H10 | 20 | 31 | M1 | 37 | VSSA | S | - | - | - | - | | - | - | - | - | N1 | - | VREF– | S | - | - | - | - | | - | - | 21 | 32 | P1 | 38 | VREF+ | S | - | - | - | - | | 13 | G9 | 22 | 33 | R1 | 39 | VDDA | S | - | - | - | - | | 14 | C10 | 23 | 34 | N3 | 40 | PA0/WKUP
(PA0) | I/O | FT | (6) | USART2_CTS/
UART4_TX/
ETH_MII_CRS /
TIM2_CH1_ETR/
TIM5_CH1 / TIM8_ETR/
EVENTOUT | ADC123_IN0/WK
UP(5) | | 15 | F8 | 24 | 35 | N2 | 41 | PA1 | I/O | FT | (5) | USART2_RTS /
UART4_RX/
ETH_RMII_REF_CLK /
ETH_MII_RX_CLK /
TIM5_CH2 / TIM2_CH2/
EVENTOUT | ADC123_IN1 | | 16 | J10 | 25 | 36 | P2 | 42 | PA2 | I/O | FT | (5) | USART2_TX/TIM5_CH3 /
TIM9_CH1 / TIM2_CH3 /
ETH_MDIO/ EVENTOUT | ADC123_IN2 | | - | - | - | - | F4 | 43 | PH2 | I/O | FT | - | ETH_MII_CRS/EVENTOUT | - | | - | - | - | - | G4 | 44 | PH3 | I/O | FT | - | ETH_MII_COL/EVENTOUT | - | | - | - | - | - | H4 | 45 | PH4 | I/O | FT | - | I2C2_SCL /
OTG_HS_ULPI_NXT/
EVENTOUT | - | | - | - | - | - | J4 | 46 | PH5 | I/O | FT | - | I2C2_SDA/ EVENTOUT | - | | 17 | H9 | 26 | 37 | R2 | 47 | PA3 | I/O | FT | (5) | USART2_RX/TIM5_CH4 /
TIM9_CH2 / TIM2_CH4 /
OTG_HS_ULPI_D0 /
ETH_MII_COL/
EVENTOUT | ADC123_IN3 | | 18 | E5 | 27 | 38 | - | - | VSS | S | - | - | - | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|-----------------------------------------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | D9 | - | - | L4 | 48 | BYPASS_REG | I | FT | - | - | - | | 19 | E4 | 28 | 39 | K4 | 49 | VDD | S | - | - | - | - | | 20 | J9 | 29 | 40 | N4 | 50 | PA4 | I/O | TTa | (5) | SPI1_NSS / SPI3_NSS /
USART2_CK /
DCMI_HSYNC /
OTG_HS_SOF/ I2S3_WS/
EVENTOUT | ADC12_IN4
/DAC_OUT1 | | 21 | G8 | 30 | 41 | P4 | 51 | PA5 | I/O | TTa | (5) | SPI1_SCK/
OTG_HS_ULPI_CK /
TIM2_CH1_ETR/
TIM8_CH1N/ EVENTOUT | ADC12_IN5/DAC
_OUT2 | | 22 | H8 | 31 | 42 | P3 | 52 | PA6 | I/O | FT | (5) | SPI1_MISO /
TIM8_BKIN/TIM13_CH1 /
DCMI_PIXCLK / TIM3_CH1
/ TIM1_BKIN/ EVENTOUT | ADC12_IN6 | | 23 | J8 | 32 | 43 | R3 | 53 | PA7 | I/O | FT | (5) | SPI1_MOSI/ TIM8_CH1N /
TIM14_CH1/TIM3_CH2/
ETH_MII_RX_DV /
TIM1_CH1N /
ETH_RMII_CRS_DV/
EVENTOUT | ADC12_IN7 | | 24 | - | 33 | 44 | N5 | 54 | PC4 | I/O | FT | (5) | ETH_RMII_RX_D0 /
ETH_MII_RX_D0/
EVENTOUT | ADC12_IN14 | | 25 | - | 34 | 45 | P5 | 55 | PC5 | I/O | FT | (5) | ETH_RMII_RX_D1 /
ETH_MII_RX_D1/
EVENTOUT | ADC12_IN15 | | 26 | G7 | 35 | 46 | R5 | 56 | PB0 | I/O | FT | (5) | TIM3_CH3 / TIM8_CH2N/
OTG_HS_ULPI_D1/
ETH_MII_RXD2 /
TIM1_CH2N/ EVENTOUT | ADC12_IN8 | | 27 | H7 | 36 | 47 | R4 | 57 | PB1 | I/O | FT | (5) | TIM3_CH4 / TIM8_CH3N/
OTG_HS_ULPI_D2/
ETH_MII_RXD3 /
TIM1_CH3N/ EVENTOUT | ADC12_IN9 | | 28 | J7 | 37 | 48 | M6 | 58 | PB2/BOOT1
(PB2) | I/O | FT | - | EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|---------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | - | - | 49 | R6 | 59 | PF11 | I/O | FT | - | DCMI_D12/ EVENTOUT | - | | - | - | - | 50 | P6 | 60 | PF12 | I/O | FT | - | FSMC_A6/ EVENTOUT | - | | - | - | - | 51 | M8 | 61 | VSS | S | - | - | - | - | | - | - | - | 52 | N8 | 62 | VDD | S | - | - | - | - | | - | - | - | 53 | N6 | 63 | PF13 | I/O | FT | - | FSMC_A7/ EVENTOUT | - | | - | - | - | 54 | R7 | 64 | PF14 | I/O | FT | - | FSMC_A8/ EVENTOUT | - | | - | - | - | 55 | P7 | 65 | PF15 | I/O | FT | - | FSMC_A9/ EVENTOUT | - | | - | - | - | 56 | N7 | 66 | PG0 | I/O | FT | - | FSMC_A10/ EVENTOUT | - | | - | - | - | 57 | M7 | 67 | PG1 | I/O | FT | - | FSMC_A11/ EVENTOUT | - | | - | G6 | 38 | 58 | R8 | 68 | PE7 | I/O | FT | - | FSMC_D4/TIM1_ETR/
EVENTOUT | - | | - | H6 | 39 | 59 | P8 | 69 | PE8 | I/O | FT | - | FSMC_D5/ TIM1_CH1N/
EVENTOUT | - | | - | J6 | 40 | 60 | P9 | 70 | PE9 | I/O | FT | - | FSMC_D6/TIM1_CH1/
EVENTOUT | - | | - | - | - | 61 | M9 | 71 | VSS | S | - | - | - | - | | - | - | - | 62 | N9 | 72 | VDD | S | - | - | - | - | | - | F6 | 41 | 63 | R9 | 73 | PE10 | I/O | FT | - | FSMC_D7/TIM1_CH2N/
EVENTOUT | - | | - | J5 | 42 | 64 | P10 | 74 | PE11 | I/O | FT | - | FSMC_D8/TIM1_CH2/
EVENTOUT | - | | - | H5 | 43 | 65 | R10 | 75 | PE12 | I/O | FT | - | FSMC_D9/TIM1_CH3N/
EVENTOUT | - | | - | G5 | 44 | 66 | N11 | 76 | PE13 | I/O | FT | - | FSMC_D10/TIM1_CH3/
EVENTOUT | - | | - | F5 | 45 | 67 | P11 | 77 | PE14 | I/O | FT | - | FSMC_D11/TIM1_CH4/
EVENTOUT | - | | - | G4 | 46 | 68 | R11 | 78 | PE15 | I/O | FT | - | FSMC_D12/TIM1_BKIN/
EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|------------------------------------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | 29 | H4 | 47 | 69 | R12 | 79 | PB10 | I/O | FT | - | SPI2_SCK / I2S2_CK /
I2C2_SCL/ USART3_TX /
OTG_HS_ULPI_D3 /
ETH_MII_RX_ER /
TIM2_CH3/ EVENTOUT | - | | 30 | J4 | 48 | 70 | R13 | 80 | PB11 | I/O | FT | - | I2C2_SDA/USART3_RX/
OTG_HS_ULPI_D4 /
ETH_RMII_TX_EN/
ETH_MII_TX_EN /
TIM2_CH4/ EVENTOUT | - | | 31 | F4 | 49 | 71 | M10 | 81 | VCAP_1 | S | - | - | - | - | | 32 | - | 50 | 72 | N10 | 82 | VDD | S | - | - | - | - | | - | - | - | - | M11 | 83 | PH6 | I/O | FT | - | I2C2_SMBA / TIM12_CH1 /
ETH_MII_RXD2/
EVENTOUT | - | | - | - | - | - | N12 | 84 | PH7 | I/O | FT | - | I2C3_SCL /
ETH_MII_RXD3/
EVENTOUT | - | | - | - | - | - | M12 | 85 | PH8 | I/O | FT | - | I2C3_SDA /
DCMI_HSYNC/
EVENTOUT | - | | - | - | - | - | M13 | 86 | PH9 | I/O | FT | - | I2C3_SMBA / TIM12_CH2/
DCMI_D0/ EVENTOUT | - | | - | - | - | - | L13 | 87 | PH10 | I/O | FT | - | TIM5_CH1 / DCMI_D1/
EVENTOUT | - | | - | - | - | - | L12 | 88 | PH11 | I/O | FT | - | TIM5_CH2 / DCMI_D2/
EVENTOUT | - | | - | - | - | - | K12 | 89 | PH12 | I/O | FT | - | TIM5_CH3 / DCMI_D3/
EVENTOUT | - | | - | - | - | - | H12 | 90 | VSS | S | - | - | - | - | | - | - | - | - | J12 | 91 | VDD | S | - | - | - | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|---------------------------------------------------------------------------------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | 33 | J3 | 51 | 73 | P12 | 92 | PB12 | I/O | FT | - | SPI2_NSS / I2S2_WS /
I2C2_SMBA/
USART3_CK/ TIM1_BKIN /
CAN2_RX /
OTG_HS_ULPI_D5/
ETH_RMII_TXD0 /
ETH_MII_TXD0/
OTG_HS_ID/ EVENTOUT | - | | 34 | J1 | 52 | 74 | P13 | 93 | PB13 | I/O | FT | - | SPI2_SCK / I2S2_CK /
USART3_CTS/
TIM1_CH1N /CAN2_TX /
OTG_HS_ULPI_D6 /
ETH_RMII_TXD1 /
ETH_MII_TXD1/
EVENTOUT | OTG_HS_VBUS | | 35 | J2 | 53 | 75 | R14 | 94 | PB14 | I/O | FT | - | SPI2_MISO/ TIM1_CH2N /
TIM12_CH1 /
OTG_HS_DM/
USART3_RTS /
TIM8_CH2N/I2S2ext_SD/
EVENTOUT | - | | 36 | H1 | 54 | 76 | R15 | 95 | PB15 | I/O | FT | - | SPI2_MOSI / I2S2_SD/
TIM1_CH3N / TIM8_CH3N
/ TIM12_CH2 /
OTG_HS_DP/ EVENTOUT | RTC_REFIN | | - | H2 | 55 | 77 | P15 | 96 | PD8 | I/O | FT | - | FSMC_D13 / USART3_TX/
EVENTOUT | - | | - | H3 | 56 | 78 | P14 | 97 | PD9 | I/O | FT | - | FSMC_D14 / USART3_RX/
EVENTOUT | - | | - | G3 | 57 | 79 | N15 | 98 | PD10 | I/O | FT | - | FSMC_D15 / USART3_CK/
EVENTOUT | - | | - | G1 | 58 | 80 | N14 | 99 | PD11 | I/O | FT | - | FSMC_CLE /
FSMC_A16/USART3_CTS/
EVENTOUT | - | | - | G2 | 59 | 81 | N13 | 100 | PD12 | I/O | FT | - | FSMC_ALE/
FSMC_A17/TIM4_CH1 /
USART3_RTS/
EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|----------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | - | 60 | 82 | M15 | 101 | PD13 | I/O | FT | - | FSMC_A18/TIM4_CH2/
EVENTOUT | - | | - | - | - | 83 | - | 102 | VSS | S | - | - | - | - | | - | - | - | 84 | J13 | 103 | VDD | S | - | - | - | - | | - | F2 | 61 | 85 | M14 | 104 | PD14 | I/O | FT | - | FSMC_D0/TIM4_CH3/
EVENTOUT/ EVENTOUT | - | | - | F1 | 62 | 86 | L14 | 105 | PD15 | I/O | FT | - | FSMC_D1/TIM4_CH4/
EVENTOUT | - | | - | - | - | 87 | L15 | 106 | PG2 | I/O | FT | - | FSMC_A12/ EVENTOUT | - | | - | - | - | 88 | K15 | 107 | PG3 | I/O | FT | - | FSMC_A13/ EVENTOUT | - | | - | - | - | 89 | K14 | 108 | PG4 | I/O | FT | - | FSMC_A14/ EVENTOUT | - | | - | - | - | 90 | K13 | 109 | PG5 | I/O | FT | - | FSMC_A15/ EVENTOUT | - | | - | - | - | 91 | J15 | 110 | PG6 | I/O | FT | - | FSMC_INT2/ EVENTOUT | - | | - | - | - | 92 | J14 | 111 | PG7 | I/O | FT | - | FSMC_INT3 /USART6_CK/
EVENTOUT | - | | - | - | - | 93 | H14 | 112 | PG8 | I/O | FT | - | USART6_RTS /
ETH_PPS_OUT/
EVENTOUT | - | | - | - | - | 94 | G12 | 113 | VSS | S | | - | - | - | | - | - | - | 95 | H13 | 114 | VDD | S | | - | - | - | | 37 | F3 | 63 | 96 | H15 | 115 | PC6 | I/O | FT | - | I2S2_MCK /
TIM8_CH1/SDIO_D6 /
USART6_TX /
DCMI_D0/TIM3_CH1/
EVENTOUT | - | | 38 | E1 | 64 | 97 | G15 | 116 | PC7 | I/O | FT | - | I2S3_MCK /
TIM8_CH2/SDIO_D7 /
USART6_RX /
DCMI_D1/TIM3_CH2/
EVENTOUT | - | | 39 | E2 | 65 | 98 | G14 | 117 | PC8 | I/O | FT | - | TIM8_CH3/SDIO_D0
/TIM3_CH3/ USART6_CK /
DCMI_D2/ EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|---------------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | 40 | E3 | 66 | 99 | F14 | 118 | PC9 | I/O | FT | - | I2S_CKIN/ MCO2 /
TIM8_CH4/SDIO_D1 /
/I2C3_SDA / DCMI_D3 /
TIM3_CH4/ EVENTOUT | - | | 41 | D1 | 67 | 100 | F15 | 119 | PA8 | I/O | FT | - | MCO1 / USART1_CK/
TIM1_CH1/ I2C3_SCL/
OTG_FS_SOF/
EVENTOUT | - | | 42 | D2 | 68 | 101 | E15 | 120 | PA9 | I/O | FT | - | USART1_TX/ TIM1_CH2 /
I2C3_SMBA / DCMI_D0/
EVENTOUT | OTG_FS_VBUS | | 43 | D3 | 69 | 102 | D15 | 121 | PA10 | I/O | FT | - | USART1_RX/ TIM1_CH3/
OTG_FS_ID/DCMI_D1/
EVENTOUT | - | | 44 | C1 | 70 | 103 | C15 | 122 | PA11 | I/O | FT | - | USART1_CTS / CAN1_RX
/ TIM1_CH4 /
OTG_FS_DM/ EVENTOUT | - | | 45 | C2 | 71 | 104 | B15 | 123 | PA12 | I/O | FT | - | USART1_RTS / CAN1_TX/
TIM1_ETR/ OTG_FS_DP/
EVENTOUT | - | | 46 | D4 | 72 | 105 | A15 | 124 | PA13
(JTMS-SWDIO) | I/O | FT | - | JTMS-SWDIO/ EVENTOUT | - | | 47 | B1 | 73 | 106 | F13 | 125 | VCAP_2 | S | - | - | - | - | | - | E7 | 74 | 107 | F12 | 126 | VSS | S | - | - | - | - | | 48 | E6 | 75 | 108 | G13 | 127 | VDD | S | - | - | - | - | | - | - | - | - | E12 | 128 | PH13 | I/O | FT | - | TIM8_CH1N / CAN1_TX/
EVENTOUT | - | | - | - | - | - | E13 | 129 | PH14 | I/O | FT | - | TIM8_CH2N / DCMI_D4/
EVENTOUT | - | | - | - | - | - | D13 | 130 | PH15 | I/O | FT | - | TIM8_CH3N / DCMI_D11/
EVENTOUT | - | | - | C3 | - | - | E14 | 131 | PI0 | I/O | FT | - | TIM5_CH4 / SPI2_NSS /
I2S2_WS / DCMI_D13/
EVENTOUT | - | | - | B2 | - | - | D14 | 132 | PI1 | I/O | FT | - | SPI2_SCK / I2S2_CK /
DCMI_D8/ EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|-----------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | - | - | - | C14 | 133 | PI2 | I/O | FT | - | TIM8_CH4 /SPI2_MISO /
DCMI_D9 / I2S2ext_SD/
EVENTOUT | - | | - | - | - | - | C13 | 134 | PI3 | I/O | FT | - | TIM8_ETR / SPI2_MOSI /
I2S2_SD / DCMI_D10/
EVENTOUT | - | | - | - | - | - | D9 | 135 | VSS | S | - | - | - | - | | - | - | - | - | C9 | 136 | VDD | S | - | - | - | - | | 49 | A2 | 76 | 109 | A14 | 137 | PA14
(JTCK/SWCLK) | I/O | FT | - | JTCK-SWCLK/ EVENTOUT | - | | 50 | B3 | 77 | 110 | A13 | 138 | PA15
(JTDI) | I/O | FT | - | JTDI/ SPI3_NSS/
I2S3_WS/TIM2_CH1_ETR
/ SPI1_NSS / EVENTOUT | - | | 51 | D5 | 78 | 111 | B14 | 139 | PC10 | I/O | FT | - | SPI3_SCK / I2S3_CK/
UART4_TX/SDIO_D2 /
DCMI_D8 / USART3_TX/
EVENTOUT | - | | 52 | C4 | 79 | 112 | B13 | 140 | PC11 | I/O | FT | - | UART4_RX/ SPI3_MISO /
SDIO_D3 /
DCMI_D4/USART3_RX /
I2S3ext_SD/ EVENTOUT | - | | 53 | A3 | 80 | 113 | A12 | 141 | PC12 | I/O | FT | - | UART5_TX/SDIO_CK /
DCMI_D9 / SPI3_MOSI
/I2S3_SD / USART3_CK/
EVENTOUT | - | | - | D6 | 81 | 114 | B12 | 142 | PD0 | I/O | FT | - | FSMC_D2/CAN1_RX/
EVENTOUT | - | | - | C5 | 82 | 115 | C12 | 143 | PD1 | I/O | FT | - | FSMC_D3 / CAN1_TX/
EVENTOUT | - | | 54 | B4 | 83 | 116 | D12 | 144 | PD2 | I/O | FT | - | TIM3_ETR/UART5_RX/
SDIO_CMD / DCMI_D11/
EVENTOUT | - | | - | - | 84 | 117 | D11 | 145 | PD3 | I/O | FT | - | FSMC_CLK/
USART2_CTS/
EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|--------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | A4 | 85 | 118 | D10 | 146 | PD4 | I/O | FT | - | FSMC_NOE/
USART2_RTS/
EVENTOUT | - | | - | C6 | 86 | 119 | C11 | 147 | PD5 | I/O | FT | - | FSMC_NWE/USART2_TX/
EVENTOUT | - | | - | - | - | 120 | D8 | 148 | VSS | S | - | - | - | - | | - | - | - | 121 | C8 | 149 | VDD | S | - | - | - | - | | - | B5 | 87 | 122 | B11 | 150 | PD6 | I/O | FT | - | FSMC_NWAIT/
USART2_RX/ EVENTOUT | - | | - | A5 | 88 | 123 | A11 | 151 | PD7 | I/O | FT | - | USART2_CK/FSMC_NE1/
FSMC_NCE2/ EVENTOUT | - | | - | - | - | 124 | C10 | 152 | PG9 | I/O | FT | - | USART6_RX /
FSMC_NE2/FSMC_NCE3/
EVENTOUT | - | | - | - | - | 125 | B10 | 153 | PG10 | I/O | FT | - | FSMC_NCE4_1/
FSMC_NE3/ EVENTOUT | - | | - | - | - | 126 | B9 | 154 | PG11 | I/O | FT | - | FSMC_NCE4_2 /
ETH_MII_TX_EN/
ETH _RMII_TX_EN/
EVENTOUT | - | | - | - | - | 127 | B8 | 155 | PG12 | I/O | FT | - | FSMC_NE4 /
USART6_RTS/
EVENTOUT | - | | - | - | - | 128 | A8 | 156 | PG13 | I/O | FT | - | FSMC_A24 /
USART6_CTS
/ETH_MII_TXD0/
ETH_RMII_TXD0/
EVENTOUT | - | | - | - | - | 129 | A7 | 157 | PG14 | I/O | FT | - | FSMC_A25 / USART6_TX
/ETH_MII_TXD1/
ETH_RMII_TXD1/
EVENTOUT | - | | - | E8 | - | 130 | D7 | 158 | VSS | S | - | - | - | - | | - | F7 | - | 131 | C7 | 159 | VDD | S | - | - | - | - | | - | - | - | 132 | B7 | 160 | PG15 | I/O | FT | - | USART6_CTS /
DCMI_D13/ EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|---------------------------------------------------------------------------------------------------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | 55 | B6 | 89 | 133 | A10 | 161 | PB3
(JTDO/
TRACESWO) | I/O | FT | - | JTDO/ TRACESWO/
SPI3_SCK / I2S3_CK /
TIM2_CH2 / SPI1_SCK/
EVENTOUT | - | | 56 | A6 | 90 | 134 | A9 | 162 | PB4
(NJTRST) | I/O | FT | - | NJTRST/ SPI3_MISO /
TIM3_CH1 / SPI1_MISO /
I2S3ext_SD/ EVENTOUT | - | | 57 | D7 | 91 | 135 | A6 | 163 | PB5 | I/O | FT | - | I2C1_SMBA/ CAN2_RX /
OTG_HS_ULPI_D7 /
ETH_PPS_OUT/TIM3_CH2
/ SPI1_MOSI/ SPI3_MOSI /
DCMI_D10 / I2S3_SD/
EVENTOUT | - | | 58 | C7 | 92 | 136 | B6 | 164 | PB6 | I/O | FT | - | I2C1_SCL/ TIM4_CH1 /
CAN2_TX /
DCMI_D5/USART1_TX/
EVENTOUT | - | | 59 | B7 | 93 | 137 | B5 | 165 | PB7 | I/O | FT | - | I2C1_SDA / FSMC_NL /
DCMI_VSYNC /
USART1_RX/ TIM4_CH2/
EVENTOUT | - | | 60 | A7 | 94 | 138 | D6 | 166 | BOOT0 | I | B | - | - | VPP | | 61 | D8 | 95 | 139 | A5 | 167 | PB8 | I/O | FT | - | TIM4_CH3/SDIO_D4/
TIM10_CH1 / DCMI_D6 /
ETH_MII_TXD3 /
I2C1_SCL/ CAN1_RX/
EVENTOUT | - | | 62 | C8 | 96 | 140 | B4 | 168 | PB9 | I/O | FT | - | SPI2_NSS/ I2S2_WS /
TIM4_CH4/ TIM11_CH1/
SDIO_D5 / DCMI_D7 /
I2C1_SDA / CAN1_TX/
EVENTOUT | - | | - | - | 97 | 141 | A4 | 169 | PE0 | I/O | FT | - | TIM4_ETR / FSMC_NBL0 /
DCMI_D2/ EVENTOUT | - | | - | - | 98 | 142 | A3 | 170 | PE1 | I/O | FT | - | FSMC_NBL1 / DCMI_D3/
EVENTOUT | - | | 63 | - | 99 | - | D5 | - | VSS | S | - | - | - | - |

| | | | Pin number | |--------|---------|---------|------------|----------|---------|------------------------------------------|----------|-----------------|-------|---------------------------------------|-------------------------| | LQFP64 | WLCSP90 | LQFP100 | LQFP144 | UFBGA176 | LQFP176 | Pin name
(function after
reset)(2) | Pin type | I / O structure | Notes | Alternate functions | Additional
functions | | - | A8 | - | 143 | C6 | 171 | PDR_ON | I | FT | - | - | - | | 64 | A1 | 10
0 | 144 | C5 | 172 | VDD | S | - | - | - | - | | - | - | - | - | D4 | 173 | PI4 | I/O | FT | - | TIM8_BKIN / DCMI_D5/
EVENTOUT | - | | - | - | - | - | C4 | 174 | PI5 | I/O | FT | - | TIM8_CH1 /
DCMI_VSYNC/
EVENTOUT | - | | - | - | - | - | C3 | 175 | PI6 | I/O | FT | - | TIM8_CH2 / DCMI_D6/
EVENTOUT | - | | - | - | - | - | C2 | 176 | PI7 | I/O | FT | - | TIM8_CH3 / DCMI_D7/
EVENTOUT | - |

Table 7. STM32F40xxx pin and ball definitions(1) (continued)

    1. Function availability depends on the chosen device.
    1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
    • The speed should not exceed 2 MHz with a maximum load of 30 pF.
    • These I/Os must not be used as a current source (e.g. to drive an LED).
    1. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com.
    1. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
    1. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low).

Table 8. FSMC pin definition

FSMCWLCSP90
Pins(1)CFNOR/PSRAM/
SRAM		NOR/PSRAM MuxNAND 16 bitLQFP100(2)(2)
PE2-A23A23-Yes-
PE3-A19A19-Yes-
PE4-A20A20-Yes-
PE5-A21A21-Yes-
PE6-A22A22-Yes-

1. UFBGA176 F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9 and K10 balls are connected to VSS for heat dissipation and package mechanical stability.

Table 8. FSMC pin definition (continued)

| | | | FSMC | |---------|-------|--------------------|---------------|-------------|------------|----------------| | Pins(1) | CF | NOR/PSRAM/
SRAM | NOR/PSRAM Mux | NAND 16 bit | LQFP100(2) | WLCSP90
(2) | | PF0 | A0 | A0 | - | - | - | - | | PF1 | A1 | A1 | - | - | - | - | | PF2 | A2 | A2 | - | - | - | - | | PF3 | A3 | A3 | - | - | - | - | | PF4 | A4 | A4 | - | - | - | - | | PF5 | A5 | A5 | - | - | - | - | | PF6 | NIORD | - | - | - | - | - | | PF7 | NREG | - | - | - | - | - | | PF8 | NIOWR | - | - | - | - | - | | PF9 | CD | - | - | - | - | - | | PF10 | INTR | - | - | - | - | - | | PF12 | A6 | A6 | - | - | - | - | | PF13 | A7 | A7 | - | - | - | - | | PF14 | A8 | A8 | - | - | - | - | | PF15 | A9 | A9 | - | - | - | - | | PG0 | A10 | A10 | - | - | - | - | | PG1 | - | A11 | - | - | - | - | | PE7 | D4 | D4 | DA4 | D4 | Yes | Yes | | PE8 | D5 | D5 | DA5 | D5 | Yes | Yes | | PE9 | D6 | D6 | DA6 | D6 | Yes | Yes | | PE10 | D7 | D7 | DA7 | D7 | Yes | Yes | | PE11 | D8 | D8 | DA8 | D8 | Yes | Yes | | PE12 | D9 | D9 | DA9 | D9 | Yes | Yes | | PE13 | D10 | D10 | DA10 | D10 | Yes | Yes | | PE14 | D11 | D11 | DA11 | D11 | Yes | Yes | | PE15 | D12 | D12 | DA12 | D12 | Yes | Yes | | PD8 | D13 | D13 | DA13 | D13 | Yes | Yes | | PD9 | D14 | D14 | DA14 | D14 | Yes | Yes | | PD10 | D15 | D15 | DA15 | D15 | Yes | Yes | | PD11 | - | A16 | A16 | CLE | Yes | Yes | | PD12 | - | A17 | A17 | ALE | Yes | Yes | | PD13 | - | A18 | A18 | - | Yes | - | | PD14 | D0 | D0 | DA0 | D0 | Yes | Yes |

Table 8. FSMC pin definition (continued)

| | | | FSMC | |---------|--------|--------------------|---------------|-------------|------------|----------------| | Pins(1) | CF | NOR/PSRAM/
SRAM | NOR/PSRAM Mux | NAND 16 bit | LQFP100(2) | WLCSP90
(2) | | PD15 | D1 | D1 | DA1 | D1 | Yes | Yes | | PG2 | - | A12 | - | - | - | - | | PG3 | - | A13 | - | - | - | - | | PG4 | - | A14 | - | - | - | - | | PG5 | - | A15 | - | - | - | - | | PG6 | - | - | - | INT2 | - | - | | PG7 | - | - | - | INT3 | - | - | | PD0 | D2 | D2 | DA2 | D2 | Yes | Yes | | PD1 | D3 | D3 | DA3 | D3 | Yes | Yes | | PD3 | - | CLK | CLK | - | Yes | - | | PD4 | NOE | NOE | NOE | NOE | Yes | Yes | | PD5 | NWE | NWE | NWE | NWE | Yes | Yes | | PD6 | NWAIT | NWAIT | NWAIT | NWAIT | Yes | Yes | | PD7 | - | NE1 | NE1 | NCE2 | Yes | Yes | | PG9 | - | NE2 | NE2 | NCE3 | - | - | | PG10 | NCE4_1 | NE3 | NE3 | - | - | - | | PG11 | NCE4_2 | - | - | - | - | - | | PG12 | - | NE4 | NE4 | - | - | - | | PG13 | - | A24 | A24 | - | - | - | | PG14 | - | A25 | A25 | - | - | - | | PB7 | - | NADV | NADV | - | Yes | Yes | | PE0 | - | NBL0 | NBL0 | - | Yes | - | | PE1 | - | NBL1 | NBL1 | - | Yes | - |

1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column.

2. Ports F and G are not available in devices delivered in 100-pin packages.

Table 9. Alternate function mapping

| | | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | |--------|------|----------------|------------------------|-----------|------------------|---------------|--------------------------------|----------------------|------------------------|--------------------|---------------------------|--------------------|-------------------------------------------|----------------------|-----------------|------|----------| | Po | ort | sys | TIM1/2 | TIM3/4/5 | TIM8/9/10
/11 | I2C1/2/3 | SPI1/SPI2/
I2S2/I2S2e
xt | SPI3/I2Sext
/I2S3 | USART1/2/3/
I2S3ext | UART4/5/
USART6 | CAN1/2
TIM12/13/
14 | OTG_FS/
OTG_HS | ETH | FSMC/SDIO
/OTG_FS | DCMI | AF14 | AF15 | | | PA0 | - | TIM2_CH1_
ETR | TIM 5_CH1 | TIM8_ETR | - | - | - | USART2_CTS | UART4_TX | - | = | ETH_MII_CRS | = | = | = | EVENTOUT | | | PA1 | - | TIM2_CH2 | TIM5_CH2 | - | - | - | - | USART2_RTS | UART4_RX | - | - | ETH_MII
RX_CLK
ETH_RMIIREF
CLK | - | - | - | EVENTOUT | | | PA2 | = | TIM2_CH3 | TIM5_CH3 | TIM9_CH1 | = | =- | - | USART2_TX | = | - | = | ETH_MDIO | = | = | = | EVENTOUT | | | PA3 | - | TIM2_CH4 | TIM5_CH4 | TIM9_CH2 | - | - | - | USART2_RX | - | - | OTG_HS_ULPI
D0 | ETH MII_COL | = | - | - | EVENTOUT | | | PA4 | - | = | - | - | - | SPI1_NSS | SPI3_NSS
I2S3_WS | USART2_CK | = | - | - | - | OTG_HS_SOF | DCMI
HSYNC | - | EVENTOUT | | | PA5 | - | TIM2_CH1
ETR | - | TIM8_CH1N | - | SPI1_SCK | - | - | - | - | OTG_HS_ULPI_
CK | - | - | - | - | EVENTOUT | | | PA6 | - | TIM1_BKIN | TIM3_CH1 | TIM8_BKIN | - | SPI1_MISO | - | - | - | TIM13_CH1 | - | - | - | DCMI_
PIXCLK | - | EVENTOUT | | Port A | PA7 | - | TIM1_CH1N | TIM3_CH2 | TIM8_CH1N | - | SPI1_MOSI | - | - | - | TIM14_CH1 | - | ETH_MII_RX_DV
ETH_RMII
CRS_DV | - | - | - | EVENTOUT | | | PA8 | MCO1 | TIM1_CH1 | - | - | I2C3_SCL | - | - | USART1_CK | - | - | OTG_FS_SOF | - | - | - | - | EVENTOUT | | | PA9 | - | TIM1_CH2 | - | - | I2C3
SMBA | - | - | USART1_TX | - | - | - | - | - | DCMI_D0 | - | EVENTOUT | | | PA10 | - | TIM1_CH3 | ı | - | = | - | = | USART1_RX | Ξ | - | OTG_FS_ID | = | i e | DCMI_D1 | - | EVENTOUT | | | PA11 | - | TIM1_CH4 | - | - | - | - | - | USART1_CTS | - | CAN1_RX | OTG_FS_DM | - | - | - | - | EVENTOUT | | | PA12 | - | TIM1_ETR | - | - | - | - | - | USART1_RTS | - | CAN1_TX | OTG_FS_DP | - | - | - | - | EVENTOUT | | | PA13 | JTMS-
SWDIO | - | - | - | - | - | - | - | - | - | - | - | - | - | | EVENTOUT | | | PA14 | JTCK-
SWCLK | - | ī | = | - | = | - | = | Ü | - | = | = | - | - | =· | EVENTOUT | | | PA15 | JTDI | TIM 2_CH1
TIM 2_ETR | - | - | - | SPI1_NSS | SPI3_NSS/
I2S3_WS | - | - | - | - | - | - | - | | EVENTOUT |

Pinouts and pin description

Table 9. AAltoernatefuınctionmapping(continued)
AF0AF1AF2AF3AF4AF5AF6AF7
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PeortsysTIM1/2TIM3/4/5TIM8/9/10
/11		I2C1/2/3SPI1/SPI2/
I2S2/I2S2e
xt		SPI3/I2Sext
/I2S3		USART1/2/3/
I2S3ext
PB0ıTIM1_CH2NTIM3_CH3TIM8_CH2N----
PB1-TIM1_CH3NTIM3_CH4TIM8_CH3N---
PB2ii ii=ē===-=
PB3JTDO/
TRACES
WO		TIM2_CH2---SPI1_SCKSPI3_SCK
I2S3_CK		-
PB4NJTRST-TIM3_CH1-SPI1_MISOSPI3_MISOI2S3ext_SD
PB5-=TIM3_CH2I2C1_SMB
A		SPI1_MOSISPI3_MOSI
I2S3_SD		-
PB6ii ii=TIM4_CH1I2C1_SCL=-USART1_TX
PB7--TIM4_CH2I2C1_SDA--USART1_RX
Port BPB8i-TIM4_CH3TIM10_CH1I2C1_SCL---
PB9--TIM4_CH4TIM11_CH1I2C1_SDASPI2_NSS
I2S2_WS		--
PB101TIM2_CH3--I2C2_SCLSPI2_SCK
I2S2_CK		-USART3_TX
PB11÷TIM2_CH4--I2C2_SDA--USART3_RX
PB121TIM1_BKIN--I2C2_
SMBA		SPI2_NSS
I2S2_WS		-USART3_CK
PB13=TIM1_CH1N---SPI2_SCK
I2S2_CK		-USART3_CTS
PB14=TIM1_CH2N-TIM8_CH2NΞSPI2_MISOI2S2ext_SDUSART3_RTS
PB15RTC_
REFIN		TIM1_CH3N-TIM8_CH3N-SPI2_MOSI
I2S2_SD		--

Table 9. Alternate function mapping (continued)

| | | | | | | | | • • • • • • • • • • • • • • • • • • • • | | | ( | , | |--------|------|------|--------|----------|------------------|----------|--------------------------------|-----------------------------------------|------------------------|--------------------|---------------------------|---------------------|---------------------------------|----------------------|---------|------|----------| | | | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | | Po | ort | sys | TIM1/2 | TIM3/4/5 | TIM8/9/10
/11 | I2C1/2/3 | SPI1/SPI2/
I2S2/I2S2e
xt | SPI3/I2Sext
/I2S3 | USART1/2/3/
I2S3ext | UART4/5/
USART6 | CAN1/2
TIM12/13/
14 | OTG_FS/
OTG_HS | ETH | FSMC/SDIO
/OTG_FS | DCMI | AF14 | AF15 | | | PC0 | - | - | - | - | - | - | - | - | - | - | OTG_HS_ULPI_
STP | - | - | - | - | EVENTOUT | | | PC1 | - | - | - | - | - | - | - | - | - | - | - | ETH_MDC | - | - | - | EVENTOUT | | | PC2 | = | = | - | - | = | SPI2_MISO | I2S2ext_SD | - | - | - | OTG_HS_ULPI_
DIR | ETH MII_TXD2 | = | = | - | EVENTOUT | | | PC3 | = | = | - | - | = | SPI2_MOSI
I2S2_SD | - | - | - | - | OTG_HS_ULPI
NXT | ETH
_MII_TX_CLK | = | = | - | EVENTOUT | | | PC4 | - | - | - | - | - | - | - | - | - | - | - | ETH_MII_RXD0
ETH_RMII_RXD0 | - | - | - | EVENTOUT | | | PC5 | = | = | - | - | = | - | = | - | - | - | - | ETH _MII_RXD1
ETH _RMII_RXD1 | = | = | - | EVENTOUT | | | PC6 | - | - | TIM3_CH1 | TIM8_CH1 | | I2S2_MCK | | - | USART6_TX | - | - | - | SDIO_D6 | DCMI_D0 | - | EVENTOUT | | Port C | PC7 | 1 | - | TIM3_CH2 | TIM8_CH2 | - | - | I2S3_MCK | - | USART6_RX | - | - | - | SDIO_D7 | DCMI_D1 | - | EVENTOUT | | | PC8 | 1 | - | TIM3_CH3 | TIM8_CH3 | - | - | - | - | USART6_CK | - | - | - | SDIO_D0 | DCMI_D2 | - | EVENTOUT | | | PC9 | MCO2 | - | TIM3_CH4 | TIM8_CH4 | I2C3_SDA | I2S_CKIN | - | - | - | - | - | - | SDIO_D1 | DCMI_D3 | - | EVENTOUT | | | PC10 | - | - | - | - | - | - | SPI3_SCK/
I2S3_CK | USART3_TX/ | UART4_TX | - | - | - | SDIO_D2 | DCMI_D8 | - | EVENTOUT | | | PC11 | -i | = | = | - | = | I2S3ext_SD | SPI3_MISO/ | USART3_RX | UART4_RX | - | = | ≡ | SDIO_D3 | DCMI_D4 | - | EVENTOUT | | | PC12 | ı | - | - | - | - | - | SPI3_MOSI
I2S3_SD | USART3_CK | UART5_TX | - | - | = | SDIO_CK | DCMI_D9 | - | EVENTOUT | | | PC13 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | | PC14 | i | - | - | - | - | - | - | | - | - | - | - | - | i | - | - | | | PC15 | = | - | - | - | = | - | - | - | - | - | = | = | - | = | - | = |

2 TIM
CA
N1/
3/ 14
12/1
CAN
1_R
CAN
1_TX
RX
-
-
-
-
-		OTG
/ OTG
_FS
_HS
X
-
-
-
-
-
-
-		ETH
-
-
-
-
-
-		FSM
DIO /OT
C/S
G_F
S
FSM
C_D
2
FSM
C_D
3
SDI
O_C
MD
FSM
C_C
LK
FSM
C_N
OE		DC
MI
-
-
DCM
I_D1
1
-
-		AF
14
-
-
-
-
-		AF
15
EVE
NTO
UT
EVE
NTO
UT
EVE
NTO
UT
EVE
NTO
UT
EVE
NTO
UT
FSM
C_N
WE		--EVE
NTO
UT
-FSM
C_N
WAI
T		--EVE
NTO
UT
---E1/ FSM
FSM
C_N
C_N
CE2		--EVE
NTO
UT
---FSM
C_D
13		--EVE
NTO
UT
---FSM
C_D
14		--EVE
NTO
UT
---FSM
C_D
15		--EVE
NTO
UT
---FSM
C_A
16		--EVE
NTO
UT
---FSM
C_A
17		--NTO
EVE
UT
---FSM
C_A
18		--EVE
NTO
UT
---FSM
C_D
0		--EVE
NTO
UT
---FSM
C_D
1		--EVE
NTO
UT

Table 9. Alternate function mapping (continued)

| | | | | | | | | | | | ` | |--------|------|--------------|-----------|----------|------------------|----------|--------------------------------|----------------------|------------------------|--------------------|---------------------------|-------------------|---------------|----------------------|---------|------|----------| | | | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | | Pe | ort | sys | TIM1/2 | TIM3/4/5 | TIM8/9/10
/11 | I2C1/2/3 | SPI1/SPI2/
I2S2/I2S2e
xt | SPI3/I2Sext
/I2S3 | USART1/2/3/
I2S3ext | UART4/5/
USART6 | CAN1/2
TIM12/13/
14 | OTG_FS/
OTG_HS | ETH | FSMC/SDIO
/OTG_FS | DCMI | AF14 | AF15 | | | PE0 | - | - | TIM4_ETR | - | - | - | - | - | - | - | - | - | FSMC_NBL0 | DCMI_D2 | - | EVENTOUT | | | PE1 | = | = | = | - | = | - | = | = | = | = | i i | = | FSMC_NBL1 | DCMI_D3 | - | EVENTOUT | | | PE2 | TRACECL
K | = | - | - | = | - | = | - | - | - | - | ETH _MII_TXD3 | FSMC_A23 | = | - | EVENTOUT | | | PE3 | TRACED0 | - | - | - | - | - | - | - | - | - | - | - | FSMC_A19 | - | - | EVENTOUT | | | PE4 | TRACED1 | - | - | - | - | - | - | | - | - | - | - | FSMC_A20 | DCMI_D4 | - | EVENTOUT | | | PE5 | TRACED2 | - | - | TIM9_CH1 | - | - | - | - | - | - | = | - | FSMC_A21 | DCMI_D6 | - | EVENTOUT | | | PE6 | TRACED3 | - | - | TIM9_CH2 | - | - | - | - | - | - | = | - | FSMC_A22 | DCMI_D7 | - | EVENTOUT | | Port E | PE7 | - | TIM1_ETR | - | - | - | - | - | - | - | - | = | - | FSMC_D4 | = | - | EVENTOUT | | | PE8 | - | TIM1_CH1N | - | - | - | - | - | - | - | - | = | - | FSMC_D5 | - | - | EVENTOUT | | | PE9 | - | TIM1_CH1 | - | - | = | - | = | = | = | - | = | = | FSMC_D6 | = | - | EVENTOUT | | | PE10 | - | TIM1_CH2N | - | - | = | - | = | = | = | - | = | = | FSMC_D7 | = | - | EVENTOUT | | | PE11 | - | TIM1_CH2 | - | - | - | - | = | = | - | - | = | = | FSMC_D8 | - | - | EVENTOUT | | | PE12 | - | TIM1_CH3N | - | - | - | - | - | - | - | - | = | - | FSMC_D9 | = | - | EVENTOUT | | | PE13 | - | TIM1_CH3 | - | - | = | - | = | = | = | - | = | = | FSMC_D10 | = | = | EVENTOUT | | | PE14 | - | TIM1_CH4 | - | - | = | - | = | = | = | - | = | = | FSMC_D11 | = | = | EVENTOUT | | | PE15 | - | TIM1_BKIN | - | - | - | - | - | - | - | - | - | - | FSMC_D12 | - | - | EVENTOUT |

S8626 Rev 1

| Por
t | | AF
1 | AF2 | AF3 | AF4 | AF
5 | AF
6 | AF7 | AF
8 | AF9 | AF
10 | AF
11 | AF
12 | AF
13 | |-------------|--------|------------|------------------|-----------------------|--------------------|----------------------------------------------|-----------------------------------|-----------------------------------------|-----------------------------|-------------------------------------|----------------------------|----------|-----------------------------------|------------------|----------|------------------| | | SYS | TIM
1/2 | TIM
3/4/
5 | TIM
10 /11
8/9/ | I2C
1/2/
3 | SPI
/ I2S
1/S
PI2
2/I2
S2e xt | SPI
t /I2S
3/I2
Sex
3 | USA
/ I2S
RT1
/2/3
3ex
t | UA
/5/ USA
RT4
RT6 | 2 TIM
CA
N1/
3/ 14
12/1 | OTG
/ OTG
_FS
_HS | ETH | FSM
DIO /OT
C/S
G_F
S | DC
MI | AF
14 | AF
15 | | PF0 | - | - | - | - | I2C2
SD
A | - | - | - | - | - | - | - | FSM
C_A
0 | - | - | EVE
NTO
UT | | PF1 | - | - | - | - | I2C2
SC
L | - | - | - | - | - | - | - | FSM
C_A
1 | - | - | EVE
NTO
UT | | PF2 | - | - | - | - | I2C2
 SMB
A | - | - | - | - | - | - | - | FSM
C_A
2 | - | - | NTO
EVE
UT | | PF3 | - | - | - | - | - | - | - | - | - | - | - | - | FSM
C_A
3 | - | - | EVE
NTO
UT | | PF4 | - | - | - | - | - | - | - | - | - | - | - | - | FSM
C_A
4 | - | - | EVE
NTO
UT | | PF5 | - | - | - | - | - | - | - | - | - | - | - | - | FSM
C_A
5 | - | - | EVE
NTO
UT | | PF6 | - | - | - | TIM
10_C
H1 | - | - | - | - | - | - | - | - | FSM
C_N
IOR
D | - | - | EVE
NTO
UT | | PF7
Port | - | - | - | 11_C
TIM
H1 | - | - | - | - | - | - | - | - | FSM
C_N
REG | - | - | NTO
EVE
UT | | F
PF8 | - | - | - | - | - | - | - | - | - | TIM
13_C
H1 | - | - | C NIO
FSM
WR | - | - | EVE
NTO
UT | | PF9 | - | - | - | - | - | - | - | - | - | TIM
14_C
H1 | - | - | FSM
C_C
D | - | - | EVE
NTO
UT | | PF1 | 0
- | - | - | - | - | - | - | - | - | - | - | - | FSM
C_IN
TR | - | - | NTO
EVE
UT | | PF1 | 1
- | - | - | - | - | - | - | - | - | - | - | - | | DCM
I_D1
2 | - | EVE
NTO
UT | | PF1 | 2
- | - | - | - | - | - | - | - | - | - | - | - | FSM
C_A
6 | - | - | EVE
NTO
UT | | PF1 | 3
- | - | - | - | - | - | - | - | - | - | - | - | FSM
C_A
7 | - | - | EVE
NTO
UT | | PF1 | 4
- | - | - | - | - | - | - | - | - | - | - | - | FSM
C_A
8 | - | - | EVE
NTO
UT | | PF1 | 5
- | - | - | - | - | - | - | - | - | - | - | - | FSM
C_A
9 | - | - | NTO
EVE
UT |

Table 9. Alternate function mapping (continued)

| | | | | | | | | | | - 1-1-1-3 | ( | , | |--------|------|-----|--------|----------|------------------|----------|--------------------------------|----------------------|------------------------|--------------------|---------------------------|-------------------|---------------------------------------|------------------------------|----------|------|----------| | | | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | | P | ort | sys | TIM1/2 | TIM3/4/5 | TIM8/9/10
/11 | I2C1/2/3 | SPI1/SPI2/
I2S2/I2S2e
xt | SPI3/I2Sext
/I2S3 | USART1/2/3/
I2S3ext | UART4/5/
USART6 | CAN1/2
TIM12/13/
14 | OTG_FS/
OTG_HS | ETH | FSMC/SDIO
/OTG_FS | DCMI | AF14 | AF15 | | | PG0 | - | - | - | - | - | - | - | - | - | - | - | - | FSMC_A10 | - | - | EVENTOUT | | | PG1 | - | - | - | - | - | - | - | - | - | - | - | - | FSMC_A11 | - | - | EVENTOUT | | | PG2 | - | - | - | - | - | - | - | - | - | - | - | - | FSMC_A12 | - | - | EVENTOUT | | | PG3 | - | - | - | - | - | - | - | - | - | - | - | - | FSMC_A13 | - | - | EVENTOUT | | | PG4 | - | - | - | - | - | - | - | - | - | - | - | - | FSMC_A14 | - | - | EVENTOUT | | | PG5 | i | - | - | - | - | - | - | - | - | - | - | - | FSMC_A15 | - | - | EVENTOUT | | | PG6 | ì | - | - | - | - | - | - | - | - | - | - | - | FSMC_INT2 | - | - | EVENTOUT | | | PG7 | i | - | - | - | - | - | - | - | USART6_CK | - | - | - | FSMC_INT3 | - | - | EVENTOUT | | | PG8 | 1 | - | ÷ | - | 1 | - | - | - | USART6_
RTS | - | ı | ETH PPS_OUT | 1 | 1 | i | EVENTOUT | | Port G | PG9 | 1 | - | ÷ | - | 1 | - | - | - | USART6_RX | - | ı | - | FSMC_NE2/
FSMC_NCE3 | 1 | i | EVENTOUT | | | PG10 | ū | - | = | - | = | - | = | = | - | = | ē | = | FSMC
NCE4_1/
FSMC_NE3 | = | - | EVENTOUT | | | PG11 | - | - | - | - | - | - | - | - | - | - | - | ETH MII_TX_EN
ETH RMII
TX_EN | FSMC_NCE4
2 | - | = | EVENTOUT | | | PG12 | ū | - | - | - | = | - | = | = | USART6_
RTS | = | ē | = | FSMC_NE4 | = | = | EVENTOUT | | | PG13 | - | - | - | - | - | - | - | - | UART6_CTS | - | - | ETH _MII_TXD0
ETH _RMII_TXD0 | FSMC_A24 | - | i | EVENTOUT | | | PG14 | - | - | - | - | - | - | - | - | USART6_TX | - | - | ETH _MII_TXD1
ETH RMII_TXD1 | FSMC_A25 | - | | EVENTOUT | | | PG15 | - | - | - | - | - | - | - | - | USART6
CTS | - | - | - | - | DCMI_D13 | | EVENTOUT |

| | | AF0 | AF
1 | AF2 | AF3 | AF4 | AF
5 | AF
6 | AF7 | AF
8 | AF9 | AF
10 | AF
11 | AF
12 | AF
13 | |-----------|----------|-----|------------|------------------|-----------------------|--------------------|----------------------------------------------|-----------------------------------|-----------------------------------------|-----------------------------|-------------------------------------|------------------------------|--------------------------|-----------------------------------|---------------------|----------|------------------| | Por | t | SYS | TIM
1/2 | TIM
3/4/
5 | TIM
10 /11
8/9/ | I2C
1/2/
3 | SPI
/ I2S
1/S
PI2
2/I2
S2e xt | SPI
t /I2S
3/I2
Sex
3 | USA
/ I2S
RT1
/2/3
3ex
t | UA
/5/ USA
RT4
RT6 | 2 TIM
CA
N1/
3/ 14
12/1 | OTG
/ OTG
_FS
_HS | ETH | FSM
DIO /OT
C/S
G_F
S | DC
MI | AF
14 | AF
15 | | | PH0 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVE
NTO
UT | | | PH1 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | EVE
NTO
UT | | | PH2 | - | - | - | - | - | - | - | - | - | - | - | ETH
_M
II_C
RS | - | - | - | EVE
NTO
UT | | | PH3 | - | - | - | - | - | - | - | - | - | - | - | ETH
_M
II_C
OL | - | - | - | EVE
NTO
UT | | | PH4 | - | - | - | - | I2C2
_SC
L | - | - | - | - | - | OTG
HS
PI NXT
_UL | - | - | - | - | EVE
NTO
UT | | | PH5 | - | - | - | - | I2C2
SD
A | - | - | - | - | - | - | - | - | - | - | EVE
NTO
UT | | | PH6 | - | - | - | - | I2C2
 SMB
A | - | - | - | - | 12_C
TIM
H1 | - | ETH
_M
II_R
XD2 | - | - | - | NTO
EVE
UT | | | PH7 | - | - | - | - | I2C3
_SC
L | - | - | - | - | - | - | ETH
M
II_R
XD3 | - | - | - | EVE
NTO
UT | | Port
H | PH8 | - | - | - | - | I2C3
SD
A | - | - | - | - | - | - | - | - | I HSY
DCM
NC | - | EVE
NTO
UT | | | PH9 | - | - | - | - | I2C3
 SMB
A | - | - | - | - | TIM
12_C
H2 | - | - | - | DCM
I_D0 | - | EVE
NTO
UT | | | PH1
0 | - | - | TIM
5_C
H1 | - | - | - | - | - | - | - | - | - | - | DCM
I_D1 | - | EVE
NTO
UT | | | PH1
1 | - | - | 5_C
TIM
H2 | - | - | - | - | - | - | - | - | - | - | DCM
I_D2 | - | NTO
EVE
UT | | | PH1
2 | - | - | 5_C
H3
TIM | - | - | - | - | - | - | - | - | - | - | DCM
I_D3 | - | NTO
EVE
UT | | | PH1
3 | - | - | - | TIM
8_C
H1N | - | - | - | - | - | CAN
1_TX | - | - | - | - | - | EVE
NTO
UT | | | PH1
4 | - | - | - | TIM
8_C
H2N | - | - | - | - | - | - | - | - | - | DCM
I_D4 | - | EVE
NTO
UT | | | PH1
5 | - | - | - | TIM
8_C
H3N | - | - | - | - | - | - | - | - | - | DCM
I_D1
1 | - | EVE
NTO
UT |

Table 9. Alternate function mapping (continued)

| | | | | | | | | | | 11 0 | ` | , | |--------|------|-----|--------|----------|------------------|----------|--------------------------------|----------------------|------------------------|--------------------|---------------------------|---------------------|----------------|----------------------|----------------|------|----------| | | | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | | P | ort | sys | TIM1/2 | TIM3/4/5 | TIM8/9/10
/11 | I2C1/2/3 | SPI1/SPI2/
I2S2/I2S2e
xt | SPI3/I2Sext
/I2S3 | USART1/2/3/
I2S3ext | UART4/5/
USART6 | CAN1/2
TIM12/13/
14 | OTG_FS/
OTG_HS | ETH | FSMC/SDIO
/OTG_FS | DCMI | AF14 | AF15 | | | PI0 | - | - | TIM5_CH4 | - | - | SPI2_NSS
I2S2_WS | = | = | = | - | = | = | = | DCMI_D13 | = | EVENTOUT | | | PI1 | - | - | - | - | - | SPI2_SCK
I2S2_CK | - | - | - | - | - | - | - | DCMI_D8 | - | EVENTOUT | | | PI2 | - | - | = | TIM8_CH4 | = | SPI2_MISO | I2S2ext_SD | = | = | - | = | = | = | DCMI_D9 | ı | EVENTOUT | | | PI3 | - | - | = | TIM8_ETR | - | SPI2_MOSI
I2S2_SD | = | = | = | - | = | ē | ē | DCMI_D10 | ii. | EVENTOUT | | | PI4 | - | - | - | TIM8_BKIN | - | - | = | = | - | - | - | = | - | DCMI_D5 | - | EVENTOUT | | Port I | PI5 | - | - | - | TIM8_CH1 | - | - | - | - | - | - | - | - | - | DCMI_
VSYNC | - | EVENTOUT | | | PI6 | - | - | - | TIM8_CH2 | - | - | - | - | - | - | - | - | - | DCMI_D6 | - | EVENTOUT | | | PI7 | - | - | - | TIM8_CH3 | - | - | - | - | - | - | - | - | - | DCMI_D7 | - | EVENTOUT | | | PI8 | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | | | PI9 | - | - | - | - | - | - | - | - | - | CAN1_RX | - | - | - | - | - | EVENTOUT | | | PI10 | - | - | - | - | - | - | - | - | - | - | - | ETH MII_RX_ER | - | - | - | EVENTOUT | | | PI11 | - | - | - | - | - | - | - | - | - | - | OTG_HS_ULPI
DIR | - | = | - | = | EVENTOUT |

8626 Rev

Electrical Characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are evaluated in the worst conditions of ambient temperature, supply voltage, and frequencies by tests in production on 100% of the devices with an ambient temperature at $T_A = 25$ °C and $T_A = T_A$ max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean $\pm 3\Sigma$ ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on $T_A$ = 25 °C, $V_{DD}$ = 3.3 V (for the 1.8 V $\leq$ VDD $\leq$ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean $\pm 2\Sigma$ ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 19.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 20.

6.1.6 Power supply scheme

MS19911V3 Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Kernel logic (CPU, digital & RAM) Analog: RCs, PLL,.. Power switch VBAT GPIOs OUT IN 15 × 100 nF + 1 × 4.7 μF VBAT = 1.65 to 3.6V Voltage regulator VDDA ADC Level shifter IO Logic VDD 100 nF + 1 μF Flash memory VCAP_1 2 × 2.2 μF VCAP_2 BYPASS_REG PDR_ON Reset controller VDD 1/2/...14/15 VSS 1/2/...14/15 VDD VREF+ VREF-VSSA VREF 100 nF + 1 μF

Figure 21. Power supply scheme

    1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.
    1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.0.16: Voltage regulator and Table 3.0.15: Power supply supervisor.
    1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
    1. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
    1. VDDA=VDD and VSSA=VSS.

6.1.7 Current consumption measurement

ai14126 VBAT VDD VDDA I DD_VBAT I DD

Figure 22. Current consumption measurement scheme

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

SymbolRatingsMinMaxUnit
VDD–VSS(1)
External main supply voltage (including VDDA, VDD)		–0.34.0
Input voltage on five-volt tolerant pin(2)VSS–0.3VDD+4V
VINInput voltage on any other pinVSS–0.34.0
ΔVDDxVariations between different VDD power pins-50
VSSX −VSSVariations between all the different ground pins
including VREF−		-50mV
VESD(HBM)Electrostatic discharge voltage (human body model)see Section 6.3.14:
Absolute maximum
ratings (electrical
sensitivity)
Table 11. Voltage characteristics
    1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.
    1. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current.

SymbolRatingsMax.Unit
$I_{VDD}$Total current into V DD power lines (source) (1)240
I VSSTotal current out of V SS ground lines (sink) (1)240
1Output current sunk by any I/O and control pin25
I IOOutput current source by any I/Os and control pin25mA
(2)Injected current on five-volt tolerant I/O(3)-5/+0
INJ(PIN) ` 'Injected current on any other pin (4)
$\Sigma I_{\text{INJ(PIN)}}^{(4)}$Total injected current (sum of all I/O and control pins) (5)±25
Table 12. Current characteristics
  • All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.
  • Negative injection disturbs the analog performance of the device. See note in Section 6.3.21: 12-bit ADC characteristics.
    1. Positive injection is not possible on these I/Os. A negative injection is induced by $V_{IN} < V_{SS}$ . $I_{INJ(PIN)}$ must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
  • A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
  • When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature125°C

Thermal Information

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:

TJ max = TA max + (PD max x ΘJA)

Where:

  • TA max is the maximum ambient temperature in ° C,
  • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
  • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
  • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$$P_{I/O}$$ max = $\Sigma (V_{OL} \times I_{OL}) + \Sigma ((V_{DD} - V_{OH}) \times I_{OH})$ ,

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

SymbolParameterValueUnit
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch		46
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch		43
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch		40
ΘJAThermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch		38°C/W
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.65 mm pitch		39
Thermal resistance junction-ambient
WLCSP90 - 0.400 mm pitch		38.1
Table 98. Package thermal characteristics

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

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