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STM32F407VGT6

ARM Cortex-M4 MCU

The STM32F407VGT6 is a arm cortex-m4 mcu from STMicroelectronics. View the full STM32F407VGT6 datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.

Official STM32F407VGT6 datasheet (PDF) — the source this page was extracted from.

Manufacturer

STMicroelectronics

Package

100-LQFP

Lifecycle

Active

STM32F407VGT6 Key Specifications

ParameterValue
ConnectivityCANbus, DCMI, EBI/EMI, Ethernet, I2C, IrDA, LINbus, SPI, UART/USART, USB OTG
Core ProcessorARM® Cortex®-M4
Core Size32-Bit
Data ConvertersA/D 16x12b; D/A 2x12b
DigiKey ProgrammableNot Verified
Mounting TypeSurface Mount
Number of I/O82
Operating Temperature-40°C ~ 85°C (TA)
Oscillator TypeInternal
Package / Case100-LQFP
PackagingTray
PeripheralsBrown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT
Flash Memory Size1MB (1M x 8)
Program Memory TypeFLASH
RAM Size192K x 8 B
Clock Speed168MHz
Standard Pack Qty540
Supplier Device Package100-LQFP (14x14)
Supply Voltage1.8V ~ 3.6V

STM32F407VGT6 Overview

Part: STM32F407VGT6 (STM32F405xx/STM32F407xx family) — STMicroelectronics

Type: ARM Cortex-M4 32-bit MCU with FPU

Description: 32-bit Arm Cortex-M4 MCU with FPU at up to 168 MHz (210 DMIPS), up to 1 MB Flash and 192+4 KB SRAM, with USB OTG HS/FS, Ethernet, 3 ADCs and 17 timers.

Operating Conditions:

  • Supply voltage: 1.8–3.6 V (VDD); VBAT 1.65–3.6 V
  • Operating temperature: -40 to 85 °C (suffix 6; suffix 7 is -40 to 105 °C at maximum power dissipation)
  • Max HCLK: 168 MHz (VOS = 1), 144 MHz (VOS = 0); APB1 42 MHz, APB2 84 MHz

Absolute Maximum Ratings:

  • Max supply voltage (VDD–VSS): 4.0 V
  • Max input voltage on five-volt tolerant pin: VDD + 4 V; on any other pin: 4.0 V
  • Total current into VDD power lines: 240 mA; out of VSS lines: 240 mA
  • Max current sunk or sourced by any I/O pin: 25 mA
  • Max junction temperature: 125 °C
  • Storage temperature: -65 to +150 °C

Key Specs:

  • VDD operating range: 1.8–3.6 V
  • VDDA: 1.8–2.4 V (ADC limited to 1.2 Msamples), 2.4–3.6 V (ADC up to 1.4 Msamples); must be at the same potential as VDD
  • VBAT backup supply: 1.65–3.6 V
  • Max HCLK: 168 MHz (VOS = 1), 144 MHz (VOS = 0)
  • Internal 1.2 V regulator output (VCAP): 1.20–1.32 V at 168 MHz, 1.08–1.20 V at 144 MHz
  • Input voltage on RST and FT pins: up to 5.5 V (2 V ≤ VDD ≤ 3.6 V), 5.2 V (VDD ≤ 2 V)
  • Power dissipation at TA = 85 °C (suffix 6): 435 mW (LQFP64), 465 mW (LQFP100), 500 mW (LQFP144), 526 mW (LQFP176), 513 mW (UFBGA176), 543 mW (WLCSP90)
  • Junction temperature range: -40 to 105 °C (suffix 6), -40 to 125 °C (suffix 7)

Features:

  • Arm Cortex-M4 with FPU, MPU, DSP instructions and ART Accelerator for 0-wait-state Flash execution
  • Up to 1 MB Flash, up to 192+4 KB SRAM (including 64 KB CCM), 512 bytes OTP
  • Flexible static memory controller (FSMC) for Compact Flash, SRAM, PSRAM, NOR and NAND
  • 3×12-bit 2.4 MSPS ADCs (up to 24 channels), 2×12-bit DACs
  • 16-stream DMA controller with FIFOs and burst support
  • Up to 17 timers
  • Up to 15 communication interfaces: 3×I²C, 4 USARTs/2 UARTs, 3 SPIs (2 with I²S), 2×CAN, SDIO
  • USB 2.0 OTG FS and USB 2.0 OTG HS/FS, 10/100 Ethernet MAC with IEEE 1588v2, 8- to 14-bit camera interface
  • True random number generator, CRC unit, 96-bit unique ID, RTC with hardware calendar
  • SWD/JTAG debug and Cortex-M4 Embedded Trace Macrocell
  • Sleep, Stop and Standby low-power modes; VBAT supply for RTC and backup registers
  • POR, PDR, PVD and BOR supervisors
  • 4–26 MHz crystal oscillator, internal 16 MHz RC (1% accuracy), 32 kHz RTC oscillator
  • Up to 140 I/O ports with interrupt capability, up to 138 5 V-tolerant I/Os

Applications:

Package:

  • LQFP64 (10 × 10 mm)
  • LQFP100 (14 × 14 mm)
  • LQFP144 (20 × 20 mm)
  • LQFP176 (24 × 24 mm)
  • UFBGA176 (10 × 10 mm)
  • WLCSP90 (4.223 × 3.969 mm)

STM32F407VGT6 Features

  • Includes ST state-of-the-art patented technology
  • Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
  • Memories
  • -Up to 1 Mbyte of flash memory
  • -Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data RAM
  • -512 bytes of OTP memory
  • -Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
  • LCD parallel interface, 8080/6800 modes
  • Clock, reset, and supply management
  • -1.8 V to 3.6 V application supply and I/Os
  • -POR, PDR, PVD and BOR
  • -4-to-26 MHz crystal oscillator
  • -Internal 16 MHz factory-trimmed RC (1% accuracy)
  • -32 kHz oscillator for RTC with calibration
  • -Internal 32 kHz RC with calibration
  • Low-power operation
  • -Sleep, Stop, and Standby modes
  • -VBAT supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM
  • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
  • 2×12-bit D/A converters
  • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
  • -10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

DS8626 Rev 11

  • 8- to 14-bit parallel camera interface up to 54 Mbytes/s
  • True random number generator
  • CRC calculation unit
  • 96-bit unique ID
  • RTC: subsecond accuracy, hardware calendar
  • All packages are ECOPACK2 compliant

Table 1. Device summary

ReferencePart number
STM32F405xxSTM32F405RG,STM32F405VG,STM32F405ZG,STM32F405OG,STM32F405OE
STM32F407xxSTM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE

Table 1. Device summary

STM32F407VGT6 Pin Configuration

PinNameTypeDescription
1PE2I/Oalt: TRACECLK, FSMC_A23, ETH_MII_TXD3, EVENTOUT
2PE3I/Oalt: TRACED0, FSMC_A19, EVENTOUT
3PE4I/Oalt: TRACED1, FSMC_A20, DCMI_D4, EVENTOUT
4PE5I/Oalt: TRACED2, FSMC_A21, TIM9_CH1, DCMI_D6, EVENTOUT
5PE6I/Oalt: TRACED3, FSMC_A22, TIM9_CH2, DCMI_D7, EVENTOUT
6VBATS
7PC13I/ORTC_OUT, RTC_TAMP1, RTC_TS
8PC14/OSC32_IN(PC14)I/OOSC32_IN
9PC15/OSC32_OUT(PC15)I/OOSC32_OUT
10VSSS
11VDDS
12PH0/OSC_INI/OPH0 (alt: EVENTOUT)
13PH1/OSC_OUTI/OPH1 (alt: EVENTOUT)
14NRSTI/O
15PC0I/Oalt: OTG_HS_ULPI_STP, EVENTOUT
16PC1I/Oalt: ETH_MDC, EVENTOUT
17PC2I/Oalt: SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, I2S2ext_SD, EVENTOUT
18PC3I/OFT (alt: SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, EVENTOUT)
19VDDS
20VSSAS
21VREF+S
22VDDAS
23PA0/WKUPI/OFT (alt: USART2_CTS, UART4_TX, ETH_MII_CRS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, EVENTOUT, ADC123_IN0, WKUP)
24PA1I/OFT (alt: USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, ETH_MII_RX_CLK, TIM5_CH2, TIM2_CH2, EVENTOUT, ADC123_IN1)
25PA2I/OFT (alt: USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO, EVENTOUT, ADC123_IN2)
26PA3I/OFT (alt: USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0, ETH_MII_COL, EVENTOUT, ADC123_IN3)
27VSSS
28VDDS
29PA4I/Oalt: SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF, I2S3_WS, EVENTOUT
30PA5I/Oalt: SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR, TIM8_CH1N, EVENTOUT
31PA6I/Oalt: SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1, TIM1_BKIN, EVENTOUT
32PA7I/Oalt: SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, TIM1_CH1N, ETH_RMII_CRS_DV, EVENTOUT
33PC4I/Oalt: ETH_RMII_RX_D0, ETH_MII_RX_D0, EVENTOUT
34PC5I/Oalt: ETH_RMII_RX_D1, ETH_MII_RX_D1, EVENTOUT
35PB0I/Oalt: TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2, TIM1_CH2N, EVENTOUT
36PB1I/Oalt: TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3, TIM1_CH3N, EVENTOUT
37PB2/BOOT1I/Oalt: EVENTOUT
38PE7I/OFT (alt: FSMC_D4, TIM1_ETR, EVENTOUT)
39PE8I/OFT (alt: FSMC_D5, TIM1_CH1N, EVENTOUT)
40PE9I/OFT (alt: FSMC_D6, TIM1_CH1, EVENTOUT)
41PE10I/OFT (alt: FSMC_D7, TIM1_CH2N, EVENTOUT)
42PE11I/OFT (alt: FSMC_D8, TIM1_CH2, EVENTOUT)
43PE12I/OFT (alt: FSMC_D9, TIM1_CH3N, EVENTOUT)
44PE13I/OFT (alt: FSMC_D10, TIM1_CH3, EVENTOUT)
45PE14I/OFT (alt: FSMC_D11, TIM1_CH4, EVENTOUT)
46PE15I/OFT (alt: FSMC_D12, TIM1_BKIN, EVENTOUT)
47PB10I/OFT (alt: SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, TIM2_CH3, EVENTOUT)
48PB11I/OFT (alt: I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_RMII_TX_EN, ETH_MII_TX_EN, TIM2_CH4, EVENTOUT)
49VCAP_1S
50VDDS
51PB12-
52PB13-
53PB14-
54PB15-
55PD8-
56PD9-
57PD10-
58PD11-
59PD12-
60PD13-
61PD14-
62PD15-
63PC6-
64PC7-
65PC8-
66PC9-
67PA8-
68PA9-
69PA10-
70PA 11-
71PA12-
72PA13-
73VCAP_2-
74VSS-
75VDD-
76PA14-
77PA15-
78PC10-
79PC11-
80PC12-
81PD0-
82PD1-
83PD2-
84PD3-
85PD4-
86PD5-
87PD6-
88PD7-
89PB3-
90PB4-
91PB5-
92PB6-
93PB7-
94BOOT0-
95PB8-
96PB9-
97PE0-
98PE1-
99VSS-
100VDD-

STM32F407VGT6 Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 37 and Table 50 , respectively.

Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .

Table 50. I/O AC characteristics (1)(2)

OSPEEDRy [1:0] bit value (1)SymbolParameterConditionsMinTypMaxUnit
00f max(IO)outMaximum frequency (3)C L = 50 pF, V DD > 2.70 V--4MHz
00f max(IO)outMaximum frequency (3)C L = 50 pF, V DD > 1.8 V--2MHz
00f max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 2.70 V--8MHz
00f max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 1.8 V--4MHz
00t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 50 pF, V DD = 1.8 V to 3.6 V--100ns
01f max(IO)outMaximum frequency (3)C L = 50 pF, V DD > 2.70 V--25MHz
01f max(IO)outMaximum frequency (3)C L = 50 pF, V DD > 1.8 V--12.5MHz
01f max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 2.70 V--50 (4)MHz
01f max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 1.8 V--20MHz
01t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 50 pF, V DD >2.7 V--10ns
01t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 50 pF, V DD > 1.8 V--20ns
01t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 10 pF, V DD > 2.70 V--6ns
01t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 10 pF, V DD > 1.8 V--10ns
10f max(IO)outMaximum frequency (3)C L = 40 pF, V DD > 2.70 V--50 (4)MHz
10f max(IO)outMaximum frequency (3)C L = 40 pF, V DD > 1.8 V--25MHz
10f max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 2.70 V--100 (4)MHz
10f max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 1.8 V--50 (4)MHz
10t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 40 pF, V DD > 2.70 V--6ns
10t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 40 pF, V DD > 1.8 V--10ns
10t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 10 pF, V DD > 2.70 V--4ns
10t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 10 pF, V DD > 1.8 V--6ns

Table 50. I/O AC characteristics (1)(2)

Table 50. I/O AC characteristics (1)(2) (continued)

OSPEEDRy [1:0] bit value (1)SymbolParameterConditionsMinTypMaxUnit
11F max(IO)outMaximum frequency (3)C L = 30 pF, V DD > 2.70 V--100 (4)MHz
11F max(IO)outMaximum frequency (3)C L = 30 pF, V DD > 1.8 V--50 (4)MHz
11F max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 2.70 V--180 (4)MHz
11F max(IO)outMaximum frequency (3)C L = 10 pF, V DD > 1.8 V--100 (4)MHz
11t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 30 pF, V DD > 2.70 V--4ns
11t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 30 pF, V DD > 1.8 V--6ns
11t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 10 pF, V DD > 2.70 V--2.5ns
11t f(IO)out / t r(IO)outOutput high to low level fall time and output low to high level rise timeC L = 10 pF, V DD > 1.8 V--4ns
-t EXTIpwPulse width of external signals detected by the EXTI controller-10--ns
  1. The maximum frequency is defined in Figure 37 .
  2. For maximum frequencies above 50 MHz, the compensation cell should be used.

Figure 37. I/O AC characteristics definition

190

STM32F407VGT6 Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 11. Voltage characteristics

SymbolRatingsMinMaxUnit
V DD -V SSExternal main supply voltage (including V DDA , V DD ) (1)-0.34.0V
V INInput voltage on five-volt tolerant pin (2)V SS -0.3V DD +4V
V INInput voltage on any other pinV SS -0.34.0V
| ∆ V DDx |Variations between different V DD power pins-50mV
|V SSX - V SS |Variations between all the different ground pins including V REF --50mV
V ESD(HBM)Electrostatic discharge voltage (human body model)see Section 6.3.14: Absolute maximum ratings (electricalsee Section 6.3.14: Absolute maximum ratings (electrical

190

Table 12. Current characteristics

SymbolRatingsMax.Unit
I VDDTotal current into V DD power lines (source) (1)240mA
I VSSTotal current out of V SS ground lines (sink) (1)240mA
I IOOutput current sunk by any I/O and control pin25mA
I IOOutput current source by any I/Os and control pin25mA
I INJ(PIN) (2)Injected current on five-volt tolerant I/O (3)-5/+0mA
I INJ(PIN) (2)Injected current on any other pin (4)±5mA
Σ I INJ(PIN) (4)Total injected current (sum of all I/O and control pins) (5)±25mA
  1. Positive injection is not possible on these I/Os. A negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
  2. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
  3. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature125°C

STM32F407VGT6 Thermal Information

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max x Θ JA )

STM32F407VGT6 Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

STM32F407VGT6 Ordering Information

MPNPackageTemperature RangePacking
(not present in provided section)nullnullnull

Ordering code legend:

  • xxx = programmed parts
  • TR = tape and reel

Variants on the same datasheet

These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.

Part NumberManufacturerPackage
STM32F405RGT6STMicroelectronics64-LQFP
STM32F407VET6STMicroelectronics100-LQFP

More part numbers on this datasheet

Their pages show this same datasheet. Some are linked through their part family rather than checked part by part, so confirm the exact part in the ordering information.

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