STM32F407IX

Part: STM32F405xx STM32F407xx, STMicroelectronics

Type: ARM Cortex-M4 32-bit MCU with FPU

Description: ARM Cortex-M4 32-bit MCU with FPU, operating up to 168 MHz, delivering 210 DMIPS, featuring up to 1 MB Flash, 192+4 KB SRAM, and extensive peripherals including USB OTG HS/FS, Ethernet, and multiple communication interfaces.

Operating Conditions:

• Supply voltage: 1.8 V to 3.6 V
• Operating temperature: -40 to +125 °C (Junction temperature)
• Max CPU frequency: 168 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V (VDD, VDDA, VDD_USB, VDD_SDIO, VDD_CAN)
• Max junction/storage temperature: +150 °C (Storage temperature)

Key Specs:

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU
• Performance: 210 DMIPS (1.25 DMIPS/MHz)
• Flash Memory: Up to 1 Mbyte
• SRAM: Up to 192+4 Kbytes (including 64 Kbyte CCM data RAM)
• ADC: 3×12-bit, 2.4 MSPS (up to 24 channels, 7.2 MSPS in triple interleaved mode)
• DAC: 2×12-bit
• Timers: Up to 17 (twelve 16-bit, two 32-bit)
• Communication Interfaces: Up to 3 I2C, 4 USARTs/2 UARTs, 3 SPIs, 2 CAN, SDIO, USB OTG HS/FS, Ethernet MAC, Camera interface

Features:

• Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory
• Memory protection unit
• Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
• Low-power operation: Sleep, Stop, and Standby modes
• True random number generator
• CRC calculation unit
• 96-bit unique ID

Package:

• UFBGA176 (10 × 10 mm)
• LQFP64 (10 × 10 mm)
• LQFP100 (14 × 14 mm)
• LQFP144 (20 × 20 mm)
• LQFP176 (24 × 24 mm)
• WLCSP90 (4.223x3.969 mm)

• Includes ST state-of-the-art patented technology
• Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -Up to 1 Mbyte of flash memory
• -Up to 192+4 Kbytes of SRAM including 64Kbyte of CCM (core coupled memory) data RAM
• -512 bytes of OTP memory
• -Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
• LCD parallel interface, 8080/6800 modes
• Clock, reset, and supply management
• -1.8 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC (1% accuracy)
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Low-power operation
• -Sleep, Stop, and Standby modes
• -VBAT supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• -10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

DS8626 Rev 11

• 8- to 14-bit parallel camera interface up to 54 Mbytes/s
• True random number generator
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar
• All packages are ECOPACK2 compliant

Table 1. Device summary

Table 1. Device summary

Figure 12. STM32F40xxx LQFP64 pinout

Figure 13. STM32F40xxx LQFP100 pinout

1. The above figure shows the package top view.

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Figure 14. STM32F40xxx LQFP144 pinout

1. The above figure shows the package top view.

Figure 15. STM32F40xxx LQFP176 pinout

1. The above figure shows the package top view.

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The definition and values of input/output AC characteristics are given in Figure 37 and Table 50 , respectively.

Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 14 .

Table 50. I/O AC characteristics (1)(2)

Table 50. I/O AC characteristics (1)(2)

Table 50. I/O AC characteristics (1)(2) (continued)

1. The maximum frequency is defined in Figure 37 .
2. For maximum frequencies above 50 MHz, the compensation cell should be used.

Figure 37. I/O AC characteristics definition

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Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 11. Voltage characteristics

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Table 12. Current characteristics

1. Positive injection is not possible on these I/Os. A negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
2. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
3. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.