STM32F103CBTx

STM32F103xC STM32F103xD STM32F103xE

Manufacturer

st

Overview

Part: STM32F103xC STM32F103xD STM32F103xE

Type: High-density performance line ARM-based 32-bit MCU

Key Specs:

  • Core: ARM 32-bit Cortex™-M3 CPU
  • Maximum Frequency: 72 MHz
  • Flash Memory: 256 to 512 Kbytes
  • SRAM: Up to 64 Kbytes
  • Application Supply Voltage: 2.0 to 3.6 V
  • A/D Converters: 3 × 12-bit, 1 μs (up to 21 channels)
  • D/A Converters: 2 × 12-bit
  • Timers: Up to 11
  • Communication Interfaces: Up to 13
  • I/O Ports: Up to 112

Features:

  • 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
  • Single-cycle multiplication and hardware division
  • Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
  • LCD parallel interface, 8080/6800 modes
  • POR, PDR, and programmable voltage

Features

  • Core: ARM 32-bit Cortex™-M3 CPU
    • 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
    • Single-cycle multiplication and hardware division

■ Memories

  • 256 to 512 Kbytes of Flash memory
  • up to 64 Kbytes of SRAM
  • Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
  • LCD parallel interface, 8080/6800 modes
  • Clock, reset and supply management
    • 2.0 to 3.6 V application supply and I/Os
    • POR, PDR, and programmable voltage detector (PVD)
    • 4-to-16 MHz crystal oscillator
    • Internal 8 MHz factory-trimmed RC
    • Internal 40 kHz RC with calibration
    • 32 kHz oscillator for RTC with calibration

■ Low power

  • Sleep, Stop and Standby modes
  • VBAT supply for RTC and backup registers
  • 3 × 12-bit, 1 μs A/D converters (up to 21 channels)
    • Conversion range: 0 to 3.6 V
    • Triple-sample and hold capability
    • Temperature sensor
  • 2 × 12-bit D/A converters
  • DMA: 12-channel DMA controller
    • Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
  • Debug mode
    • Serial wire debug (SWD) & JTAG interfaces
    • Cortex-M3 Embedded Trace Macrocell™

  • Up to 112 fast I/O ports
    • 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
  • Up to 11 timers
    • Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
    • 2 × 16-bit motor control PWM timers with dead-time generation and emergency stop
    • 2 × watchdog timers (Independent and Window)
    • SysTick timer: a 24-bit downcounter
    • 2 × 16-bit basic timers to drive the DAC
  • Up to 13 communication interfaces
    • Up to 2 × I2C interfaces (SMBus/PMBus)
    • Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
    • Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed
    • CAN interface (2.0B Active)
    • USB 2.0 full speed interface
    • SDIO interface
  • CRC calculation unit, 96-bit unique ID
  • ECOPACK® packages

Table 1. Device summary

ReferencePart number
STM32F103xCSTM32F103RC STM32F103VC
STM32F103ZC
STM32F103xDSTM32F103RD STM32F103VD
STM32F103ZD
STM32F103xESTM32F103RE STM32F103ZE
STM32F103VE

Pin Configuration

Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout

Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout

12345678910
ΑPC14-1
OSC32_IN T		PC13-
AMPER-RT		C PE2(PB9)(PB7)( PB4 )(PB3)(PA15)(PA14)(PA13)
3PC15-,
OSC32_OUT		(V BAT )(PE3)(PB8)(PB6)(PD5)(PD2)(PC11)(PC10)(PA12)
COSC_INV SS_5(PE4)(PE1)(PB5)(PD6)(PD3)(PC12)(PA9)(PA11)
OOSC_OUTV DD_5(PE5)(PEO)вooтo(PD7)(PD4)(PDO)(PA8)(PA10)
E(NRST)(PC2)(PE6)V SS_4'Vss_3V SS_2(V SS_1 )(PD1)PC9(PC7)
F(PCO)(PC1)(PC3)V DD_4V DD_3V DD_2V DD_1 ,(NC)PC8PC6
G(Vssa)PÁO-WKŲP(PA4)PC4(PB2)(PE10)(PE14)(PB15)(PD11)(PD15)
HV REF(PA1)(PA5)PC5(PE7)(PE11)(PE15)(PB14)(PD10)(PD14)
JVREF+PA2(PA6)(PBO)(PE8)(PE12)(PB10)(PB13)PD9(PD13)
KV DDA ,(PA3)(PA7)(PB1)(PE9)(PE13)(PB11)(PB12)(PD8)(PD12)

Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout

Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 4948 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 LQFP64 ai14392

Figure 7. STM32F103xC and STM32F103xE performance line LQFP64 pinout

Figure 8. STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side

Table 5. High-density STM32F103xx pin definitions

PinsAlternate functions(4)
LFBGA144LFBGA100WLCSP64LQFP64LQFP100LQFP144Pin nameType(1)I / O Level(2)Main
function(3)
(after reset)		Default
A3A3--11PE2I/O FTPE2TRACECK/ FSMC_A23
A2B3--22PE3I/O FTPE3TRACED0/FSMC_A19
B2C3--33PE4I/O FTPE4TRACED1/FSMC_A20
B3D3--44PE5I/O FTPE5TRACED2/FSMC_A21
B4E3--55PE6I/O FTPE6TRACED3/FSMC_A22
C2B2C6166VBATSVBAT
A1A2C8277PC13-TAMPER
RTC(5)		I/OPC13(6)TAMPER-RTC
B1A1B8388PC14-
OSC32_IN(5)		I/OPC14(6)OSC32_IN
C1B1B7499PC15-
OSC32_OUT(5)		I/OPC15(6)OSC32_OUT
C3----10PF0I/O FTPF0FSMC_A0
C4----11PF1I/O FTPF1FSMC_A1
D4----12PF2I/O FTPF2FSMC_A2
E2----13PF3I/O FTPF3FSMC_A3
E3----14PF4I/O FTPF4FSMC_A4
E4----15PF5I/O FTPF5FSMC_A5
D2C2--1016VSS_5SVSS_5
D3D2--1117VDD_5SVDD_5
F3----18PF6I/OPF6ADC3_IN4/FSMC_NIORD
F2----19PF7I/OPF7ADC3_IN5/FSMC_NREG
G3----20PF8I/OPF8ADC3_IN6/FSMC_NIOWR
G2----21PF9I/OPF9ADC3_IN7/FSMC_CD
G1----22PF10I/OPF10ADC3_IN8/FSMC_INTR
D1C1D851223OSC_INIOSC_IN
E1D1D761324OSC_OUTOOSC_OUT
F1E1C771425NRSTI/ONRST
H1F1E881526PC0I/OPC0ADC123_IN10
H2F2F891627PC1I/OPC1ADC123_IN11
H3E2D6101728PC2I/OPC2ADC123_IN12
H4F3-111829PC3I/OPC3ADC123_IN13
J1G1E7121930VSSASVSSA
Table 5. High-density STM32F103xx pin definitions (continued)
PinsAlternate functions(4)
LFBGA144LFBGA100WLCSP64LQFP64LQFP100LQFP144Pin nameType(1)I / O Level(2)Main
function(3)
(after reset)		Default
K1H1--2031VREF-SVREF
L1J1F7
(7)		-2132VREF+SVREF+
M1K1G8132233VDDASVDDA
J2G2F6142334PA0-WKUPI/OPA0WKUP/USART2_CTS(8)
ADC123_IN0
TIM2_CH1_ETR
TIM5_CH1/TIM8_ETR
K2H2E6152435PA1I/OPA1USART2_RTS(8)
ADC123_IN1/
TIM5_CH2/TIM2_CH2(8)
L2J2H8162536PA2I/OPA2USART2_TX(8)/TIM5_CH3
ADC123_IN2/
TIM2_CH3 (8)
M2K2G7172637PA3I/OPA3USART2_RX(8)/TIM5_CH4
ADC123_IN3/TIM2_CH4(8)
G4E4F5182738VSS_4SVSS_4
F4F4G6192839VDD_4SVDD_4
J3G3H7202940PA4I/OPA4SPI1_NSS(8)/
USART2_CK(8)
DAC_OUT1/ADC12_IN4
K3H3E5213041PA5I/OPA5SPI1_SCK(8)
DAC_OUT2 ADC12_IN5
L3J3G5223142PA6I/OPA6SPI1_MISO(8)
TIM8_BKIN/ADC12_IN6
TIM3_CH1(8)
M3K3G4233243PA7I/OPA7SPI1_MOSI(8)/
TIM8_CH1N/ADC12_IN7
TIM3_CH2(8)
J4G4H6243344PC4I/OPC4ADC12_IN14
K4H4H5253445PC5I/OPC5ADC12_IN15
L4J4H4263546PB0I/OPB0ADC12_IN8/TIM3_CH3
TIM8_CH2N
M4K4F4273647PB1I/OPB1ADC12_IN9/TIM3_CH4(8)
TIM8_CH3N
J5G5H3283748PB2I/O FTPB2/BOOT1
M5----49PF11I/O FTPF11FSMC_NIOS16
L5----50PF12I/O FTPF12FSMC_A6
Table 5. High-density STM32F103xx pin definitions (continued)
e J.Piry 31W32F103XAlternate functions (4)
LFBGA144LFBGA100WLCSP64LQFP64LQFP100LQFP144Pin nameType (1)I / O Level (2)Main
function (3)
(after reset)		DefaultRemap
H5-11-51Vrm SS6SVSS6
G5----52VDD6SVDD6
K5----53PF13I/OFTPF13FSMC_A7
M6--ıı54PF14I/OFTPF14FSMC_A8
L6-1ıı55PF15I/OFTPF15FSMC_A9
K611-56PG0I/OFTPG0FSMC_A10
J6----57PG1I/OFTPG1FSMC_A11
M7H5-3858PE7I/OFTPE7FSMC_D4TIM1_ETR
L7J5--3959PE8I/OFTPE8FSMC_D5TIM1_CH1N
K7K5-4060PE9I/OFTPE9FSMC_D6TIM1_CH1
H6---61V SS_7SV SS_7
G6---62V DD_7SV DD_7
J7G6-4163PE10I/OFTPE10FSMC_D7TIM1_CH2N
H8H6-14264PE11I/OFTPE11FSMC_D8TIM1_CH2
J8J6-14365PE12I/OFTPE12FSMC_D9TIM1_CH3N
K8K6-14466PE13I/OFTPE13FSMC_D10TIM1_CH3
L8G7--4567PE14I/OFTPE14FSMC_D11TIM1_CH4
M8H7-14668PE15I/OFTPE15FSMC_D12TIM1_BKIN
M9J7G3294769PB10I/OFTPB10I2C2_SCL/USART3_TX (8)TIM2_CH3
M10K7F3304870PB11I/OFTPB11I2C2_SDA/USART3_RX (8)TIM2_CH4
H7E7H2314971V SS_1SV SS_1
G7F7H1325072V DD_1SV DD_1
M11K8G2335173PB12I/OFTPB12SPI2_NSS/I2S2_WS/
I2C2_SMBA/
USART3_CK (8) /
TIM1_BKIN (8)
M12J8G1345274PB13I/OFTPB13SPI2_SCK/I2S2_CK
USART3_CTS (8) /
TIM1_CH1N
L11H8F2355375PB14I/OFTPB14SPI2_MISO/TIM1_CH2N
USART3_RTS (8) /
L12G8F1365476PB15I/OFTPB15SPI2_MOSI/I2S2_SD
TIM1_CH3N (8) /
L9K9-ı5577PD8I/OFTPD8FSMC_D13USART3_TX
K9J9-•5678PD9I/OFTPD9FSMC_D14USART3_RX

Table 5. High-density STM32F103xx pin definitions (continued)

PinsAlternate functions(4)
LFBGA144LFBGA100WLCSP64LQFP64LQFP100LQFP144Pin nameType(1)I / O Level(2)Main
function(3)
(after reset)		Default
J9H9--5779PD10I/O FTPD10FSMC_D15
H9G9--5880PD11I/O FTPD11FSMC_A16
L10 K10--5981PD12I/O FTPD12FSMC_A17
K10 J10--6082PD13I/O FTPD13FSMC_A18
G8----83VSS_8SVSS_8
F8----84VDD_8SVDD_8
K11 H10--6185PD14I/O FTPD14FSMC_D0
K12 G10--6286PD15I/O FTPD15FSMC_D1
J12----87PG2I/O FTPG2FSMC_A12
J11----88PG3I/O FTPG3FSMC_A13
J10----89PG4I/O FTPG4FSMC_A14
H12----90PG5I/O FTPG5FSMC_A15
H11----91PG6I/O FTPG6FSMC_INT2
H10----92PG7I/O FTPG7FSMC_INT3
G11----93PG8I/O FTPG8
G10----94VSS_9SVSS_9
F10----95VDD_9SVDD_9
G12 F10 E1376396PC6I/O FTPC6I2S2_MCK/
TIM8_CH1/SDIO_D6
F12 E10 E2386497PC7I/O FTPC7I2S3_MCK/
TIM8_CH2/SDIO_D7
F11F9E3396598PC8I/O FTPC8TIM8_CH3/SDIO_D0
E11E9D1406699PC9I/O FTPC9TIM8_CH4/SDIO_D1
E12D9E44167 100PA8I/O FTPA8USART1_CK/
TIM1_CH1(8)/MCO
D12C9D24268 101PA9I/O FTPA9USART1_TX(8)/
TIM1_CH2(8)
D11 D10 D34369 102PA10I/O FTPA10USART1_RX(8)/
TIM1_CH3(8)
C12 C10 C14470 103PA11I/O FTPA11USART1_CTS/USBDM
CAN_RX(8)/TIM1_CH4(8)
B12 B10 C24571 104PA12I/O FTPA12USART1_RTS/USBDP/
CAN_TX(8)/TIM1_ETR(8)
Table 5. High-density STM32F103xx pin definitions (continued)
PinsAlternate functions(4)
LFBGA144LFBGA100WLCSP64LQFP64LQFP100LQFP144Pin nameType(1)I / O Level(2)Main
function(3)
(after reset)		Default
A12 A10 D44672 105PA13I/O FTJTMS
SWDIO
C11F8--73 106Not connected
G9E6B14774 107VSS_2SVSS_2
F9F6A14875 108VDD_2SVDD_2
A11A9B24976 109PA14I/O FTJTCK
SWCLK
A10A8C35077 110PA15I/O FTJTDISPI3_NSS/
I2S3_WS
B11B9A25178 111PC10I/O FTPC10UART4_TX/SDIO_D2
B10B8B35279 112PC11I/O FTPC11UART4_RX/SDIO_D3
C10C8C45380 113PC12I/O FTPC12UART5_TX/SDIO_CK
E10D8D8581 114PD0I/O FTOSC_IN(9)FSMC_D2(10)
D10E8D7682 115PD1I/O FT OSC_OUT(9)FSMC_D3(10)
E9B7A35483 116PD2I/O FTPD2TIM3_ETR/UART5_RX
SDIO_CMD
D9C7--84 117PD3I/O FTPD3FSMC_CLK
C9D7--85 118PD4I/O FTPD4FSMC_NOE
B9B6--86 119PD5I/O FTPD5FSMC_NWE
E7----120VSS_10SVSS_10
F7----121VDD_10SVDD_10
A8C6--87 122PD6I/O FTPD6FSMC_NWAIT
A9D6--88 123PD7I/O FTPD7FSMC_NE1/FSMC_NCE2
E8----124PG9I/O FTPG9FSMC_NE2/FSMC_NCE3
D8----125PG10I/O FTPG10FSMC_NCE4_1/
FSMC_NE3
C8----126PG11I/O FTPG11FSMC_NCE4_2
B8----127PG12I/O FTPG12FSMC_NE4
D7----128PG13I/O FTPG13FSMC_A24
C7----129PG14I/O FTPG14FSMC_A25
E6----130VSS_11SVSS_11
F6----131VDD_11SVDD_11
B7----132PG15I/O FTPG15
A7 A7 A4 55 89 133 PB3 I/O FT JTDO SPI3_SCK / I2S3_CK/ PB3/TRACESWO TIM2_CH2 / SPI1_SCK A6 A6 B4 56 90 134 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1 SPI1_MISO B6 C5 A5 57 91 135 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI I2S3_SD TIM3_CH2 / SPI1_MOSI C6 B5 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL(8)/ TIM4_CH1(8) USART1_TX D6 A5 C5 59 93 137 PB7 I/O FT PB7 I2C1_SDA(8) / FSMC_NADV / TIM4_CH2(8) USART1_RX D5 D5 A6 60 94 138 BOOT0 I BOOT0 C5 B4 D5 61 95 139 PB8 I/O FT PB8 TIM4_CH3(8)/SDIO_D4 I2C1_SCL/ CAN_RX B5 A4 B6 62 96 140 PB9 I/O FT PB9 TIM4_CH4(8)/SDIO_D5 I2C1_SDA / CAN_TX A5 D4 - - 97 141 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0 A4 C4 - - 98 142 PE1 I/O FT PE1 FSMC_NBL1 E5 E5 A7 63 99 143 VSS_3 S VSS_3 Pins Pin name Type(1) I / O Level(2) Main function(3) (after reset) Alternate functions(4) LFBGA144 LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Default Remap

Table 5. High-density STM32F103xx pin definitions (continued)

F5 F5 A8 64 100 144 VDD_3 S VDD_3

    1. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
    1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
    1. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
    1. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The VREF+ functionality is provided instead.
    1. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
    1. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
    1. For devices delivered in LQFP64 packages, the FSMC function is not available.

1. I = input, O = output, S = supply.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

Table 6. FSMC pin definition

Table 6.FSMC pin definition
PinsCFCF/IDE
PE2
PE3
PE4
PE5
PE6
PF0A0A0
PF1A1A1
PF2A2A2
PF3A3
PF4A4
PF5A5
PF6NIORDNIORD
PF7NREGNREG
PF8NIOWRNIOWR
PF9CDCD
PF10INTRINTR
PF11NIOS16NIOS16
PF12A6
PF13A7
PF14A8
PF15A9
PG0A10
PG1
PE7D4D4
PE8D5D5
PE9D6D6
PE10D7D7
PE11D8D8
PE12D9D9
PE13D10D10
PE14D11D11
PE15D12D12
PD8D13D13

Table 6. FSMC pin definition (continued)

FSMC
PinsCFCF/IDENOR/PSRAM/
SRAM
PD9D14D14D14
PD10D15D15D15
PD11A16
PD12A17
PD13A18
PD14D0D0D0
PD15D1D1D1
PG2A12
PG3A13
PG4A14
PG5A15
PG6
PG7
PD0D2D2D2
PD1D3D3D3
PD3CLK
PD4NOENOENOE
PD5NWENWENWE
PD6NWAITNWAITNWAIT
PD7NE1
PG9NE2
PG10NCE4_1NCE4_1NE3
PG11NCE4_2NCE4_2
PG12NE4
PG13A24
PG14A25
PB7NADV
PE0NBL0
PE1NBL1

1. Ports F and G are not available in devices delivered in 100-pin packages.

Electrical Characteristics

The definition and values of input/output AC characteristics are given in Figure 46 and Table 48, respectively.

Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10.

Table 48. I/O AC characteristics(1)

MODEx[1:0]
bit value(1)		SymbolParameterConditionsMinMaxUnit
fmax(IO)outMaximum frequency(2)CL = 50 pF, VDD = 2 V to 3.6 V2MHz
10tf(IO)outOutput high to low
level fall time		125(3)ns
tr(IO)outOutput low to high
level rise time		CL = 50 pF, VDD = 2 V to 3.6 V125(3)
fmax(IO)outMaximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V10MHz
01tf(IO)outOutput high to low
level fall time		25(3)
tr(IO)outOutput low to high
level rise time		CL = 50 pF, VDD = 2 V to 3.6 V25(3)ns
CL = 30 pF, VDD = 2.7 V to 3.6 V50MHz
Fmax(IO)outMaximum frequency(2)CL = 50 pF, VDD = 2.7 V to 3.6 V30MHz
CL = 50 pF, VDD = 2 V to 2.7 V20MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V5(3)
11tf(IO)outOutput high to low
level fall time		CL = 50 pF, VDD = 2.7 V to 3.6 V8(3)
CL = 50 pF, VDD = 2 V to 2.7 V12(3)ns
CL = 30 pF, VDD = 2.7 V to 3.6 V5(3)
tr(IO)outOutput low to high
level rise time		CL = 50 pF, VDD = 2.7 V to 3.6 V8(3)
CL = 50 pF, VDD = 2 V to 2.7 V12(3)
-tEXTIpwPulse width of
external signals
detected by the EXTI
controller		10ns

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 46.

3. Guaranteed by design, not tested in production.

ai14131 10% 90% 50% t r(IO)out OUTPUT EXTERNAL ON 50pF Maximum frequency is achieved if (tr + tf ) ≤ 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T t r(IO)out

Figure 46. I/O AC characteristics definition

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 7. Voltage characteristics

SymbolRatingsMinMaxUnit
VDD–VSSExternal main supply voltage (including VDDA
(1)
and VDD)		–0.34.0
Input voltage on five volt tolerant pinVSS - 0.3VDD + 4.0V
VIN(2)Input voltage on any other pinVSS
- 0.3		4.0
ΔVDDxVariations between different VDD power pins50
VSSX - VSSVariations between all the different ground pins50mV
VESD(HBM)Electrostatic discharge voltage (human body
model)		see Section 5.3.12:
Absolute maximum ratings
(electrical sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

Table 8. Current characteristics

SymbolRatingsMax.Unit
IVDDTotal current into VDD/VDDA power lines (source)(1)150
IVSSTotal current out of VSS ground lines (sink)(1)150
Output current sunk by any I/O and control pin25
IIOOutput current source by any I/Os and control pin- 25mA
Injected current on five volt tolerant pins(3)-5/+0
IINJ(PIN)(2)Injected current on any other pin(4)± 5
ΣIINJ(PIN)Total injected current (sum of all I/O and control pins)(5)± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.
    1. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.
    1. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum allowed injected current values.

2. Negative injection disturbs the analog performance of the device. See note 3 below Table 62 on page 105.

3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 7: Voltage characteristics for the maximum allowed input voltage values.

Table 9. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature150°C

Thermal Information

The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 42.

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:TJ max = TA max + (PD max x ΘJA)$

Where:

  • TA max is the maximum ambient temperature in °C,
  • ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
  • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
  • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

$PI/O max = Sigma (VOL × IOL) + Sigma ((VDD - VOH) × IOH),$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Table 73. Package thermal characteristics

SymbolParameterValueUnit
Thermal resistance junction-ambient
LFBGA144 - 10 × 10 mm / 0.8 mm pitch		40
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch		30
Thermal resistance junction-ambient
LFBGA100 - 10 × 10 mm / 0.8 mm pitch		40
ΘJAThermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch		46°C/W
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch		45
Thermal resistance junction-ambient
WLCSP64		50

6.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org

6.2.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 74: Ordering information scheme.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F103xC, STM32F103xD and STM32F103xE at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T_{Amax}=82~^{\circ}C (measured according to JESD51-2), I_{DDmax}=50 mA, V_{DD}=3.5 V, maximum 20 I/Os used at the same time in output at low level with I_{OL}=8 mA, V_{OL}=0.4 V and maximum 8 I/Os used at the same time in output at low level with I_{OL}=20 mA, V_{OL}=1.3 V

$PINTmax = 50 mA × 3.5 V = 175 mW$

$PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW$

$PDmax = 175 + 272 = 447 mW$

Thus: PDmax = 447 mW

Using the values obtained in Table 73 T.lmax is calculated as follows:

    For LQFP100, 46 °C/W

$TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C$

This is within the range of the suffix 6 version parts ( $-40 < T_{.1} < 105$ °C).

In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 74: Ordering information scheme).

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature $T_J$ remains within the specified range.

Assuming the following application conditions:

Maximum ambient temperature T_{Amax} = 115 °C (measured according to JESD51-2), I_{DDmax} = 20 mA, V_{DD} = 3.5 V, maximum 20 I/Os used at the same time in output at low level with I_{OL} = 8 mA, V_{OL} = 0.4 V

$PINTmax = 20 mA × 3.5 V = 70 mW$

$PIOmax = 20 × 8 mA × 0.4 V = 64 mW$

This gives: PINTmax = 70 mW and PIOmax = 64 mW:

$PDmax = 70 + 64 = 134 mW$

Using the values obtained in Table 73 TJmax is calculated as follows:

– For LQFP100, 46 °C/W

$TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C$

This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).

In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 74: Ordering information scheme).

Figure 73. LQFP100 PD max vs. TA

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