STM32F103C4

Part: STM32F103x4, STM32F103x6 from STMicroelectronics

Type: ARM-based 32-bit Microcontroller (MCU)

Description: ARM Cortex-M3 32-bit RISC core MCU operating at up to 72 MHz, with 16 or 32 KB Flash memory, 6 or 10 KB SRAM, featuring USB, CAN, 6 timers, 2 ADCs, and 6 communication interfaces.

Operating Conditions:

• Supply voltage: 2.0 to 3.6 V
• Operating temperature: -40 to +105 °C
• Max CPU frequency: 72 MHz
• ADC conversion range: 0 to 3.6 V

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V (VDD - VSS)
• Max junction/storage temperature: +125 °C

Key Specs:

• CPU Core: ARM 32-bit Cortex-M3
• Max CPU Frequency: 72 MHz
• Flash Memory: 16 or 32 Kbytes
• SRAM: 6 or 10 Kbytes
• A/D Converters: 2 x 12-bit, 1 μs (up to 16 channels)
• DMA Controller: 7-channel
• I/O Ports: Up to 51 fast I/O ports, almost all 5 V-tolerant
• Communication Interfaces: 1x I2C, 2x USARTs, 1x SPI, CAN, USB 2.0 full-speed

Features:

• Single-cycle multiplication and hardware division
• POR, PDR, and programmable voltage detector (PVD)
• Low power modes: Sleep, Stop and Standby
• Serial wire debug (SWD) & JTAG interfaces
• CRC calculation unit, 96-bit unique ID

Applications:

• Motor drives
• Application control
• Medical and handheld equipment
• PC and gaming peripherals
• GPS platforms
• Industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs

Package:

• VFQFPN36 (36-pin, 6x6 mm)
• UFQFPN48 (48-lead, 7x7 mm)
• LQFP64 (64-pin, 10 x 10 mm)
• TFBGA64 (64-ball, 5 x 5 mm)
• LQFP48 (48-pin, 7 x 7 mm)

• ARM 32-bit Cortex™-M3 CPU Core
  • 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
  • Single-cycle multiplication and hardware division
• Memories
  • 16 or 32 Kbytes of Flash memory
  • 6 or 10 Kbytes of SRAM
• Clock, reset and supply management
  • 2.0 to 3.6 V application supply and I/Os
  • POR, PDR, and programmable voltage detector (PVD)
  • 4-to-16 MHz crystal oscillator
  • Internal 8 MHz factory-trimmed RC
  • Internal 40 kHz RC
  • PLL for CPU clock
  • 32 kHz oscillator for RTC with calibration
• Low power
  • Sleep, Stop and Standby modes
  • VBAT supply for RTC and backup registers
• 2 x 12-bit, 1 μs A/D converters (up to 16 channels)
  • Conversion range: 0 to 3.6 V
  • Dual-sample and hold capability
  • Temperature sensor
• DMA
  • 7-channel DMA controller
  • Peripherals supported: timers, ADC, SPIs, I 2Cs and USARTs
• Up to 51 fast I/O ports
  • 26/37/51 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant

• Debug mode
  • Serial wire debug (SWD) & JTAG interfaces
• 6 timers
  • Two 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
  • 16-bit, motor control PWM timer with deadtime generation and emergency stop
  • 2 watchdog timers (Independent and Window)
  • SysTick timer 24-bit downcounter
• 6 communication interfaces
  • 1 x I2C interface (SMBus/PMBus)
  • 2 × USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
  • 1 × SPI (18 Mbit/s)
  • CAN interface (2.0B Active)
  • USB 2.0 full-speed interface
• CRC calculation unit, 96-bit unique ID
• • Packages are ECOPACK®

Table 1. Device summary

Reference	Part number
STM32F103x4	STM32F103C4, STM32F103R4, STM32F103T4
STM32F103x6	STM32F103C6, STM32F103R6, STM32F103T6

Figure 3. STM32F103xx performance line LQFP64 pinout

Figure 4. STM32F103xx performance line TFBGA64 ballout

Figure 5. STM32F103xx performance line LQFP48 pinout

Figure 7. STM32F103xx performance line VFQFPN36 pinout

Table 5. Low-density STM32F103xx pin definitions

LQFP48/ UFQFPN48	LQFP64	TFBGA64	VFQFPN36	Pin name	Type(1)	I/O Level(2)	Main function(3) (after reset)	Default	Remap
1	1	B2	-	VBAT	S	-	VBAT	-	-
2	2	A2	-	PC13-TAMPER-RTC(5)	I/O	-	PC13(6)	TAMPER-RTC	-
3	3	A1	-	PC14-OSC32_IN(5)	I/O	-	PC14(6)	OSC32_IN	-
4	4	B1	-	PC15-OSC32_OUT(5)	I/O	-	PC15(6)	OSC32_OUT	-
5	5	C1	2	OSC_IN	I	-	OSC_IN	-	PD0(7)
6	6	D1	3	OSC_OUT	O	-	OSC_OUT	-	PD1(7)
18	26	F5	15	PB0	I/O	-	PB0	ADC12_IN8/TIM3_CH3$^{(9)}$	TIM1_CH2N
19	27	G5	16	PB1	I/O	-	PB1	ADC12_IN9/TIM3_CH4$^{(9)}$	TIM1_CH3N
20	28	G6	17	PB2	I/O	FT	PB2/BOOT1	-	-
21	29	G7	-	PB10	I/O	FT	PB10	-	TIM2_CH3
22	30	H7	-	PB11	I/O	FT	PB11	-	TIM2_CH4
23	31	D6	18	VSS_1	S	-	VSS_1	-	-
24	32	E6	19	VDD_1	S	-	VDD_1	-	-
25	33	H8	-	PB12	I/O	FT	PB12	TIM1_BKIN$^{(9)}$	-
26	34	G8	-	PB13	I/O	FT	PB13	TIM1_CH1N$^{(9)}$	-
27	35	F8	-	PB14	I/O	FT	PB14	TIM1_CH2N$^{(9)}$	-
28	36	F7	-	PB15	I/O	FT	PB15	TIM1_CH3N$^{(9)}$	-
-	37	F6	-	PC6	I/O	FT	PC6	-	TIM3_CH1
-	38	E7	-	PC7	I/O	FT	PC7	-	TIM3_CH2
-	39	E8	-	PC8	I/O	FT	PC8	-	TIM3_CH3
-	40	D8	-	PC9	I/O	FT	PC9	-	TIM3_CH4
29	41	D7	20	PA8	I/O	FT	PA8	USART1_CK/ TIM1_CH1/MCO	-
30	42	C7	21	PA9	I/O	FT	PA9	USART1_TX$^{(9)}$/ TIM1_CH2$^{(9)}$	-
31	43	C6	22	PA10	I/O	FT	PA10	USART1_RX$^{(9
7	7	E1	4	NRST	I/O	-	NRST	-	-
-	8	E3	-	PC0	I/O	-	PC0	ADC12_IN10	-
-	9	E2	-	PC1	I/O	-	PC1	ADC12_IN11	-
-	10	F2	-	PC2	I/O	-	PC2	ADC12_IN12	-
-	11	-	-	PC3	I/O	-	PC3	ADC12_IN13	-
-	-	G1	-	VREF+(

Table 5. Low-density STM32F103xx pin definitions (continued)

	Pins							Alternate functions(4)
UFQFPN48 LQFP48/	LQFP64	TFBGA64	VFQFPN36	Pin name	Type(1)	I / O Level(2)	Main function(3) (after reset)	Default
18	26	F5	15	PB0	I/O	-	PB0	ADC12_IN8/TIM3_CH3(9)
19	27	G5	16	PB1	I/O	-	PB1	ADC12_IN9/TIM3_CH4(9)
20	28	G6	17	PB2	I/O	FT	PB2/BOOT1	-
21	29	G7	-	PB10	I/O	FT	PB10	-
22	30	H7	-	PB11	I/O	FT	PB11	-
23	31	D6	18	VSS_1	S	-	VSS_1	-
24	32	E6	19	VDD_1	S	-	VDD_1	-
25	33	H8	-	PB12	I/O	FT	PB12	TIM1_BKIN(9)
26	34	G8	-	PB13	I/O	FT	PB13	TIM1_CH1N (9)
27	35	F8	-	PB14	I/O	FT	PB14	TIM1_CH2N (9)
28	36	F7	-	PB15	I/O	FT	PB15	TIM1_CH3N(9)
-	37	F6	-	PC6	I/O	FT	PC6	-
-	38	E7	-	PC7	I/O	FT	PC7	-
-	39	E8	-	PC8	I/O	FT	PC8	-
-	40	D8	-	PC9	I/O	FT	PC9	-
29	41	D7	20	PA8	I/O	FT	PA8	USART1_CK/ TIM1_CH1/MCO
30	42	C7	21	PA9	I/O	FT	PA9	USART1_TX(9)/ TIM1_CH2(9)
31	43	C6	22	PA10	I/O	FT	PA10	USART1_RX(9)/ TIM1_CH3
32	44	C8	23	PA11	I/O	FT	PA11	USART1_CTS/ CAN_RX(9)/ TIM1_CH4 / USBDM
33	45	B8	24	PA12	I/O	FT	PA12	USART1_RTS/ CAN_TX(9) / TIM1_ETR / USBDP
34	46	A8	25	PA13	I/O	FT	JTMS/SWDIO
35	47	D5	26	VSS_2	S	-	VSS_2	-
36	48	E5	27	VDD_2	S	-	VDD_2	-
37	49	A7	28	PA14	I/O	FT	JTCK/SWCLK	-
38	50	A6	29	PA15	I/O	FT	JTDI	-
-	51	B7	-	PC10	I/O	FT	PC10	-
-	52	B6	-	PC11	I/O	FT	PC11	-
-	53	C5	-	PC12	I/O	FT	PC12	-
-	-	C1	2	PD0	I/O	FT	PD0	-

• • D1 3 PD1 I/O FT PD1 - - - 54 B5 - PD2 I/O FT PD2 TIM3_ETR - 39 55 A5 30 PB3 I/O FT JTDO - TIM2_CH2 / PB3/ TRACESWO 40 56 A4 31 PB4 I/O FT NJTRST - TIM3_CH1 /PB4 SPI1_MISO 41 57 C4 32 PB5 I/O - PB5 I2C1_SMBA TIM3_CH2 / SPI1_MOSI 42 58 D3 33 PB6 I/O FT PB6 I2C1_SCL(9)/ USART1_TX 43 59 C3 34 PB7 I/O FT PB7 I2C1_SDA(9) USART1_RX 44 60 B4 35 BOOT0 I - BOOT0 - - 45 61 B3 - PB8 I/O FT PB8 - I2C1_SCL /CAN_RX 46 62 A3 - PB9 I/O FT PB9 - I2C1_SDA / CAN_TX 47 63 D4 36 VSS_3 S- VSS_3 - - 48 64 E4 1 VDD_3 S- VDD_3 - - Pins Pin name Type(1) I / O Level(2) Main function(3) (after reset) Alternate functions(4) LQFP48/ UFQFPN48 LQFP64 TFBGA64 VFQFPN36 Default Remap

Table 5. Low-density STM32F103xx pin definitions (continued)

• 1. I = input, O = output, S = supply.
• 1. FT = 5 V tolerant.
• 1. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 11.
• 1. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
• 1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
• 1. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
• 1. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48, UFQFPN48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
• 1. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
• 1. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to V_SS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T_A = 25 °C and T_A = T_A max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3o).

5.1.2 Typical values

Unless otherwise specified, typical data are based on T_A = 25 °C, V_DD = 3.3 V (for the 2 V ≤ V _DD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 sigma ).

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD - VSS	External main supply voltage (including VDDA and VDD)(1)	–0.3	4.0	V
VIN(2)	Input voltage on five volt tolerant pin	VSS - 0.3	VDD + 4.0	V
	Input voltage on any other pin	VSS -0.3	4.0	V
|ΔVDDx|	Variations between different VDD power pins	-	50	mV
|VSSX -VSS|	Variations between all the different ground pins	-	50	mV
VESD(HBM)	Electrostatic discharge voltage (human body model)		see Section 5.3.11: Absolute maximum ratings (electrical sensitivity)	-

^1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

^2. VIN maximum must always be respected. Refer to Table 7: Current characteristics for the maximum allowed injected current values.

Symbol Max. Unit Ratings Total current into V_DD/V_DDA power lines (source)⁽¹⁾ 150I_{VDD}$ Total current out of V_SS ground lines (sink)⁽¹⁾ 150 $I_{VSS}$ Output current sunk by any I/O and control pin 25 $I_{10}$ Output current source by any I/Os and control pin -25 mΑ Injected current on five volt tolerant pins(3) -5/+0 I_INJ(PIN)⁽²⁾ Injected current on any other pin⁽⁴⁾ ± 5 Total injected current (sum of all I/O and control pins)(5) ± 25 $\Sigma I_{INJ(PIN)}Table 7. Current characteristics

• All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power supply, in the permitted range.
• 1. Negative injection disturbs the analog performance of the device. See note 2. on page 71.
• Positive injection is not possible on these I/Os. A negative injection is induced by V_IN<V_SS. I_INJ(PIN) must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values.
• 1. A positive injection is induced by V_IN>V_DD while a negative injection is induced by V_IN<V_SS. I_INJ(PIN) must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values
• When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 8. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	150	°C

The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 33.

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:

TJ max = TA max + (PD max × ΘJA)

Where:

• TA max is the maximum ambient temperature in ° C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:P_I/O max = Sigma (V_OL × I_OL) + Sigma((V_DD - V_OH) × I_OH),$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

• Symbol Parameter Value Unit
• Thermal resistance junction-ambient
  TFBGA64 - 5 × 5 mm / 0.5 mm pitch 65
• Thermal resistance junction-ambient
  LQFP64 - 10 × 10 mm / 0.5 mm pitch 45
• ΘJA Thermal resistance junction-ambient
  LQFP48 - 7 × 7 mm / 0.5 mm pitch 55 °C/W
• Thermal resistance junction-ambient
  UFQFPN 48 -7 × 7 mm / 0.5 mm pitch 32
• Thermal resistance junction-ambient
  VFQFPN 36 - 6 × 6 mm / 0.5 mm pitch 18

Table 57. Package thermal characteristics

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

6.1 VFQFPN36 Package

Figure 38. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline

1. Drawing is not to scale.

Table 51. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data

		millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ	Max
A	0.800	0.900	1.000	0.0315	0.0354	0.0394
A1	-	0.020	0.050	-	0.0008	0.0020
A2	-	0.650	1.000	-	0.0256	0.0394
A3	-	0.200	-	-	0.0079	-
b	0.180	0.230	0.300	0.0071	0.0091	0.0118
D	5.875	6.000	6.125	0.2313	0.2362	0.2411
D2	1.750	3.700	4.250	0.0689	0.1457	0.1673
E	5.875	6.000	6.125	0.2313	0.2362	0.2411
E2	1.750	3.700	4.250	0.0689	0.1457	0.1673
e	0.450	0.500	0.550	0.0177	0.0197	0.0217
L	0.350	0.550	0.750	0.0138	0.0217	0.0295
K	0.250	-	-	0.0098	-	-
ddd	-	-	0.080	-	-	0.0031

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 39. VFQFPN36 - 36-pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint

1. Dimensions are expressed in millimeters.

Device Marking for VFQFPN36

The following figure gives an example of topside marking orientation versus ball 1 identifier location.

Figure 40. VFQFPN36 marking example (package view)

1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.