PIC24FJ128GL306

Part: PIC24FJ128GL306 (PIC24FJ128GL30x / PIC24FJ64GL30x family)

Type: 16-bit Low-Power Microcontroller with LCD Controller

Description: 16-bit PIC24F MCU with up to 16 MIPS at 32 MHz, 128 KB Flash with ECC, 8 KB SRAM, and an LCD controller driving up to 256 pixels, in a 64-pin package with a 2.0–3.6 V supply range.

Operating Conditions:

• Supply voltage: 2.0–3.6 V
• Operating ambient temperature: -40 to +125 °C (AEC-Q100 Grade 1)
• CPU speed: up to 32 MHz (16 MIPS)

Absolute Maximum Ratings:

• Voltage on VDD with respect to VSS: -0.3 to +4.0 V
• Voltage on 5.5 V-tolerant pins (including MCLR) with respect to VSS: -0.3 to +6.0 V when VDD ≥ 2.0 V (-0.3 to +4.0 V when VDD = 0 V)
• Maximum current into VDD pin: 300 mA at +85 °C, 100 mA at +125 °C
• Maximum current out of VSS pin: 300 mA at +85 °C, 100 mA at +125 °C
• Maximum output current sunk or sourced by any I/O pin: 25 mA (50 mA for RB15 and RC15)
• Ambient temperature under bias: -40 to +125 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Flash: 128 KB with ECC (SEC/DED); typical endurance 10,000 erase/write cycles; data retention 20 years minimum
• SRAM: 8 KB
• ADC: up to 17 channels, 12-bit at 350 ksps or 10-bit at 400 ksps
• LCD: 32x8 with up to 256 pixels, charge pump, operation in Sleep mode
• Internal oscillator: 8 MHz fast RC, with 96 MHz PLL option
• GPIO: 54 pins; 5.5 V-tolerant on selected pins
• Communication: 4 UARTs, 2 SPI (up to 25 MHz), 2 I²C
• Timers: 5 × 16-bit timers and 5 MCCP modules
• DMA: 6 channels

Features:

• Modified Harvard architecture with 17x17 single-cycle multiplier and 32/16 hardware divider
• Three analog comparators with programmable reference voltage
• Four Configurable Logic Cells (CLC)
• Hardware RTCC, 32-bit CRC generator, and Peripheral Pin Select (PPS)
• Sleep, Idle, and Doze modes, plus Retention Sleep with ultra-low-power regulator
• Fail-safe clock monitor, POR/BOR, HLVD, WDT, and Deadman Timer
• CodeGuard security, Flash OTP write inhibit, and unique device ID
• ICSP/ICE programming and JTAG boundary scan
• AEC-Q100 REVG Grade 1 qualified

Applications:

Package:

• 64-pin TQFP/QFN (PIC24FJ128GL306)
• 48-pin TQFP/UQFN
• 36-pin UQFN
• 28-pin QFN/UQFN
• 28-pin SOIC/SSOP

• Up to 17-Channel, Software-Selectable, 10/12-Bit Analog-to-Digital Converter:
• -12-bit, 350K samples/second conversion rate (single Sample-and-Hold)
• -10-bit, 400K samples/second conversion rate (single Sample-and-Hold)
• -Sleep mode operation
• -Low-voltage boost for input
• -Band gap reference input feature
• -Core-independent windowed threshold compare feature
• -Auto-scan feature
• Three Analog Comparators with Input Multiplexing:
• -Programmable reference voltage for comparators

• 2: The HLVDIF flag cannot be cleared by software unless HLVDEVT = 0 . The voltage must be monitored so that the HLVD condition (as set by VDIR and HLVDL[3:0]) is not asserted.
• 3: CMPEN can only be written when the HLVDEN bit = 1 .

Note

1:

Maximum allowable current is a function of device maximum power dissipation (see Table 30-1).

• 2: Only on the 28-lead and 36-lead packages can AVDD/AVSS be considered for grouping of I/Os.

† NOTICE: Stresses above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

• Dimensioning and tolerancing per ASME Y14.5M 1.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

• For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 2.

Microchip Technology Drawing C04-2436-M5 Rev B