PIC24FJ128GL303
The PIC24FJ128GL303 is an electronic component from Microchip Technology. View the full PIC24FJ128GL303 datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Microchip Technology
Category
Microcontrollers
Overview
| Field | Description |
|---|---|
| #text | Means literal defined by ' text ' |
| (text) | Means 'content of text ' |
| [text] | Means 'the location addressed by text ' |
| { } | Optional field or operation |
| [n:m] | Register bit field |
| .b | Byte mode selection |
| .d | Double-Word mode selection |
| .S | Shadow register select |
| .w | Word mode selection (default) |
| bit4 | 4-bit Bit Selection field (used in word addressed instructions) {0...15} |
| C, DC, N, OV, Z | MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero |
| Expr | Absolute address, label or expression (resolved by the linker) |
| f | File register address {0000h...1FFFh} |
| lit1 | 1-bit unsigned literal {0,1} |
| lit4 | 4-bit unsigned literal {0...15} |
| lit5 | 5-bit unsigned literal {0...31} |
| lit8 | 8-bit unsigned literal {0...255} |
| lit10 | 10-bit unsigned literal {0...255} for Byte mode, {0...1023} for Word mode |
| lit14 | 14-bit unsigned literal {0...16383} |
| lit16 | 16-bit unsigned literal {0...65535} |
| lit23 | 23-bit unsigned literal {0...8388607}; LSb must be ' 0 ' |
| None | Field does not require an entry, may be blank |
| PC | Program Counter |
| Slit10 | 10-bit signed literal {-512...511} |
| Slit16 | 16-bit signed literal {-32768...32767} |
| Slit6 | 6-bit signed literal {-16...16} |
| Wb | Base Wregister {W0..W15} |
| Wd | Destination Wregister { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } |
| Wdo | Destination Wregister { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } |
| Wm,Wn | Dividend, Divisor Working register pair (direct addressing) |
| Wn | One of 16 Working registers {W0..W15} |
| Wnd | One of 16 destination Working registers {W0..W15} |
| Wns | One of 16 source Working registers {W0..W15} |
| WREG | W0 (Working register used in file register instructions) |
| Ws | Source Wregister { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } |
| Wso | Source Wregister { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } |
TABLE 28-2: INSTRUCTION SET OVERVIEW
| Assembly Mnemonic | Assembly Syntax | Description | # of Words | # of Cycles | Status Flags Affected | |
|---|---|---|---|---|---|---|
| ADD | ADD | f | f = f + WREG | 1 | 1 | C, DC, N, OV, Z |
| ADD | ADD | f,WREG | WREG = f + WREG | 1 | 1 | C, DC, N, OV, Z |
| ADD | ADD | #lit10,Wn | Wd = lit10 + Wd | 1 | 1 | C, DC, N, OV, Z |
| ADD | ADD | Wb,Ws,Wd | Wd = Wb + Ws | 1 | 1 | C, DC, N, OV, Z |
| ADD | ADD | Wb,#lit5,Wd | Wd = Wb + lit5 | 1 | 1 | C, DC, N, OV, Z |
| ADDC | ADDC | f | f = f + WREG + (C) | 1 | 1 | C, DC, N, OV, Z |
| ADDC | ADDC | f,WREG | WREG = f + WREG + (C) | 1 | 1 | C, DC, N, OV, Z |
| ADDC | ADDC | #lit10,Wn | Wd = lit10 + Wd + (C) | 1 | 1 | C, DC, N, OV, Z |
| ADDC | ADDC | Wb,Ws,Wd | Wd = Wb + Ws + (C) | 1 | 1 | C, DC, N, OV, Z |
| ADDC | ADDC | Wb,#lit5,Wd | Wd = Wb + lit5 + (C) | 1 | 1 | C, DC, N, OV, Z |
| AND | AND | f | f = f .AND. WREG | 1 | 1 | N, Z |
| AND | AND | f,WREG | WREG = f .AND. WREG | 1 | 1 | N, Z |
| AND | AND | #lit10,Wn | Wd = lit10 .AND. Wd | 1 | 1 | N, Z |
| AND | AND | Wb,Ws,Wd | Wd = Wb .AND. Ws | 1 | 1 | N, Z |
| AND | AND | Wb,#lit5,Wd | Wd = Wb .AND. lit5 | 1 | 1 | N, Z |
| ASR | ASR | f | f = Arithmetic Right Shift f | 1 | 1 | C, N, OV, Z |
| ASR | ASR | f,WREG | WREG = Arithmetic Right Shift f | 1 | 1 | C, N, OV, Z |
| ASR | ASR | Ws,Wd | Wd = Arithmetic Right Shift Ws | 1 | 1 | C, N, OV, Z |
| ASR | ASR | Wb,Wns,Wnd | Wnd = Arithmetic Right Shift Wb by Wns | 1 | 1 | N, Z |
| BCLR | BCLR | f,#bit4 | Bit Clear f | 1 | 1 | None |
| BCLR | BCLR | Ws,#bit4 | Bit Clear Ws | 1 | 1 | None |
| BRA | BRA | C,Expr | Branch if Carry | 1 | 1 (2) | None |
| BCLR | BRA | GE,Expr | Branch if Greater Than or Equal | 1 | 1 (2) | None |
| BCLR | BRA | GEU,Expr | Branch if Unsigned Greater Than or Equal | 1 | 1 (2) | None |
| BCLR | BRA | GT,Expr | Branch if Greater Than | 1 | 1 (2) | None |
| BCLR | BRA | GTU,Expr | Branch if Unsigned Greater Than | 1 | 1 (2) | None |
| BCLR | BRA | LE,Expr | Branch if Less Than or Equal | 1 | 1 (2) | None |
| BCLR | BRA | LEU,Expr | Branch if Unsigned Less Than or Equal | 1 | 1 (2) | None |
| BCLR | BRA | LT,Expr | Branch if Less Than | 1 | 1 (2) | None |
| BCLR | BRA | LTU,Expr N,Expr | Branch if Unsigned Less Than | 1 | 1 (2) | None |
| BCLR | BRA | Branch if Negative | 1 | 1 (2) | None | |
| BCLR | BRA | NC,Expr | Branch if Not Carry | 1 | 1 (2) | None |
| BCLR | BRA | NN,Expr | Branch if Not Negative | 1 | 1 (2) | None |
| BCLR | BRA | NOV,Expr | Branch if Not Overflow | 1 | 1 (2) | None |
| BCLR | BRA | NZ,Expr | Branch if Not Zero | 1 | 1 (2) | None |
| BCLR | BRA | OV,Expr | Branch if Overflow | 1 | 1 (2) | None |
| BCLR | BRA | Expr | Branch Unconditionally | 1 | 2 | None |
| BCLR | BRA BRA | Z,Expr Wn | Branch if Zero Computed Branch | 1 1 | 1 (2) 2 | None None |
| BSET | BSET | f,#bit4 | Bit Set f | 1 | 1 | None |
| BSET | BSET | Ws,#bit4 | Bit Set Ws | 1 | 1 | None |
| BSW | BSW.C | Ws,Wb | Write C bit to Ws[Wb] | 1 | 1 | None |
| BSW | BSW.Z | Ws,Wb | Write Z bit to Ws[Wb] | 1 | 1 | None |
| BTG | BTG | f,#bit4 | Bit Toggle f | 1 | 1 | None |
| BTG | BTG | Ws,#bit4 | Bit Toggle Ws | 1 | 1 | None |
| BTSC | BTSC | f,#bit4 | Bit Test f, Skip if Clear | 1 | 1 (2 or 3) | None |
| BTSC | BTSC | Ws,#bit4 | Bit Test Ws, Skip if Clear | 1 | 1 (2 or 3) | None |
Features
- Up to 17-Channel, Software-Selectable, 10/12-Bit Analog-to-Digital Converter:
- -12-bit, 350K samples/second conversion rate (single Sample-and-Hold)
- -10-bit, 400K samples/second conversion rate (single Sample-and-Hold)
- -Sleep mode operation
- -Low-voltage boost for input
- -Band gap reference input feature
- -Core-independent windowed threshold compare feature
- -Auto-scan feature
- Three Analog Comparators with Input Multiplexing:
- -Programmable reference voltage for comparators
Electrical Characteristics
- 2: The HLVDIF flag cannot be cleared by software unless HLVDEVT = 0 . The voltage must be monitored so that the HLVD condition (as set by VDIR and HLVDL[3:0]) is not asserted.
- 3: CMPEN can only be written when the HLVDEN bit = 1 .
Absolute Maximum Ratings
| Ambient temperature under bias.............................................................................................................-40°C to | +125°C |
|---|---|
| Storage temperature .............................................................................................................................. | -65°C to +150°C |
| Voltage on VDD with respect to VSS ......................................................................................................... | -0.3V to +4.0V |
| Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS ....... -0.3V to (VDD + | 0.3V) |
| Voltage on any general purpose digital or analog pin (5.5V tolerant, including MCLR) with respect to VSS: | |
| When VDD = 0V: .......................................................................................................................... | -0.3V to +4.0V |
| When VDD 2.0V: ....................................................................................................................... | -0.3V to +6.0V |
| Voltage on AVDD with respect to VSS ...................................................(VDD - 0.3V) to (lesser of: 4.0V or | (VDD + 0.3V)) |
| Voltage on AVSS with respect to VSS ........................................................................................................ -0.3V | to +0.3V |
| Maximum current out of VSS pin: | |
| +85°C......................................................................................................................................................300 | mA |
| +125°C....................................................................................................................................................100 | mA |
| Maximum current into VDD pin (Note 1) : | |
| +85°C......................................................................................................................................................300 | mA |
| +125°C....................................................................................................................................................100 | mA |
| Maximum output current sunk by any I/O pin: | |
| RB15, RC15 | .............................................................................................................................................50 mA |
| All other I/Os.............................................................................................................................................25 | mA |
| Maximum output current sourced by any I/O pin: | |
| RB15, RC15 .............................................................................................................................................50 | mA |
| All other I/Os.............................................................................................................................................25 | mA |
| Maximum current sunk by group of I/Os between two VSS Pins (Note 2) : | |
| +85°C......................................................................................................................................................300 | mA |
| +125°C......................................................................................................................................................75 | mA |
| Maximum current sourced by group of I/Os between two VDD pins (Note 2) : | |
| +85°C......................................................................................................................................................300 | mA |
| +125°C......................................................................................................................................................75 | mA |
Note
1:
Maximum allowable current is a function of device maximum power dissipation (see Table 30-1).
- 2: Only on the 28-lead and 36-lead packages can AVDD/AVSS be considered for grouping of I/Os.
† NOTICE: Stresses above those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Thermal Information
| Rating | Symbol | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| PIC24FJ128GL306: | |||||
| Operating Junction Temperature Range | TJ | -40 | - | +135 | °C |
| Operating Ambient Temperature Range | TA | -40 | - | +125 | °C |
| Power Dissipation: | |||||
| Internal Chip Power Dissipation: PINT = VDD x (IDD - I OH) | PD | PINT + PI /O | PINT + PI /O | PINT + PI /O | W |
| I/O Pin Power Dissipation: PI /O = ({VDD - VOH} x I OH) + (V OL x I OL ) | |||||
| Maximum Allowed Power Dissipation | PDMAX | (T J - TA)/ JA | (T J - TA)/ JA | (T J - TA)/ JA | W |
Package Information
| Units | MILLIMETERS | MILLIMETERS | MILLIMETERS | |
|---|---|---|---|---|
| Dimension Limits | Dimension Limits | MIN | NOM | MAX |
| Contact Pitch | E | 0.40 BSC | ||
| Center Pad Width | X2 | 3.80 | ||
| Center Pad Length | Y2 | 3.80 | ||
| Contact Pad Spacing | C1 | 5.00 | ||
| Contact Pad Spacing | C2 | 5.00 | ||
| Contact Pad Width (X36) | X1 | 0.20 | ||
| Contact Pad Length (X36 | Y1 | 0.80 | ||
| Corner Pad Width (X4) | X3 | 0.85 | ||
| Corner Pad Length (X4) | Y3 | 0.85 | ||
| Corner Pad Radius | R | 0.10 | ||
| Contact Pad to Center Pad (X36) | G | 0.20 | ||
| Thermal Via Diameter | V | 0.30 | ||
| Thermal Via Pitch | EV | 1.00 |
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
- For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 2.
Microchip Technology Drawing C04-2436-M5 Rev B
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| PIC24FJ128GL302 | Microchip Technology | — |
| PIC24FJ128GL305 | Microchip Technology | — |
| PIC24FJ128GL306 | Microchip Technology | — |
| PIC24FJ128GL30X | Microchip Technology | — |
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.
Get structured datasheet data via API
Get started free