LMK04828B/26B
JESD204B Clock Jitter CleanerThe LMK04828B/26B is a jesd204b clock jitter cleaner from Texas Instruments. View the full LMK04828B/26B datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
LMK04828B/26B shares its datasheet with LMK04828, whose page lists every part number it covers.
Official LMK04828B/26B datasheet (PDF) — the source this page was extracted from.
LMK04828B/26B Key Specifications
| Parameter | Value |
|---|---|
| Interface | SPI |
| Output Formats | LVPECL, LVDS, HSDS, LCPECL |
| Supply Voltage | 3.15V to 3.45V |
| Analog Delay Step | 25 ps |
| Package Dimensions | 9.0 mm x 9.0 mm x 0.8 mm |
| Output Divider Range | 1 to 32 (even and odd), 50% duty cycle |
| SYSREF Clock Outputs | Up to 7 |
| Operating Temperature | -40°C to 85°C (105°C PCB temperature at thermal pad) |
| PLL2 Phase Detector Rate | Up to 155 MHz |
| Noise Floor At 245.76 MHz | -162.5 dBc/Hz |
| VCO0 Frequency (LMK04826B) | 1840 to 1970 MHz |
| VCO0 Frequency (LMK04828B) | 2370 to 2630 MHz |
| VCO1 Frequency (LMK04826B) | 2440 to 2505 MHz |
| VCO1 Frequency (LMK04828B) | 2920 to 3080 MHz |
| Normalized PLL2 Noise Floor | -227 dBc/Hz |
| RMS Jitter (100 Hz To 20 MHz) | 91 fs |
| RMS Jitter (12 KHz To 20 MHz) | 88 fs |
| Redundant Input Clocks (PLL1) | Up to 3 |
| Maximum Output Clock Frequency | 3.1 GHz |
| Differential Device Clock Outputs | Up to 14 (from PLL2) |
LMK04828B/26B Overview
Part: LMK04828 (LMK0482x family: LMK04821, LMK04826, LMK04828), Texas Instruments
Type: JESD204B Clock Jitter Cleaner with Dual-Loop PLLs
Description: Ultra low-noise JESD204B-compliant clock jitter cleaner with 88 fs RMS jitter (12 kHz to 20 MHz), up to 14 differential device clocks, a maximum output frequency of 3.1 GHz, and 3.15–3.45 V operation.
Operating Conditions:
- Supply voltage: 3.15–3.45 V (3.3 V typical)
- Operating temperature: -40 to 85 °C (ambient)
- PCB temperature (measured at thermal pad): up to 105 °C
- Junction temperature: up to 125 °C
Absolute Maximum Ratings:
- Max supply voltage (VCC): 3.6 V
- Input voltage: -0.3 V to (VCC + 0.3 V)
- Differential input current (CLKinX, OSCin, FBCLKin, Fin): ±5 mA
- Max junction temperature: 150 °C
- Storage temperature: -65 to 150 °C
- Lead temperature (solder, 4 s): 260 °C
Key Specs:
- RMS jitter: 88 fs (12 kHz to 20 MHz); 91 fs (100 Hz to 20 MHz)
- Noise floor: -162.5 dBc/Hz at 245.76 MHz
- PLL2 normalized [1 Hz] noise floor: -227 dBc/Hz
- PLL2 phase detector rate: up to 155 MHz
- Maximum clock output frequency: 3.1 GHz
- LMK04828 VCO0: 2370 to 2630 MHz; VCO1: 2920 to 3080 MHz
- Output divides: 1 to 32 (even and odd), 50% duty cycle
- Analog delay: 25 ps step
Features:
- JEDEC JESD204B support
- Up to 14 differential device clocks from PLL2, and up to 7 SYSREF clocks
- Programmable outputs: LVPECL, LVDS, HSDS, LCPECL (PLL2); LVPECL, LVDS, 2xLVCMOS (buffered VCXO output from PLL1)
- Dual-loop PLLatinum architecture
- PLL1: up to 3 redundant input clocks, automatic and manual switchover, hitless switching, LOS, holdover mode, integrated low-noise crystal oscillator circuit
- PLL2: OSCin frequency doubler, two integrated low-noise VCOs
- Precision digital delay (dynamically adjustable) and glitchless analog delay
- Multi-mode: dual PLL, single PLL, and clock distribution
Applications:
- Wireless infrastructure
- Data converter clocking
- Networking, SONET/SDH, DSLAM
- Medical / video / military / aerospace
- Test and measurement
Package:
- 64-pin QFN (9.0 mm × 9.0 mm × 0.8 mm)
LMK04828B/26B Features
- 1 · JEDEC JESD204B Support
- Ultra-Low RMS Jitter
- -88 fs RMS Jitter (12 kHz to 20 MHz)
- -91 fs RMS Jitter (100 Hz to 20 MHz)
- --162.5 dBc/Hz Noise Floor at 245.76 MHz
- Up to 14 Differential Device Clocks from PLL2
- -Up to 7 SYSREF Clocks
- -Maximum Clock Output Frequency 3.1 GHz
- -LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
- Up to 1 Buffered VCXO/Crystal Output from PLL1 -LVPECL, LVDS, 2xLVCMOS Programmable
- Dual Loop PLLatinum™ PLL Architecture
- PLL1
- -Up to 3 Redundant Input Clocks
- -Automatic and Manual Switch-Over Modes
- -Hitless Switching and LOS
- -Integrated Low-Noise Crystal Oscillator Circuit
- -Holdover Mode When Input Clocks are Lost
LMK04828B/26B Applications
- Wireless Infrastructure
- Data Converter Clocking
- Networking, SONET/SDH, DSLAM
- Medical / Video / Military / Aerospace
- Test and Measurement
LMK04828B/26B Pin Configuration
LMK04828B/26B Electrical Characteristics
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| CURRENT CONSUMPTION | CURRENT CONSUMPTION | CURRENT CONSUMPTION | CURRENT CONSUMPTION | CURRENT CONSUMPTION | CURRENT CONSUMPTION | CURRENT CONSUMPTION |
| I CC_PD | Power down supply current | 1 | 3 | mA | ||
| I CC_CLKS | Supply current (1) | 14 HSDS 8-mA clocks enabled PLL1 and PLL2 locked. | 565 | 665 | mA | |
| CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS | CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS | CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS | CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS | CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS | CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS | CLKin0/0*, CLKin1/1*, and CLKin2/2* INPUT CLOCK SPECIFICATIONS |
| f CLKin | Clock input frequency | 0.001 | 750 | MHz | ||
| SLEW CLKin | Clock input slew rate (2) | 20% to 80% | 0.15 | 0.5 | V/ns | |
| V ID CLKin | Clock input Differential input voltage (3) Figure 8 | AC coupled | 0.125 | 1.55 | |V| | |
| V SS CLKin | Clock input Differential input voltage (3) Figure 8 | AC coupled | 0.25 | 3.1 | Vpp | |
| V CLKin | Clock input Single-ended input voltage | AC coupled to CLKinX; CLKinX* AC coupled to ground CLKinX_TYPE = 0 (bipolar) | 0.25 | 2.4 | Vpp | |
| V CLKin | Clock input Single-ended input voltage | AC coupled to CLKinX; CLKinX* AC coupled to ground CLKinX_TYPE = 1 (MOS) | 0.35 | 2.4 | Vpp | |
| |V CLKinX-offset | | DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX) | Each pin AC coupled, CLKin0/1/2 CLKinX_TYPE = 0 (bipolar) | 0 | |mV| | ||
| |V CLKinX-offset | | DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX) | Each pin AC coupled, CLKin0/1 CLKinX_TYPE = 1 (MOS) | 55 | |mV| | ||
| |V CLKinX-offset | | DC offset voltage between CLKin2/CLKin2* (CLKin2* - CLKin2) | Each pin AC coupled CLKinX_TYPE = 1 (MOS) | 20 | |mV| | ||
| V CLKin- V IH | High input voltage | DC coupled to CLKinX; CLKinX* AC coupled to ground CLKinX_TYPE = 1 (MOS) | 2.0 | V CC | V | |
| V CLKin- V IL | Low input voltage | DC coupled to CLKinX; CLKinX* AC coupled to ground CLKinX_TYPE = 1 (MOS) | 0.0 | 0.4 | V | |
| FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS | FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS |
| f FBCLKin | Clock input frequency for zero-delay with external feedback. | AC coupled CLKinX_TYPE = 0 (bipolar) | 0.001 | 750 | MHz | |
| f Fin | Clock input frequency for external VCO or distribution mode | AC coupled (4) CLKinX_TYPE = 0 (bipolar) | 0.001 | 3100 | MHz |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| V FBCLKin/Fin | Single ended Clock input voltage | AC coupled CLKinX_TYPE = 0 (bipolar) | 0.25 | 2.0 | Vpp | |
| SLEW FBCLKin/Fin | Slew rate on CLKin (2) | AC coupled; 20% to 80%; (CLKinX_TYPE = 0) | 0.15 | 0.5 | V/ns | |
| PLL1 SPECIFICATIONS | PLL1 SPECIFICATIONS | PLL1 SPECIFICATIONS | PLL1 SPECIFICATIONS | PLL1 SPECIFICATIONS | PLL1 SPECIFICATIONS | PLL1 SPECIFICATIONS |
| f PD1 | PLL1 phase detector frequency | V CPout1 = V CC /2, PLL1_CP_GAIN = 0 | 50 | 40 | MHz μA | |
| I CPout1 SOURCE | PLL1 charge Pump source current (5) | V CPout1 = V CC /2, PLL1_CP_GAIN = 1 V CPout1 = V CC /2, PLL1_CP_GAIN = 2 … V CPout1 = V CC /2, PLL1_CP_GAIN = 14 V CPout1 = V CC /2, PLL1_CP_GAIN = 15 | 150 250 … 1450 1550 | μA μA μA μA μA | ||
| I CPout1 SINK | V CPout1 =V CC /2, PLL1_CP_GAIN = 0 | -50 | μA | |||
| PLL1 charge | V CPout1 =V CC /2, PLL1_CP_GAIN = 1 V CPout1 =V CC /2, PLL1_CP_GAIN = 2 | -150 -250 | μA μA | |||
| Pump sink current (5) | … V CPout1 =V CC /2, PLL1_CP_GAIN = 14 V CPout1 =V CC /2, PLL1_CP_GAIN = 15 | … -1450 -1550 | μA μA μA | |||
| I CPout1 %MIS | Charge pump Sink / source mismatch | V CPout1 = V CC /2, T = 25 °C | 1% | 10% | ||
| I CPout1 V TUNE | Magnitude of charge pump current variation vs. charge pump voltage | 0.5 V < V CPout1 < V CC - 0.5 V T A = 25 °C | 4% | |||
| I CPout1 %TEMP | Charge pump current vs. temperature variation | 4% | ||||
| I CPout1 TRI | Charge pump TRI-STATE leakage current | 0.5 V < V CPout < V CC - 0.5 V | 5 | nA | ||
| PN10kHz | PLL 1/f noise at 10-kHz offset. | PLL1_CP_GAIN = 350 μA | -117 | dBc/Hz | ||
| Normalized to 1-GHz output frequency | PLL1_CP_GAIN = 1550 μA | -118 | dBc/Hz | |||
| PN1Hz | PLL1_CP_GAIN = 350 μA | -221.5 | dBc/Hz | |||
| Normalized phase noise contribution | PLL1_CP_GAIN = 1550 μA | -223 | dBc/Hz | |||
| PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS |
| f OSCin | PLL2 reference input (6) | 500 | MHz | |||
| SLEW OSCin | PLL2 reference clock minimum slew rate on OSCin (2) | 20% to 80% | 0.15 | 0.5 | V/ns | |
| V OSCin | Input voltage for OSCin or OSCin* | AC coupled; single-ended (unused pin AC coupled to GND) | 0.2 | 2.4 | Vpp | |
| V ID OSCin | Differential voltage swing | AC coupled | 0.2 | 1.55 | |V| | |
| V SS OSCin | Figure 8 | AC coupled | 0.4 | 3.1 | Vpp | |
| |V OSCin-offset | | DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX) | Each pin AC coupled | 20 | |mV| | ||
| f doubler_max | Doubler input frequency (7) | EN_PLL2_REF_2X = 1 (8) ; OSCin duty cycle 40% to 60% | 155 | MHz |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| CRYSTAL OSCILLATOR MODE SPECIFICATIONS | CRYSTAL OSCILLATOR MODE SPECIFICATIONS | CRYSTAL OSCILLATOR MODE SPECIFICATIONS | CRYSTAL OSCILLATOR MODE SPECIFICATIONS | CRYSTAL OSCILLATOR MODE SPECIFICATIONS | CRYSTAL OSCILLATOR MODE SPECIFICATIONS | CRYSTAL OSCILLATOR MODE SPECIFICATIONS |
| F XTAL | Crystal frequency range | Fundamental mode crystal ESR = 200 Ω (10 to 30 MHz) ESR = 125 Ω (30 to 40 MHz) | 10 | 40 | MHz | |
| C IN | Input capacitance of OSCin port | -40 to 85 °C | 1 | pF | ||
| PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS | PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS |
| f PD2 | Phase detector frequency (7) | 155 | MHz | |||
| I CPout SOURCE | PLL2 charge pump source current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 0 | 100 | μA | ||
| I CPout SOURCE | PLL2 charge pump source current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 1 | 400 | μA | ||
| I CPout SOURCE | PLL2 charge pump source current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 2 | 1600 | μA | ||
| I CPout SOURCE | PLL2 charge pump source current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 3 | 3200 | μA | ||
| I CPout SINK | PLL2 charge pump sink current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 0 | -100 | μA | ||
| I CPout SINK | PLL2 charge pump sink current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 1 | -400 | μA | ||
| I CPout SINK | PLL2 charge pump sink current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 2 | -1600 | μA | ||
| I CPout SINK | PLL2 charge pump sink current (5) | V CPout2 =V CC /2, PLL2_CP_GAIN = 3 | -3200 | μA | ||
| I CPout2 %MIS | Charge pump sink/source mismatch | V CPout2 =V CC /2, T A = 25 °C | 1% | 10% | ||
| I CPout2 V TUNE | Magnitude of charge pump current vs. charge pump voltage variation | 0.5 V < V CPout2 < V CC - 0.5 V T A = 25 °C | 4% | |||
| I CPout2 %TEMP | Charge pump current vs. temperature variation | 4% | ||||
| I CPout2 TRI | Charge pump leakage | 0.5 V < V CPout2 < V CC - 0.5 V | 10 | nA | ||
| PN10kHz | PLL 1/f noise at 10-kHz offset (9) . Normalized to 1-GHz output frequency | PLL2_CP_GAIN = 400 μA | -118 | dBc/Hz | ||
| PN10kHz | PLL 1/f noise at 10-kHz offset (9) . Normalized to 1-GHz output frequency | PLL2_CP_GAIN = 3200 μA | -121 | dBc/Hz | ||
| PN1Hz | Normalized phase noise contribution (10) | PLL2_CP_GAIN = 400 μA | -222.5 | dBc/Hz | ||
| PN1Hz | Normalized phase noise contribution (10) | PLL2_CP_GAIN = 3200 μA | -227 | dBc/Hz |
- (10) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat (f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(f PDX ). L PLL_flat (f) is the single side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth and fPDX is the phase-detector frequency of the synthesizer. L PLL_flat (f) contributes to the total noise, L(f).
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INTERNAL VCO SPECIFICATIONS | INTERNAL VCO SPECIFICATIONS | INTERNAL VCO SPECIFICATIONS | INTERNAL VCO SPECIFICATIONS | INTERNAL VCO SPECIFICATIONS | INTERNAL VCO SPECIFICATIONS | INTERNAL VCO SPECIFICATIONS |
| LMK04821 VCO tuning range | VCO0 | 1930 | 2075 | MHz | ||
| VCO1 (11) | 2920 | 3080 | MHz | |||
| f VCO | LMK04826 VCO tuning range | VCO0 | 1840 | 1970 | MHz | |
| f VCO | VCO1 | 2440 | 2505 | MHz | ||
| LMK04828 VCO tuning range | VCO0 | 2370 | 2630 | MHz | ||
| VCO1 | 2920 | 3080 | MHz | |||
| LMK04821 fine tuning sensitivity | LMK04821 VCO0 LMK04821 VCO1 | 12 to 20 15 to 24 | MHz/V MHz/V | |||
| K VCO | LMK04826 fine tuning sensitivity | LMK04826 VCO0 | 11 to 19 | MHz/V | ||
| K VCO | LMK04826 VCO1 | 8 to 11 | MHz/V | |||
| LMK04828 fine tuning sensitivity | LMK04828 VCO0 at 2457.6 MHz LMK04828 VCO1 at 2949.12 MHz | 17 to 27 17 to 23 | MHz/V MHz/V | |||
| | Δ T CL | | Allowable temperature drift for continuous lock (12) | After programming for lock, no changes to output configuration are permitted to assure continuous lock | 125 | °C |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| NOISE FLOOR | PARAMETER - NOISE FLOOR | TEST CONDITIONS - NOISE FLOOR | TEST CONDITIONS - NOISE FLOOR | MIN TYP - NOISE FLOOR | MAX - NOISE FLOOR | UNIT - NOISE FLOOR | NOISE FLOOR |
|---|---|---|---|---|---|---|---|
| L(f) CLKout | LMK04821, VCO0, noise floor 20-MHz offset (13) | 245.76 MHz | LVDS | -158.2 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO0, noise floor 20-MHz offset (13) | 245.76 MHz | HSDS 6 mA | -160 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO0, noise floor 20-MHz offset (13) | 245.76 MHz | HSDS 8 mA | -161 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO0, noise floor 20-MHz offset (13) | 245.76 MHz | HSDS 10 mA | -161.4 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO0, noise floor 20-MHz offset (13) | 245.76 MHz | LVPECL16 with 240 Ω | -161.6 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO0, noise floor 20-MHz offset (13) | 245.76 MHz | LVPECL20 with 240 Ω | -162 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO0, noise floor 20-MHz offset (13) | 245.76 MHz | LVPECL | 161.7 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO1, noise floor 20-MHz offset (13) | 245.76 MHz | LVDS | -157.1 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO1, noise floor 20-MHz offset (13) | 245.76 MHz | HSDS 6 mA | -158.3 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO1, noise floor 20-MHz offset (13) | 245.76 MHz | HSDS 8 mA | -159 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO1, noise floor 20-MHz offset (13) | 245.76 MHz | HSDS 10 mA | -159.2 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO1, noise floor 20-MHz offset (13) | 245.76 MHz | LVPECL16 with 240 Ω | -158.8 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO1, noise floor 20-MHz offset (13) | 245.76 MHz | LVPECL20 with 240 Ω | -158.9 | dBc/Hz | ||
| L(f) CLKout | LMK04821, VCO1, noise floor 20-MHz offset (13) | 245.76 MHz | LVPECL | -158.8 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO0, noise floor 20-MHz offset (14) | 245.76 MHz | LVDS | -158.1 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO0, noise floor 20-MHz offset (14) | 245.76 MHz | HSDS 6 mA | -159.7 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO0, noise floor 20-MHz offset (14) | 245.76 MHz | HSDS 8 mA | -160.8 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO0, noise floor 20-MHz offset (14) | 245.76 MHz | HSDS 10 mA | -161.3 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO0, noise floor 20-MHz offset (14) | 245.76 MHz | LVPECL16 with 240 Ω | -161.8 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO0, noise floor 20-MHz offset (14) | 245.76 MHz | LVPECL20 with 240 Ω | -162.0 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO0, noise floor 20-MHz offset (14) | 245.76 MHz | LCPECL | -161.7 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO1, noise floor 20-MHz offset (14) | 245.76 MHz | LVDS | -157.5 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO1, noise floor 20-MHz offset (14) | 245.76 MHz | HSDS 6 mA | -158.9 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO1, noise floor 20-MHz offset (14) | 245.76 MHz | HSDS 8 mA | -159.8 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO1, noise floor 20-MHz offset (14) | 245.76 MHz | HSDS 10 mA | -160.3 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO1, noise floor 20-MHz offset (14) | 245.76 MHz | LVPECL16 with 240 Ω | -160.8 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO1, noise floor 20-MHz offset (14) | 245.76 MHz | LVPECL20 with 240 Ω | -160.7 | dBc/Hz | ||
| L(f) CLKout | LMK04826, VCO1, noise floor 20-MHz offset (14) | 245.76 MHz | LCPECL | -160.7 | dBc/Hz |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | TEST CONDITIONS | TEST CONDITIONS | MIN TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| NOISE FLOOR (continued) | NOISE FLOOR (continued) | NOISE FLOOR (continued) | NOISE FLOOR (continued) | NOISE FLOOR (continued) | NOISE FLOOR (continued) | NOISE FLOOR (continued) | NOISE FLOOR (continued) |
| L(f) CLKout | 245.76 MHz | LVDS | -156.3 | dBc/Hz | |||
| L(f) CLKout | 245.76 MHz | HSDS 6 mA | -158.4 | dBc/Hz | |||
| L(f) CLKout | 245.76 MHz | HSDS 8 mA | -159.3 | dBc/Hz | |||
| L(f) CLKout | LMK04828, VCO0, noise floor | 245.76 MHz | HSDS 10 mA | -158.9 | dBc/Hz | ||
| 20-MHz | offset (15) | 245.76 MHz | LVPECL16 with 240 Ω | -161.6 | dBc/Hz | ||
| L(f) CLKout | 245.76 MHz | LVPECL20 with 240 Ω LCPECL | -162.5 -162.1 | dBc/Hz dBc/Hz | |||
| L(f) CLKout | LMK04828, VCO1, noise floor offset (15) 245.76 | MHz | LVDS | -155.7 | dBc/Hz | ||
| L(f) CLKout | MHz | HSDS 6 mA | -157.5 | dBc/Hz | |||
| L(f) CLKout | MHz | HSDS 8 mA | -158.1 | dBc/Hz | |||
| L(f) CLKout | MHz | HSDS 10 mA | -157.7 | dBc/Hz | |||
| 20-MHz | MHz | LVPECL16 with 240 Ω | -160.3 | dBc/Hz | |||
| L(f) CLKout | MHz | LVPECL20 with 240 Ω | -161.1 | dBc/Hz | |||
| L(f) CLKout | MHz | LCPECL | -160.8 | dBc/Hz | |||
| CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) |
| L(f) CLKout | Offset = 1 kHz Offset = 10 kHz | -126.9 -133.5 | dBc/Hz dBc/Hz | ||||
| LMK04821 | Offset = 100 kHz | -135.4 | dBc/Hz | ||||
| VCO0 | Offset = 1 MHz | -149.8 | dBc/Hz | ||||
| SSB phase 245.76 | noise (13) | LVDS | -158.1 | dBc/Hz | |||
| MHz | Offset = 10 MHz | HSDS 8 mA | -161.1 | dBc/Hz | |||
| Offset = 10 MHz | LVPECL16 with 240 Ω | -161.7 | dBc/Hz | ||||
| L(f) CLKout | Offset = 1 kHz | -126.8 | dBc/Hz | ||||
| L(f) CLKout | Offset = 10 kHz | -133.4 | dBc/Hz | ||||
| LMK04821 | Offset = 100 kHz | -135.4 | dBc/Hz | ||||
| VCO1 | Offset = 1 MHz | -151.8 | dBc/Hz | ||||
| SSB phase 245.76 | noise (13) MHz | LVDS | -157.2 | dBc/Hz | |||
| L(f) CLKout | Offset = 10 MHz | HSDS 8 mA | -159.1 | dBc/Hz | |||
| L(f) CLKout | LVPECL16 with 240 Ω | -158.9 | dBc/Hz |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | PARAMETER | TEST | CONDITIONS | MIN TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) Offset = 10 kHz Offset = 100 kHz | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) -134.8 -135.4 | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) | CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) dBc/Hz dBc/Hz |
| Offset = 1 MHz | LVDS | -148.2 | dBc/Hz | |||
| L(f) CLKout | Offset = 1 MHz | HSDS 8 mA LVPECL16 with 240 Ω | -148.6 | dBc/Hz | ||
| Offset = 10 MHz | LVDS | -157.8 | dBc/Hz | |||
| Offset = 10 MHz | HSDS 8 mA | -160.4 | dBc/Hz | |||
| Offset = 10 MHz | LVPECL16 with 240 Ω | -161.5 | dBc/Hz | |||
| L(f) CLKout | Offset = 10 kHz | -134.3 | dBc/Hz | |||
| L(f) CLKout | Offset = 100 kHz | -133.7 | dBc/Hz | |||
| Offset = 1 MHz | LVDS | -152.5 | dBc/Hz | |||
| Offset = 1 MHz | HSDS 8 mA LVPECL16 with 240 Ω | -153.6 | dBc/Hz | |||
| Offset = 10 MHz | LVDS | -157.3 | dBc/Hz | |||
| Offset = 10 MHz | HSDS 8 mA | -159.6 | dBc/Hz | |||
| Offset = 10 MHz | LVPECL16 with 240 Ω | -160.5 | dBc/Hz | |||
| L(f) CLKout | Offset = 1 kHz | -124.3 | dBc/Hz | |||
| L(f) CLKout | Offset = 10 kHz | -134.7 | dBc/Hz | |||
| L(f) CLKout | Offset = 100 kHz | -136.5 | dBc/Hz | |||
| L(f) CLKout | Offset = 1 MHz | -148.4 | dBc/Hz | |||
| L(f) CLKout | Offset = 10 MHz | LVDS | -156.4 | dBc/Hz | ||
| L(f) CLKout | Offset = 10 MHz | HSDS 8 mA | -159.1 | dBc/Hz | ||
| L(f) CLKout | Offset = 10 MHz | LVPECL16 with 240 Ω | -160.8 | dBc/Hz | ||
| L(f) CLKout | Offset = 1 kHz | -124.2 | dBc/Hz | |||
| L(f) CLKout | Offset = 10 kHz | -134.4 | dBc/Hz | |||
| L(f) CLKout | Offset = 100 kHz | -135.2 | dBc/Hz | |||
| L(f) CLKout | Offset = 1 MHz | -151.5 | dBc/Hz | |||
| Offset = 10 MHz | LVDS | -159.9 | dBc/Hz | |||
| Offset = 10 MHz | HSDS 8 mA | -155.8 | dBc/Hz | |||
| Offset = 10 MHz | LVPECL16 with 240 Ω | -158.1 | dBc/Hz |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | TEST CONDITIONS | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) LVDS, BW = 12 kHz to 20 MHz HSDS 8 mA, BW = 12 kHz to 20 MHz LVPECL16 with 240 Ω , BW = 12 kHz to 20 MHz LVPECL20 with 240 Ω , BW = 12 kHz to 20 MHz LCPECL with 240 Ω , BW = 12 kHz to 20 MHz | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) 99 94 96 94 93 | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) fs rms fs rms fs rms fs rms fs rms | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16) |
| J CLKout | LVDS, BW = 12 kHz to 20 MHz | 96 | fs rms | |||
| J CLKout | HSDS 8 mA, BW = 12 kHz to 20 MHz | 90 | fs rms | |||
| J CLKout | LVPECL16 with 240 Ω , BW = 12 kHz to 20 MHz | 92 | fs rms | |||
| J CLKout | LVPECL20 with 240 Ω , BW = 12 kHz to 20 MHz | 91 | fs rms | |||
| J CLKout | LCPECL with 240 Ω , BW = 12 kHz to 20 MHz | 91 | fs rms | |||
| CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) LVDS, BW = 100 Hz to 20 MHz LVDS, BW = 12 kHz to 20 MHz HSDS 8 mA, BW = 100 Hz to 20 MHz HSDS 8 mA, BW = 12 kHz to 20 MHz LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz LVPECL16 /w 240 Ω , BW = 12 kHz to 20 MHz LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) 106 104 99 97 99 96 100 97 | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) |
| J CLKout | LVDS, BW = 100 Hz to 20 MHz | 99 | fs rms | |||
| J CLKout | LVDS, BW = 12 kHz to 20 MHz | 97 | fs rms | |||
| J CLKout | HSDS 8 mA, BW = 100 Hz to 20 MHz | 92 | fs rms | |||
| J CLKout | HSDS 8 mA, BW = 12 kHz to 20 MHz | 90 | fs rms | |||
| J CLKout | LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz | 91 | fs rms | |||
| J CLKout | LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz | 89 | fs rms | |||
| J CLKout | LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz | 92 | fs rms | |||
| J CLKout | LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz | 89 | fs rms |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN TYP | UNIT | ||
|---|---|---|---|---|---|---|
| CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) J CLKout | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) LVDS, BW = 100 Hz to 20 MHz LVDS, BW = 12 kHz to 20 MHz HSDS 8 mA, BW = 100 Hz to 20 MHz HSDS 8 mA, BW = 12 kHz to 20 MHz LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz LVDS, BW = 100 Hz to 20 MHz LVDS, BW = 12 kHz to 20 MHz HSDS 8 mA, BW = 100 Hz to 20 MHz HSDS 8 mA, BW = 12 kHz to 20 MHz LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) 112 109 102 99 98 95 96 93 108 105 98 94 93 90 91 88 | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) | CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16) |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY | DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY | DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY | DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY | DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY | DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY | DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY |
| f CLKout-startup | Default output clock frequency at | LMK04826 | 235 | MHz | ||
| f CLKout-startup | device power on (17)(18) | LMK04828 | 315 | |||
| f OSCout | OSCout frequency | (7) | 500 | MHz | ||
| CLOCK SKEW and DELAY | CLOCK SKEW and DELAY | CLOCK SKEW and DELAY | CLOCK SKEW and DELAY | CLOCK SKEW and DELAY | CLOCK SKEW and DELAY | CLOCK SKEW and DELAY |
| |T SKEW | | DCLKoutX to SDCLKoutY F CLK = 245.76 MHz, R L = 100 Ω AC coupled (19) | Same pair, same format (20) SDCLKoutY_MUX = 0 (device clock) | 25 | |ps| | ||
| |T SKEW | | Maximum DCLKoutX or SDCLKoutY to DCLKoutX or SDCLKoutY F CLK = 245.76 MHz, R L = 100 Ω AC coupled | Any pair, same format (20) SDCLKoutY_MUX = 0 (device clock) | 50 | |||
| ts JESD204B | SYSREF to device clock setup time base reference. See SYSREF to Device Clock Alignment to adjust SYSREF to device clock setup time as required. | SDCLKoutY_MUX = 1 (SYSREF) SYSREF_DIV = 30 SYSREF_DDLY = 8 (global) SDCLKoutY_DDLY = 1 (2 cycles, local) DCLKoutX_MUX = 1 (Div+DCC+HS) DCLKoutX_DIV = 30 DCLKoutX_DDLY_CNTH = 7 DCLKoutX_DDLY_CNTL = 6 DCLKoutX_HS = 0 SDCLKoutY_HS = 0 | -80 | ps | ||
| t PD CLKin0_ SDCLKout1 | Propagation delay from CLKin0 to SDCLKout1 | CLKin0_OUT_MUX = 0 (SYSREF mux) SYSREF_CLKin0_MUX = 1 (CLKin0) SDCLKout1_PD = 0 SDCLKout1_DDLY = 0 (bypass) SDCLKout1_MUX = 1 (SR) EN_SYNC = 1 LVPECL16 /w 240 Ω | 0.65 | ns | ||
| f ADLY max | Maximum analog delay frequency | DCLKoutX_MUX = 4 | 1536 | MHz | ||
| LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout) | LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout) | LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout) | LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout) | LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout) | LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout) | LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout) |
| V OD | Differential output voltage | T = 25 °C, DC measurement AC coupled to receiver input R L = 100- Ω differential termination | 395 | |mV| | ||
| Δ V OD | Change in magnitude of V OD for complementary output states | T = 25 °C, DC measurement AC coupled to receiver input R L = 100- Ω differential termination | -60 | 60 | mV | |
| V OS | Output offset voltage | T = 25 °C, DC measurement AC coupled to receiver input R L = 100- Ω differential termination | 1.125 | 1.25 | 1.375 | V |
| Δ V OS | Change in V OS for complementary output states | T = 25 °C, DC measurement AC coupled to receiver input R L = 100- Ω differential termination | 35 | |mV| | ||
| T R / T F | Output rise time | 20% to 80%, R L = 100 Ω , 245.76 MHz | 180 | ps | ||
| T R / T F | Output fall time | 80% to 20%, R L = 100 Ω | 180 | |||
| I SA I SB | Output short circuit current - single ended | Single-ended output shorted to GND T = 25 °C | -24 | 24 | mA | |
| I SAB | Output short circuit current - differential | Complimentary outputs tied together | -12 | 12 | mA |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| TEST | PARAMETER | CONDITIONS | MIN TYP | MAX | UNIT |
|---|---|---|---|---|---|
| 6-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY) | |||||
| V OH T = 25 °C, DC | measurement | V CC - 1.05 | |||
| Termination = 50 V CC - 1.42 V V OL | Ω to | V CC - 1.64 | |||
| V OD | Differential output voltage | 590 | |mV| | ||
| Δ V OD | Change in V OD for complementary output states | -80 | 80 | mVpp | |
| 8-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY) | |||||
| T / T F | Output rise time | 245.76 MHz, 20% to 80%, R L = 100 Ω | 170 | ps | |
| R | Output fall time | 245.76 MHz, 80% to 20%, R L = 100 Ω | |||
| V OH T = 25 °C, DC | measurement | V CC - 1.26 | |||
| Termination = 50 V CC - 1.64 V V OL | Ω to | V CC -2.06 | |||
| V OD | Differential output voltage | 800 | |mV| | ||
| Δ V OD | Change in V OD for complementary output states | -115 | 115 | mVpp | |
| 10-mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY) | |||||
| V OH T = 25 °C, DC | measurement | V CC - 0.99 | |||
| Termination = 50 V CC - 1.43 V V OL | Ω to | V CC - 1.97 | |||
| V OD | 980 | |mv| | |||
| Δ V OD | Change in V OD for complementary output states | -115 | 115 | mVpp | |
| LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY) | |||||
| T / T F | 20% to 80% output rise | R L = 100 Ω , emitter resistors = 240 Ω to GND | 150 | ||
| R | 80% to 20% output fall time | DCLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp) | ps | ||
| 1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY) | |||||
| V OH | Output high voltage | V CC - 1.04 | V | ||
| DC measurement Termination = 50 V CC - 2.0 V V OL | Output low voltage | Ω to | V CC - 1.80 | V | |
| V OD | Output voltage Figure 9 | 760 | |mV| | ||
| 2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY) | |||||
| V OH | Output high voltage | V CC - 1.09 | V | ||
| DC measurement Termination = 50 V OL | Output low voltage | Ω to V CC - 2.3 V | V CC - 2.05 | V | |
| V OD | Output voltage Figure 9 | 960 | |mV| | ||
| LCPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY) | |||||
| V OH | Output high voltage | 1.57 | V | ||
| V OL | Output low voltage | DC measurement | 0.62 | V | |
| Termination = 50 V OD | Output voltage Figure 9 | Ω to 0.5 V | 950 | |mV| |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| LVCMOS CLOCK OUTPUTS (OSCout) | LVCMOS CLOCK OUTPUTS (OSCout) | LVCMOS CLOCK OUTPUTS (OSCout) | LVCMOS CLOCK OUTPUTS (OSCout) | LVCMOS CLOCK OUTPUTS (OSCout) | LVCMOS CLOCK OUTPUTS (OSCout) | LVCMOS CLOCK OUTPUTS (OSCout) |
| f CLKout | Maximum frequency (21) | 5-pF load | 250 | MHz | ||
| V OH | Output high voltage | 1-mA load | V CC - 0.1 | V | ||
| V OL | Output low voltage | 1-mA load | 0.1 | V | ||
| I OH | Output high current (source) | V CC = 3.3 V, V O = 1.65 V | 28 | mA | ||
| I OL | Output low current (sink) | V CC = 3.3 V, V O = 1.65 V | 28 | mA | ||
| DUTY CLK | Output duty cycle (22) | V CC /2 to V CC /2, F CLK = 100 MHz, T = 25 °C | 50% | |||
| T R | Output rise time | 20% to 80%, R L = 50 Ω , C L = 5 pF | 400 | ps | ||
| T F | Output fall time | 80% to 20%, R L = 50 Ω , C L = 5 pF | 400 | ps | ||
| DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) | DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) | DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) | DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) | DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) | DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) | DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO) |
| V OH | High-level output voltage | I OH = -500 μA CLKin_SELX_TYPE = 3 or 4 Status_LDX_TYPE = 3 or 4 RESET_TYPE = 3 or 4 | V CC - 0.4 | V | ||
| V OL | Low-level output voltage | I OL = 500 μA CLKin_SELX_TYPE = 3, 4, or 6 Status_LDX_TYPE = 3, 4, or 6 RESET_TYPE = 3, 4, or 6 | 0.4 | V | ||
| DIGITAL OUTPUT (SDIO) | DIGITAL OUTPUT (SDIO) | DIGITAL OUTPUT (SDIO) | DIGITAL OUTPUT (SDIO) | DIGITAL OUTPUT (SDIO) | DIGITAL OUTPUT (SDIO) | DIGITAL OUTPUT (SDIO) |
| V OH | High-level output voltage | I OH = -500 μA ; During SPI read. SDIO_RDBK_TYPE = 0 | V CC - 0.4 | V | ||
| V OL | Low-level output voltage | I OL = 500 μA ; During SPI read. SDIO_RDBK_TYPE = 0 or 1 | 0.4 | V | ||
| DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) | DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) | DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) | DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) | DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) | DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) | DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) |
| V IH | High-level input voltage | 1.2 | V CC | V | ||
| V IL | Low-level input voltage | 0.4 | V | |||
| DIGITAL INPUTS (CLKinX_SEL) | DIGITAL INPUTS (CLKinX_SEL) | DIGITAL INPUTS (CLKinX_SEL) | DIGITAL INPUTS (CLKinX_SEL) | DIGITAL INPUTS (CLKinX_SEL) | DIGITAL INPUTS (CLKinX_SEL) | DIGITAL INPUTS (CLKinX_SEL) |
| I IH | High-level input current V IH = V CC | CLKin_SELX_TYPE = 0, (high impedance) | -5 | 5 | μA | |
| I IH | High-level input current V IH = V CC | CLKin_SELX_TYPE = 1 (pull-up) | -5 | 5 | μA | |
| I IH | High-level input current V IH = V CC | CLKin_SELX_TYPE = 2 (pull-down) | 10 | 80 | μA | |
| I IL | Low-level input current V IL = 0 V | CLKin_SELX_TYPE = 0, (high impedance) | -5 | 5 | μA | |
| I IL | Low-level input current V IL = 0 V | CLKin_SELX_TYPE = 1 (pull-up) | -40 | -5 | μA | |
| I IL | Low-level input current V IL = 0 V | CLKin_SELX_TYPE = 2 (pull-down) | -5 | 5 | μA | |
| DIGITAL INPUT (RESET/GPO) | DIGITAL INPUT (RESET/GPO) | DIGITAL INPUT (RESET/GPO) | DIGITAL INPUT (RESET/GPO) | DIGITAL INPUT (RESET/GPO) | DIGITAL INPUT (RESET/GPO) | DIGITAL INPUT (RESET/GPO) |
| I IH | High-level input current V IH = V CC | RESET_TYPE = 2 (pull-down) | 10 | 80 | μA | |
| I IL | RESET_TYPE = 0 (high impedance) | -5 | 5 | |||
| Low-level input current V IL = 0 V | RESET_TYPE = 1 (pull-up) | -40 | -5 | μA | ||
| Low-level input current V IL = 0 V | RESET_TYPE = 2 (pull-down) | -5 | 5 | μA | ||
| DIGITAL INPUTS (SYNC) | DIGITAL INPUTS (SYNC) | DIGITAL INPUTS (SYNC) | DIGITAL INPUTS (SYNC) | DIGITAL INPUTS (SYNC) | DIGITAL INPUTS (SYNC) | DIGITAL INPUTS (SYNC) |
| I IH | High-level input current | V IH = V CC | 25 | |||
| I IL | Low-level input current | V IL = 0 V | -5 | 5 | μA | |
| DIGITAL INPUTS (SCK, SDIO, CS*) | DIGITAL INPUTS (SCK, SDIO, CS*) | DIGITAL INPUTS (SCK, SDIO, CS*) | DIGITAL INPUTS (SCK, SDIO, CS*) | DIGITAL INPUTS (SCK, SDIO, CS*) | DIGITAL INPUTS (SCK, SDIO, CS*) | DIGITAL INPUTS (SCK, SDIO, CS*) |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
| PARAMETER | CONDITIONS | TEST | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| I IH | High-level input current | V IH = V CC | -5 | 5 | μA | |
| I IL | Low-level input current | V IL = 0 | -5 | 5 | μA | |
| DIGITAL INPUT TIMING | DIGITAL INPUT TIMING | |||||
| t HIGH | RESET pin held high for device reset | 25 | ns |
(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)
LMK04828B/26B Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| V CC | Supply voltage (2) | -0.3 | 3.6 | V |
| V IN | Input voltage | -0.3 | (V CC + 0.3) | V |
| T L | Lead temperature (solder 4 seconds) | 260 | °C | |
| T J | Junction temperature | 150 | °C | |
| I IN | Differential input current (CLKinX/X*, OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) | ± 5 | mA | |
| MSL | Moisture sensitivity level | 3 | ||
| T stg | Storage temperature | -65 | 150 | °C |
LMK04828B/26B Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| T J | Junction temperature | 125 | °C | ||
| T A | Ambient temperature | -40 | 25 | 85 | °C |
| T PCB | PCB temperature (measured at thermal pad) | 105 | °C | ||
| V CC | Supply voltage | 3.15 | 3.3 | 3.45 | V |
LMK04828B/26B Thermal Information
| THERMAL METRIC | (1) | LMK0482x NKD (WQFN) 64 PINS | UNIT |
|---|---|---|---|
| R θ JA | Junction-to-ambient thermal resistance (2) | 24.3 | °C/W |
| R θ JC(top) | Junction-to-case (top) thermal resistance (3) | 6.1 | °C/W |
| R θ JB | Junction-to-board thermal resistance (4) | 3.5 | °C/W |
LMK04828B/26B Typical Application
To assist customers in frequency planning and designing loop filters, Texas Instruments provides PLLatinum Sim (www.ti.com/tool/PLLATINUMSIM-SW) and TICS Pro (www.ti.com/tool/TICSPRO-SW).
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| LMK04828 | Texas Instruments | WQFN-64 9x9mm |
| LMK04828-EP | Texas Instruments | WQFN-64 9x9mm |
| LMK04828B | Texas Instruments | WQFN-64 9x9mm |
| LMK04828BISQ | Texas Instruments | WQFN-64 9x9mm |
| LMK04828BISQ/NOPB | Texas Instruments | 64-Pin QFN |
| LMK04828BISQE/NOPB | Texas Instruments | WQFN-64 9x9mm |
| LMK04828BISQX | Texas Instruments | WQFN-64 9x9mm |
| LMK04828BISQX/NOPB | Texas Instruments | WQFN-64 9x9mm |
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