LMK04828BISQ

The LMK04828BISQ is an electronic component from Texas Instruments. View the full LMK04828BISQ datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

Texas Instruments

Overview

Part: LMK04821, LMK04826, LMK04828

Type: Clock Jitter Cleaner with Dual Loop PLLs

Description: Ultra-Low RMS Jitter JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs, offering up to 14 differential device clocks and a maximum output frequency of 3.1 GHz.

Operating Conditions:

Supply voltage: 3.15-V to 3.45-V
Operating temperature: -40 to 85°C
PCB temperature: Supports 105°C (Measured at Thermal Pad)
Maximum clock output frequency: 3.1 GHz

Key Specs:

RMS Jitter (12 kHz to 20 MHz): -88 fs
RMS Jitter (100 Hz to 20 MHz): -91 fs
Noise Floor at 245.76 MHz: -162.5 dBc/Hz
PLL2 Normalized [1 Hz] PLL Noise Floor: -227 dBc/Hz
PLL2 Phase Detector Rate: up to 155 MHz
Output Divides: 1 to 32 (even and odd)
Analog Delay Step: 25 ps

Features:

JEDEC JESD204B Support
Up to 14 Differential Device Clocks from PLL2
Up to 7 SYSREF Clocks
LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
Up to 1 Buffered VCXO/Crystal Output from PLL1 (LVPECL, LVDS, 2xLVCMOS Programmable)
Dual Loop PLLatinum™ PLL Architecture
PLL1: Up to 3 Redundant Input Clocks, Automatic and Manual Switch-Over Modes, Hitless Switching and LOS, Integrated Low-Noise Crystal Oscillator Circuit, Holdover mode
PLL2: Two Integrated Low-Noise VCOs, 50% Duty Cycle Output Divides, Precision Digital Delay, Dynamically Adjustable
Multi-mode: Dual PLL, single PLL, and Clock Distribution

Applications:

Wireless Infrastructure
Data Converter Clocking
Networking, SONET/SDH, DSLAM
Medical / Video / Military / Aerospace
Test and Measurement

Package:

64-Pin QFN (9.0 mm x 9.0 mm x 0.8 mm)

Features

1 · JEDEC JESD204B Support
Ultra-Low RMS Jitter
-88 fs RMS Jitter (12 kHz to 20 MHz)
-91 fs RMS Jitter (100 Hz to 20 MHz)
--162.5 dBc/Hz Noise Floor at 245.76 MHz
Up to 14 Differential Device Clocks from PLL2
-Up to 7 SYSREF Clocks
-Maximum Clock Output Frequency 3.1 GHz
-LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
Up to 1 Buffered VCXO/Crystal Output from PLL1
-LVPECL, LVDS, 2xLVCMOS Programmable
Dual Loop PLLatinum™ PLL Architecture
PLL1
-Up to 3 Redundant Input Clocks
-Automatic and Manual Switch-Over Modes
-Hitless Switching and LOS
-Integrated Low-Noise Crystal Oscillator Circuit
-Holdover mode when Input Clocks are Lost

Applications

Wireless Infrastructure
Data Converter Clocking
Networking, SONET/SDH, DSLAM
Medical / Video / Military / Aerospace
Test and Measurement

Pin Configuration

Pin Functions

Pin Functions

PIN	PIN	I/O	TYPE	DESCRIPTION (1)
NO.	NAME	I/O	TYPE	DESCRIPTION (1)
1, 2	DCLKout0, DCLKout0*	O	Programmable	Device clock output 0.
3, 4	SDCLKout1, SDCLKout1*	O	Programmable	SYSREF / Device clock output 1
5	RESET/GPO	I	CMOS	Device reset input or GPO
6	SYNC/SYSREF_REQ	I	CMOS	Synchronization input or SYSREF_REQ for requesting continuous SYSREF.
7, 8, 9	NC			Do not connect. These pins must be left floating.
10	Vcc1_VCO		PWR	Power supply for VCO LDO.
11	LDObyp1		ANLG	LDO Bypass, bypassed to ground with 10-μF capacitor.
12	LDObyp2		ANLG	LDO Bypass, bypassed to ground with a 0.1-μF capacitor.
13, 14	SDCLKout3, SDCLKout3*	O	Programmable	SYSREF / Device Clock output 3.
15, 16	DCLKout2, DCLKout2*	O	Programmable	Device clock output 2.
17	Vcc2_CG1		PWR	Power supply for clock outputs 2 and 3.
18	CS*	I	CMOS	Chip Select
19	SCK	I	CMOS	SPI Clock

Electrical Characteristics

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION
I CC_PD	Power Down Supply Current			1	3	mA
I CC_CLKS	Supply Current (1)	14 HSDS 8 mA clocks enabled PLL1 and PLL2 locked.		565	665	mA
CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS	CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS	CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS	CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS	CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS	CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS	CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS
f CLKin	Clock Input Frequency		0.001		750	MHz
SLEW CLKin	Clock Input Slew Rate (2)	20% to 80%	0.15	0.5		V/ns
V ID CLKin	Clock Input Differential Input Voltage (3) Figure 8	AC coupled	0.125		1.55	\
V SS CLKin	Clock Input Differential Input Voltage (3) Figure 8	AC coupled	0.25		3.1	Vpp
V CLKin	Clock Input Single-ended Input Voltage	AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_TYPE = 0 (Bipolar)	0.25		2.4	Vpp
V CLKin	Clock Input Single-ended Input Voltage	AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_TYPE = 1 (MOS)	0.35		2.4	Vpp
\	V CLKinX-offset \		DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX)	Each pin AC coupled, CLKin0/1/2 CLKinX_TYPE = 0 (Bipolar)		0
\	V CLKinX-offset \		DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX)	Each pin AC coupled, CLKin0/1 CLKinX_TYPE = 1 (MOS)		55
\	V CLKinX-offset \		DC offset voltage between CLKin2/CLKin2* (CLKin2* - CLKin2)	Each pin AC coupled CLKinX_TYPE = 1 (MOS)		20
V CLKin- V IH	High input voltage	DC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_TYPE = 1 (MOS)	2.0		V CC	V
V CLKin- V IL	Low input voltage	DC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_TYPE = 1 (MOS)	0.0		0.4	V
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS	FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS	FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS	FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS	FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS	FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS	FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS
f FBCLKin	Clock Input Frequency for 0-delay with external feedback.	AC coupled CLKinX_TYPE = 0 (Bipolar)	0.001		750	MHz
f Fin	Clock Input Frequency for external VCO or distribution mode.	AC coupled (4) CLKinX_TYPE = 0 (Bipolar)	0.001		3100	MHz

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V FBCLKin/Fin	Single Ended Clock Input Voltage	AC coupled CLKinX_TYPE = 0 (Bipolar)	0.25		2.0	Vpp
SLEW FBCLKin/Fin	Slew Rate on CLKin (2)	AC coupled; 20% to 80%; (CLKinX_TYPE = 0)	0.15	0.5		V/ns
PLL1 SPECIFICATIONS	PLL1 SPECIFICATIONS	PLL1 SPECIFICATIONS	PLL1 SPECIFICATIONS	PLL1 SPECIFICATIONS	PLL1 SPECIFICATIONS	PLL1 SPECIFICATIONS
f PD1	PLL1 Phase Detector Frequency	V CPout1 = V CC /2, PLL1_CP_GAIN = 0		50	40	MHz μA
	PLL1 Charge Pump Source Current (5)	V CPout1 = V CC /2, PLL1_CP_GAIN = 1		150		μA
I SOURCE		V CPout1 = V CC /2, PLL1_CP_GAIN = 2		250		μA
CPout1		…		…		μA
CPout1		V CPout1 = V CC /2, PLL1_CP_GAIN = 14		1450		μA
CPout1		V CPout1 = V CC /2, PLL1_CP_GAIN = 15		1550		μA
I CPout1 SINK		V CPout1 =V CC /2, PLL1_CP_GAIN = 0		-50		μA
I CPout1 SINK		V CPout1 =V CC /2, PLL1_CP_GAIN = 1		-150		μA
	PLL1 Charge (5)	V CPout1 =V CC /2, PLL1_CP_GAIN = 2		-250		μA
	Pump Sink Current	… V CPout1 =V CC /2, PLL1_CP_GAIN = 14 V CPout1 =V CC /2, PLL1_CP_GAIN = 15		… -1450 -1550		μA μA μA
I CPout1 %MIS	Charge Pump Sink / Source Mismatch	V CPout1 = V CC /2, T = 25 °C		1%	10%
I CPout1 V TUNE	Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage	0.5 V < V CPout1 < V CC - 0.5 V T A = 25 °C		4%
I CPout1 %TEMP	Charge Pump Current vs. Temperature Variation			4%
I CPout1 TRI	Charge Pump TRI-STATE Leakage Current	0.5 V < V CPout < V CC - 0.5 V			5	nA
PN10kHz	PLL 1/f Noise at 10 kHz offset.	PLL1_CP_GAIN = 350 μA		-117		dBc/Hz
	Normalized to 1 GHz Output Frequency	PLL1_CP_GAIN = 1550 μA		-118		dBc/Hz
PN1Hz	Normalized Phase Noise Contribution	PLL1_CP_GAIN = 350 μA PLL1_CP_GAIN = 1550 μA		-221.5 -223		dBc/Hz
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS	PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS	PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS	PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS	PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS	PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS	PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
f OSCin	PLL2 Reference Input (6)				500	MHz
SLEW OSCin	PLL2 Reference Clock minimum slew rate on OSCin (2)	20% to 80%	0.15	0.5		V/ns
V OSCin	Input Voltage for OSCin or OSCin*	AC coupled; Single-ended (Unused pin AC coupled to GND)	0.2		2.4	Vpp
V ID OSCin	Differential voltage swing	AC coupled	0.2		1.55	\
V SS OSCin	Figure 8	AC coupled	0.4		3.1	Vpp
\	V OSCin-offset \		DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX)	Each pin AC coupled		20
f doubler_max	Doubler input frequency (7)	EN_PLL2_REF_2X = 1 (8) ; OSCin Duty Cycle 40% to 60%			155	MHz

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
CRYSTAL OSCILLATOR MODE SPECIFICATIONS	CRYSTAL OSCILLATOR MODE SPECIFICATIONS	CRYSTAL OSCILLATOR MODE SPECIFICATIONS	CRYSTAL OSCILLATOR MODE SPECIFICATIONS	CRYSTAL OSCILLATOR MODE SPECIFICATIONS	CRYSTAL OSCILLATOR MODE SPECIFICATIONS	CRYSTAL OSCILLATOR MODE SPECIFICATIONS
F XTAL	Crystal Frequency Range	Fundamental mode crystal ESR = 200 Ω (10 to 30 MHz) ESR = 125 Ω (30 to 40 MHz)	10		40	MHz
C IN	Input Capacitance of OSCin port	-40 to 85 °C		1		pF
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS	PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS	PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS	PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS	PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS	PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS	PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS
f PD2	Phase Detector Frequency (7)				155	MHz
I CPout SOURCE	PLL2 Charge Pump Source Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 0		100		μA
I CPout SOURCE	PLL2 Charge Pump Source Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 1		400		μA
I CPout SOURCE	PLL2 Charge Pump Source Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 2		1600		μA
I CPout SOURCE	PLL2 Charge Pump Source Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 3		3200		μA
I CPout SINK	PLL2 Charge Pump Sink Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 0		-100		μA
I CPout SINK	PLL2 Charge Pump Sink Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 1		-400		μA
I CPout SINK	PLL2 Charge Pump Sink Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 2		-1600		μA
I CPout SINK	PLL2 Charge Pump Sink Current (5)	V CPout2 =V CC /2, PLL2_CP_GAIN = 3		-3200		μA
I CPout2 %MIS	Charge Pump Sink/Source Mismatch	V CPout2 =V CC /2, T A = 25 °C		1%	10%
I CPout2 V TUNE	Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation	0.5 V < V CPout2 < V CC - 0.5 V T A = 25 °C		4%
I CPout2 %TEMP	Charge Pump Current vs. Temperature Variation			4%
I CPout2 TRI	Charge Pump Leakage	0.5 V < V CPout2 < V CC - 0.5 V			10	nA
PN10kHz	PLL 1/f Noise at 10 kHz offset (9) . Normalized to 1 GHz Output Frequency	PLL2_CP_GAIN = 400 μA		-118		dBc/Hz
PN10kHz	PLL 1/f Noise at 10 kHz offset (9) . Normalized to 1 GHz Output Frequency	PLL2_CP_GAIN = 3200 μA		-121		dBc/Hz
PN1Hz	Normalized Phase Noise Contribution (10)	PLL2_CP_GAIN = 400 μA		-222.5		dBc/Hz
PN1Hz	Normalized Phase Noise Contribution (10)	PLL2_CP_GAIN = 3200 μA		-227		dBc/Hz

(9) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L PLL_flicker (f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker (f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker (f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L PLL_flicker (f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L PLL_flicker (f) and LPLL_flat (f).
(10) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat (f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(f PDX ). L PLL_flat (f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. L PLL_flat (f) contributes to the total noise, L(f).

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

PARAMETER	PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
INTERNAL VCO SPECIFICATIONS	INTERNAL VCO SPECIFICATIONS	INTERNAL VCO SPECIFICATIONS	INTERNAL VCO SPECIFICATIONS	INTERNAL VCO SPECIFICATIONS	INTERNAL VCO SPECIFICATIONS
	LMK04821 VCO Tuning Range	VCO0	1930	2075	MHz
		VCO1 (11)	2920	3080	MHz
f VCO	LMK04826 VCO Tuning Range	VCO0	1840	1970	MHz
f VCO		VCO1	2440	2505	MHz
	LMK04828 VCO Tuning Range	VCO0	2370	2630	MHz
		VCO1	2920	3080	MHz
	LMK04821 Fine Tuning Sensitivity	LMK04821 VCO0	12 to 20		MHz/V
		LMK04821 VCO1	15 to 24		MHz/V
K VCO	LMK04826 Fine Tuning Sensitivity	LMK04826 VCO0	11 to 19		MHz/V
K VCO		LMK04826 VCO1	8 to 11		MHz/V
	LMK04828 Fine Tuning Sensitivity	LMK04828 VCO0 at 2457.6 MHz	17 to 27		MHz/V
		LMK04828 VCO1 at 2949.12 MHz	17 to 23		MHz/V
\	Δ T CL \		Allowable Temperature Drift for Continuous Lock (12)	After programming for lock, no changes to output configuration are permitted to assure continuous lock	125

	PARAMETER	TEST CONDITIONS	MIN TYP	UNIT
NOISE FLOOR
L(f) CLKout		LVDS	-158.2	dBc/Hz
L(f) CLKout		HSDS 6 mA	-160	dBc/Hz
L(f) CLKout		HSDS 8 mA	-161	dBc/Hz
L(f) CLKout	LMK04821, VCO0, Noise Floor 245.76 Offset (13)	HSDS 10 mA	-161.4	dBc/Hz
L(f) CLKout		LVPECL16 /w 240 Ω	-161.6	dBc/Hz
L(f) CLKout		LVPECL20 /w 240 Ω	-162	dBc/Hz
L(f) CLKout		LVPECL	161.7	dBc/Hz
L(f) CLKout		LVDS	-157.1	dBc/Hz
L(f) CLKout		HSDS 6 mA	-158.3	dBc/Hz
L(f) CLKout		HSDS 8 mA	-159	dBc/Hz
L(f) CLKout	LMK04821, VCO1, Noise Floor 245.76 Offset (13)	HSDS 10 mA	-159.2	dBc/Hz
L(f) CLKout		LVPECL16 /w 240 Ω	-158.8	dBc/Hz
L(f) CLKout		LVPECL20 /w 240 Ω	-158.9	dBc/Hz
L(f) CLKout		LVPECL	-158.8	dBc/Hz
L(f) CLKout	LMK04826, VCO0, Noise Floor 245.76 Offset (14)	LVDS	-158.1	dBc/Hz
L(f) CLKout		HSDS 6 mA	-159.7	dBc/Hz
L(f) CLKout		HSDS 8 mA	-160.8	dBc/Hz
L(f) CLKout		HSDS 10 mA	-161.3	dBc/Hz
L(f) CLKout		LVPECL16 /w 240 Ω	-161.8	dBc/Hz
L(f) CLKout		LVPECL20 /w 240 Ω	-162	dBc/Hz
L(f) CLKout		LCPECL	-161.7	dBc/Hz
L(f) CLKout	LMK04826, VCO1, Noise Floor 245.76 Offset (14)	LVDS	-157.5	dBc/Hz
L(f) CLKout		HSDS 6 mA	-158.9	dBc/Hz
L(f) CLKout		HSDS 8 mA	-159.8	dBc/Hz
L(f) CLKout		HSDS 10 mA	-160.3	dBc/Hz
L(f) CLKout		LVPECL16 /w 240 Ω	-160.8	dBc/Hz
L(f) CLKout		LVPECL20 /w 240 Ω	-160.7	dBc/Hz
L(f) CLKout		LCPECL	-160.7	dBc/Hz

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

PARAMETER	PARAMETER	TEST CONDITIONS	TEST CONDITIONS	MIN TYP	MAX	UNIT
NOISE FLOOR (continued)	NOISE FLOOR (continued)	NOISE FLOOR (continued)	NOISE FLOOR (continued)	NOISE FLOOR (continued)	NOISE FLOOR (continued)	NOISE FLOOR (continued)
L(f) CLKout		245.76 MHz	LVDS	-156.3		dBc/Hz
L(f) CLKout		245.76 MHz	HSDS 6 mA	-158.4		dBc/Hz
L(f) CLKout		245.76 MHz	HSDS 8 mA	-159.3		dBc/Hz
L(f) CLKout		245.76 MHz	HSDS 10 mA	-158.9		dBc/Hz
L(f) CLKout		245.76 MHz	LVPECL16 /w 240 Ω	-161.6		dBc/Hz
L(f) CLKout		245.76 MHz	LVPECL20 /w 240 Ω	-162.5		dBc/Hz
L(f) CLKout		245.76 MHz	LCPECL	-162.1		dBc/Hz
L(f) CLKout		245.76 MHz	LVDS	-155.7		dBc/Hz
L(f) CLKout		245.76 MHz	HSDS 6 mA	-157.5		dBc/Hz
L(f) CLKout		245.76 MHz	HSDS 8 mA	-158.1		dBc/Hz
L(f) CLKout		245.76 MHz	HSDS 10 mA	-157.7		dBc/Hz
L(f) CLKout	20	245.76 MHz	LVPECL16 /w 240 Ω	-160.3		dBc/Hz
L(f) CLKout		245.76 MHz	LVPECL20 /w 240 Ω	-161.1		dBc/Hz
L(f) CLKout		245.76 MHz	LCPECL	-160.8		dBc/Hz
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)
L(f) CLKout		Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz		-126.9 -133.5 -135.4 -149.8		dBc/Hz dBc/Hz dBc/Hz dBc/Hz
		Offset = 10 MHz	LVDS HSDS 8 mA LVPECL16 /w 240 Ω	-158.1 -161.1 -161.7		dBc/Hz dBc/Hz dBc/Hz
L(f) CLKout		Offset = 1 kHz		-126.8		dBc/Hz
L(f) CLKout		Offset = 10 kHz		-133.4		dBc/Hz
L(f) CLKout		Offset = 100 kHz Offset = 1 MHz	LVDS	-135.4 -151.8 -157.2		dBc/Hz dBc/Hz dBc/Hz
		Offset = 10 MHz	HSDS 8 mA LVPECL16 /w 240 Ω	-159.1 -158.9		dBc/Hz dBc/Hz

PARAMETER	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)	CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued)
		Offset = 10 kHz	Offset = 10 kHz	-134.8		dBc/Hz
		Offset = 100 kHz	Offset = 100 kHz	-135.4		dBc/Hz
		Offset = 1 MHz	LVDS	-148.2		dBc/Hz
		Offset = 1 MHz	HSDS 8 mA LVPECL16 /w 240 Ω	-148.6		dBc/Hz
		Offset = 10 MHz	LVDS	-157.8		dBc/Hz
		Offset = 10 MHz	HSDS 8 mA	-160.4		dBc/Hz
		Offset = 10 MHz	LVPECL16 /w 240 Ω	-161.5		dBc/Hz
		Offset = 10 kHz	Offset = 10 kHz	-134.3		dBc/Hz
		Offset = 100 kHz	Offset = 100 kHz	-133.7		dBc/Hz
	LMK04826B VCO1 SSB Phase Noise (14) 245.76 MHz	Offset = 1 MHz	LVDS	-152.5		dBc/Hz
	LMK04826B VCO1 SSB Phase Noise (14) 245.76 MHz	Offset = 1 MHz	HSDS 8 mA LVPECL16 /w 240 Ω	-153.6		dBc/Hz
		Offset = 10 MHz	LVDS	-157.3		dBc/Hz
		Offset = 10 MHz	HSDS 8 mA	-159.6		dBc/Hz
		Offset = 10 MHz	LVPECL16 /w 240 Ω	-160.5		dBc/Hz
		Offset = 1 kHz	Offset = 1 kHz	-124.3		dBc/Hz
		Offset = 10 kHz	Offset = 10 kHz	-134.7		dBc/Hz
		Offset = 100 kHz	Offset = 100 kHz	-136.5		dBc/Hz
		Offset = 1 MHz	Offset = 1 MHz	-148.4		dBc/Hz
		Offset = 10 MHz	LVDS	-156.4		dBc/Hz
		Offset = 10 MHz	HSDS 8 mA	-159.1		dBc/Hz
		Offset = 10 MHz	LVPECL16 /w 240 Ω	-160.8		dBc/Hz
		Offset = 1 kHz	Offset = 1 kHz	-124.2		dBc/Hz
		Offset = 10 kHz	Offset = 10 kHz	-134.4		dBc/Hz
		Offset = 100 kHz	Offset = 100 kHz	-135.2		dBc/Hz
	VCO1 SSB Phase Noise (15)	Offset = 1 MHz	Offset = 1 MHz	-151.5		dBc/Hz
	VCO1 SSB Phase Noise (15)	Offset = 10 MHz	LVDS	-159.9		dBc/Hz
	VCO1 SSB Phase Noise (15)	Offset = 10 MHz	HSDS 8 mA	-155.8		dBc/Hz
	VCO1 SSB Phase Noise (15)	Offset = 10 MHz	LVPECL16 /w 240 Ω	-158.1		dBc/Hz

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

PARAMETER	TEST CONDITIONS	TYP	MAX	UNIT
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (16)
	LVDS, BW = 12 kHz to 20 MHz	99		fs rms
	HSDS 8 mA, BW = 12 kHz to 20 MHz	94		fs rms
	LVPECL16 /w 240 Ω , BW = 12 kHz to 20 MHz	96		fs rms
	LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz	94		fs rms
	LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz	93		fs rms
J CLKout	LVDS, BW = 12 kHz to 20 MHz	96		fs rms
J CLKout	HSDS 8 mA, BW = 12 kHz to 20 MHz	90		fs rms
J CLKout	LVPECL16 /w 240 Ω , BW = 12 kHz to 20 MHz	92		fs rms
J CLKout	LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz	91		fs rms
J CLKout	LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz	91		fs rms
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)
	LVDS, BW = 100 Hz to 20 MHz	106		fs rms
	LVDS, BW = 12 kHz to 20 MHz	104		fs rms
	HSDS 8 mA, BW = 100 Hz to 20 MHz	99		fs rms
	HSDS 8 mA, BW = 12 kHz to 20 MHz	97		fs rms
	LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz	99		fs rms
	LVPECL16 /w 240 Ω , BW = 12 kHz to 20 MHz	96		fs rms
	LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz	100		fs rms
	LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz	97		fs rms
J CLKout	LVDS, BW = 100 Hz to 20 MHz	99		fs rms
J CLKout	LVDS, BW = 12 kHz to 20 MHz	97		fs rms
J CLKout	HSDS 8 mA, BW = 100 Hz to 20 MHz	92		fs rms
J CLKout	HSDS 8 mA, BW = 12 kHz to 20 MHz	90		fs rms
J CLKout	LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz	91		fs rms
J CLKout	LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz	89		fs rms
J CLKout	LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz	92		fs rms
J CLKout	LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz	89		fs rms

PARAMETER	PARAMETER	TEST CONDITIONS	MIN TYP	UNIT
CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)	CLKout CLOSED LOOP JITTER SPECIFICATIONS a COMMERCIAL QUALITY VCXO (continued) (16)
		LVDS, BW = 100 Hz to 20 MHz	112	fs rms
		LVDS, BW = 12 kHz to 20 MHz	109	fs rms
		HSDS 8 mA, BW = 100 Hz to 20 MHz	102	fs rms
		HSDS 8 mA, BW = 12 kHz to 20 MHz	99	fs rms
		LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz	98	fs rms
		LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz	95	fs rms
		LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz	96	fs rms
		LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz	93	fs rms
	J CLKout	LVDS, BW = 100 Hz to 20 MHz LVDS, BW = 12 kHz to 20 MHz HSDS 8 mA, BW = 100 Hz to 20 MHz HSDS 8 mA, BW = 12 kHz to 20 MHz LVPECL16 /w 240 Ω , BW = 100 Hz to 20 MHz LVPECL20 /w 240 Ω , BW = 12 kHz to 20 MHz LCPECL /w 240 Ω , BW = 100 Hz to 20 MHz LCPECL /w 240 Ω , BW = 12 kHz to 20 MHz	108 105 98 94 93 90 91 88

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY	DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY	DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY	DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY	DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY	DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY	DEFAULT POWER on RESET CLOCK OUTPUT FREQUENCY
f CLKout-startup	Default output clock frequency at	LMK04826		235		MHz
f CLKout-startup	device power on (17)(18)	LMK04828		315
f OSCout	OSCout Frequency	(7)			500	MHz
CLOCK SKEW and DELAY	CLOCK SKEW and DELAY	CLOCK SKEW and DELAY	CLOCK SKEW and DELAY	CLOCK SKEW and DELAY	CLOCK SKEW and DELAY	CLOCK SKEW and DELAY
\	T SKEW \		DCLKoutX to SDCLKoutY F CLK = 245.76 MHz, R L = 100 Ω AC coupled (19)	Same pair, Same format (20) SDCLKoutY_MUX = 0 (Device Clock)
\	T SKEW \		Maximum DCLKoutX or SDCLKoutY to DCLKoutX or SDCLKoutY F CLK = 245.76 MHz, R L = 100 Ω AC coupled	Any pair, Same format (20) SDCLKoutY_MUX = 0 (Device Clock)		50
ts JESD204B	SYSREF to Device Clock setup time base reference. See SYSREF to Device Clock Alignment to adjust SYSREF to Device Clock setup time as required.	SDCLKoutY_MUX = 1 (SYSREF) SYSREF_DIV = 30 SYSREF_DDLY = 8 (global) SDCLKoutY_DDLY = 1 (2 cycles, local) DCLKoutX_MUX = 1 (Div+DCC+HS) DCLKoutX_DIV = 30 DCLKoutX_DDLY_CNTH = 7 DCLKoutX_DDLY_CNTL = 6 DCLKoutX_HS = 0 SDCLKoutY_HS = 0		-80		ps
t PD CLKin0_ SDCLKout1	Propagation Delay from CLKin0 to SDCLKout1	CLKin0_OUT_MUX = 0 (SYSREF Mux) SYSREF_CLKin0_MUX = 1 (CLKin0) SDCLKout1_PD = 0 SDCLKout1_DDLY = 0 (Bypass) SDCLKout1_MUX = 1 (SR) EN_SYNC = 1 LVPECL16 /w 240 Ω		0.65		ns
f ADLY max	Maximum analog delay frequency	DCLKoutX_MUX = 4		1536		MHz
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)	LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)	LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)	LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)	LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)	LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)	LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, and OSCout)
V OD	Differential Output Voltage	T = 25 °C, DC measurement AC coupled to receiver input R L = 100 Ω differential termination		395		\
Δ V OD	Change in Magnitude of V OD for complementary output states	T = 25 °C, DC measurement AC coupled to receiver input R L = 100 Ω differential termination	-60		60	mV
V OS	Output Offset Voltage	T = 25 °C, DC measurement AC coupled to receiver input R L = 100 Ω differential termination	1.125	1.25	1.375	V
Δ V OS	Change in V OS for complementary output states	T = 25 °C, DC measurement AC coupled to receiver input R L = 100 Ω differential termination			35	\
T R / T F	Output Rise Time	20% to 80%, R L = 100 Ω , 245.76 MHz		180		ps
T R / T F	Output Fall Time	80% to 20%, R L = 100 Ω		180
I SA I SB	Output short circuit current - single ended	Single-ended output shorted to GND T = 25 °C	-24		24	mA
I SAB	Output short circuit current - differential	Complimentary outputs tied together	-12		12	mA

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

	PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
6 mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
V OH T = 25 °C, DC		measurement	V CC - 1.05
Termination = 50 V OL V CC - 1.42 V		Ω to	V CC - 1.64
V OD	Differential Output Voltage		590		\
Δ V OD	Change in V OD for complementary output states		-80	80	mVpp
8 mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
T / T F	Output Rise Time	245.76 MHz, 20% to 80%, R L = 100 Ω	170		ps
R	Output Fall Time	245.76 MHz, 80% to 20%, R L = 100 Ω	V CC -
V OH T = 25 °C, DC		measurement	1.26
Termination = 50 V OL V CC - 1.64 V		Ω to	V CC -2.06
V OD	Differential Output Voltage		800		\
Δ V OD	Change in V OD for complementary output states		-115	115	mVpp
10 mA HSDS CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
V OH T = 25 °C, DC		measurement	V CC - 0.99
Termination = 50 V OL V CC - 1.43 V		Ω to	V CC - 1.97
V OD			980		mVpp
Δ V OD	Change in V OD for complementary output states		-115	115	mVpp
LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
T / T F	20% to 80% Output Rise	R L = 100 Ω , emitter resistors = 240 Ω to GND	150
R	80% to 20% Output Fall Time	DCLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp)			ps
1600 mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
V OH	Output High Voltage		V CC - 1.04		V
V OL	Output Low Voltage	DC Measurement Termination = 50 Ω to	V CC - 1.80		V
V OD	Output Voltage Figure 9	V CC - 2.0 V	760		\
2000 mVpp LVPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
V OH	Output High Voltage		V CC - 1.09		V
V OL	Output Low Voltage	DC Measurement Termination = 50 Ω to V CC - 2.3 V	V CC - 2.05		V
V OD	Output Voltage Figure 9		960		\
LCPECL CLOCK OUTPUTS (DCLKoutX and SDCLKoutY)
V OH	Output High Voltage		1.57		V
V OL	Output Low Voltage	DC Measurement	0.62		V
V OD	Output Voltage Figure 9	Termination = 50 Ω to 0.5 V	950		\

(3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C and TPCB ≤ 105 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.)

PARAMETER	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
LVCMOS CLOCK OUTPUTS (OSCout)	LVCMOS CLOCK OUTPUTS (OSCout)	LVCMOS CLOCK OUTPUTS (OSCout)	LVCMOS CLOCK OUTPUTS (OSCout)	LVCMOS CLOCK OUTPUTS (OSCout)	LVCMOS CLOCK OUTPUTS (OSCout)	LVCMOS CLOCK OUTPUTS (OSCout)
f CLKout	Maximum Frequency (21)	5 pF Load	250			MHz
V OH	Output High Voltage	1 mA Load	V CC - 0.1			V
V OL	Output Low Voltage	1 mA Load			0.1	V
I OH	Output High Current (Source)	V CC = 3.3 V, V O = 1.65 V		28		mA
I OL	Output Low Current (Sink)	V CC = 3.3 V, V O = 1.65 V		28		mA
DUTY CLK	Output Duty Cycle (22)	V CC /2 to V CC /2, F CLK = 100 MHz, T = 25 °C		50%
T R	Output Rise Time	20% to 80%, R L = 50 Ω , C L = 5 pF		400		ps
T F	Output Fall Time	80% to 20%, R L = 50 Ω , C L = 5 pF		400		ps
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)	DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)	DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)	DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)	DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)	DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)	DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, and RESET/GPO)
V OH	High-Level Output Voltage	I OH = -500 μA CLKin_SELX_TYPE = 3 or 4 Status_LDX_TYPE = 3 or 4 RESET_TYPE = 3 or 4	V CC - 0.4			V
V OL	Low-Level Output Voltage	I OL = 500 μA CLKin_SELX_TYPE = 3, 4, or 6 Status_LDX_TYPE = 3, 4, or 6 RESET_TYPE = 3, 4, or 6			0.4	V
DIGITAL OUTPUT (SDIO)	DIGITAL OUTPUT (SDIO)	DIGITAL OUTPUT (SDIO)	DIGITAL OUTPUT (SDIO)	DIGITAL OUTPUT (SDIO)	DIGITAL OUTPUT (SDIO)	DIGITAL OUTPUT (SDIO)
V OH	High-Level Output Voltage	I OH = -500 μA ; During SPI read. SDIO_RDBK_TYPE = 0	V CC - 0.4			V
V OL	Low-Level Output Voltage	I OL = 500 μA ; During SPI read. SDIO_RDBK_TYPE = 0 or 1			0.4	V
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)	DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)	DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)	DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)	DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)	DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)	DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*)
V IH	High-Level Input Voltage		1.2		V CC	V
V IL	Low-Level Input Voltage				0.4	V
DIGITAL INPUTS (CLKinX_SEL)	DIGITAL INPUTS (CLKinX_SEL)	DIGITAL INPUTS (CLKinX_SEL)	DIGITAL INPUTS (CLKinX_SEL)	DIGITAL INPUTS (CLKinX_SEL)	DIGITAL INPUTS (CLKinX_SEL)	DIGITAL INPUTS (CLKinX_SEL)
I IH	High-Level Input Current V IH = V CC	CLKin_SELX_TYPE = 0, (High Impedance)	-5		5	μA
I IH	High-Level Input Current V IH = V CC	CLKin_SELX_TYPE = 1 (Pull-up)	-5		5	μA
I IH	High-Level Input Current V IH = V CC	CLKin_SELX_TYPE = 2 (Pull-down)	10		80	μA
I IL	Low-Level Input Current V IL = 0 V	CLKin_SELX_TYPE = 0, (High Impedance)	-5		5	μA
I IL	Low-Level Input Current V IL = 0 V	CLKin_SELX_TYPE = 1 (Pull-up)	-40		-5	μA
I IL	Low-Level Input Current V IL = 0 V	CLKin_SELX_TYPE = 2 (Pull-down)	-5		5	μA
DIGITAL INPUT (RESET/GPO)	DIGITAL INPUT (RESET/GPO)	DIGITAL INPUT (RESET/GPO)	DIGITAL INPUT (RESET/GPO)	DIGITAL INPUT (RESET/GPO)	DIGITAL INPUT (RESET/GPO)	DIGITAL INPUT (RESET/GPO)
I IH	High-Level Input Current V IH = V CC	RESET_TYPE = 2 (Pull-down)	10		80	μA
I IL		RESET_TYPE = 0 (High Impedance)	-5		5
I IL	Low-Level Input Current V = 0 V	RESET_TYPE = 1 (Pull-up)	-40		-5	μA
I IL	IL	RESET_TYPE = 2 (Pull-down)	-5		5	μA
DIGITAL INPUTS (SYNC)	DIGITAL INPUTS (SYNC)	DIGITAL INPUTS (SYNC)	DIGITAL INPUTS (SYNC)	DIGITAL INPUTS (SYNC)	DIGITAL INPUTS (SYNC)	DIGITAL INPUTS (SYNC)
I IH	High-Level Input Current	V IH = V CC			25
I IL	Low-Level Input Current	V IL = 0 V	-5		5	μA
DIGITAL INPUTS (SCK, SDIO, CS*)	DIGITAL INPUTS (SCK, SDIO, CS*)

PARAMETER	CONDITIONS	TEST	MIN	MAX	UNIT
I IH	High-Level Input Current	V IH = V CC	-5	5	μA
I IL	Low-Level Input Current	V IL = 0	-5	5	μA
DIGITAL INPUT TIMING	DIGITAL INPUT TIMING
t HIGH		RESET pin held high for device reset	25		ns

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

		MIN	MAX	UNIT
V CC	Supply voltage (2)	-0.3	3.6	V
V IN	Input voltage	-0.3	(V CC + 0.3)	V
T L	Lead temperature (solder 4 seconds)		260	°C
T J	Junction temperature		150	°C
I IN	Differential input current (CLKinX/X, OSCin/OSCin, FBCLKin/FBCLKin, Fin/Fin)		± 5	mA
MSL	Moisture sensitivity level		3
T stg	Storage temperature	-65	150	°C

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
T J	Junction Temperature			125	°C
T A	Ambient Temperature	-40	25	85	°C
T PCB	PCB Temperature (measured at thermal pad)			105	°C
V CC	Supply Voltage	3.15	3.3	3.45	V

Thermal Information

THERMAL METRIC (1)	THERMAL METRIC (1)	LMK0482x NKD (WQFN) 64 PINS	UNIT
R θ JA	Junction-to-ambient thermal resistance (2)	24.3	°C/W
R θ JC(top)	Junction-to-case (top) thermal resistance (3)	6.1	°C/W
R θ JB	Junction-to-board thermal resistance (4)	3.5	°C/W

Typical Application

To assist customers in frequency planning and design of loop filters Texas Instrument's provides the Clock Design Tool (www.ti.com/tool/clockdesigntool) and Clock Architect (www.ti.com/clockarchitect).

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
LMK04828	Texas Instruments	—
LMK04828-EP	Texas Instruments	—
LMK04828B	Texas Instruments	—
LMK04828B/26B	Texas Instruments	—
LMK04828BISQ/NOPB	Texas Instruments	64-Pin QFN
LMK04828BISQE/NOPB	Texas Instruments	—
LMK04828BISQX	Texas Instruments	—
LMK04828BISQX/NOPB	Texas Instruments	—

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