KSZ8081MLXCA
Physical Layer TransceiverThe KSZ8081MLXCA is a physical layer transceiver from Microchip Technology. View the full KSZ8081MLXCA datasheet below including key specifications, electrical characteristics, absolute maximum ratings.
Key Specifications
| Parameter | Value |
|---|---|
| Data Rate | 100Mbps |
| Duplex | Full |
| Mounting Type | Surface Mount |
| Number of Drivers/Receivers | 1/1 |
| Operating Temperature | 0°C ~ 70°C |
| Package / Case | 48-LQFP |
| Protocol | Ethernet |
| Supplier Device Package | 48-LQFP (7x7) |
| Supplier Device Package | 48-LQFP (7x7) |
| Supplier Device Package | 48-LQFP (7x7) |
| Supplier Device Package | 48-LQFP (7x7) |
| Supplier Device Package | 48-LQFP (7x7) |
| Supplier Device Package | 48-LQFP (7x7) |
| Supplier Device Package | 48-LQFP (7x7) |
| Type | Transceiver |
| Type | Transceiver |
| Type | Transceiver |
| Type | Transceiver |
| Type | Transceiver |
| Type | Transceiver |
| Type | Transceiver |
| Supply Voltage | 3.3V |
Overview
Part: KSZ8081MLX — Microchip Type: 10BASE-T/100BASE-TX Ethernet Physical Layer Transceiver Description: A single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for data transmission and reception over standard CAT-5 UTP cable, featuring MII interface, on-chip termination resistors, and 1.8V/2.5V/3.3V digital I/O support.
Operating Conditions:
- Supply voltage: 3.3V (single supply)
- I/O voltage options: 1.8V, 2.5V, 3.3V
- Core voltage: 1.2V (supplied by integrated regulator)
- Crystal/Oscillator/External Clock Input: 25 MHz ±50 ppm
Absolute Maximum Ratings:
- Max HBM ESD Rating: 6 kV
Key Specs:
- Ethernet Compliance: IEEE 802.3 10BASE-T/100BASE-TX
- Interface: MII
- Cable Diagnostics: LinkMD TDR-based
- Auto MDI/MDI-X: HP Auto MDI/MDI-X with disable/enable
- Auto-Negotiation: 10/100 Mbps speed and Half/Full duplex
- Management Interface: MDC/MDIO
- PHY Address: Configurable 0 to 7 (default 00001)
- REXT Resistor: 6.49 kΩ to ground
Features:
- Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
- MII Interface Support
- Back-to-Back Mode Support for a 100 Mbps Copper Repeater
- MDC/MDIO Management Interface for PHY Register Configuration
- Programmable Interrupt Output
- LED Outputs for Link and Activity Status Indication
- On-Chip Termination Resistors for the Differential Pairs
- Baseline Wander Correction
- HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
- Power-Down and Power-Saving Modes
- LinkMD TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
- Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
- Loopback Modes for Diagnostics
- Single 3.3V Power Supply with VDD I/O Options for 1.8V, 2.5V, or 3.3V
- Built-In 1.2V Regulator for Core
Applications:
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Package:
- 48-pin 7 mm x 7 mm LQFP
Features
- Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
- MII Interface Support
- Back-to-Back Mode Support for a 100 Mbps Copper Repeater
- MDC/MDIO Management Interface for PHY Register Configuration
- Programmable Interrupt Output
- LED Outputs for Link and Activity Status Indication
- On-Chip Termination Resistors for the Differential Pairs
- Baseline Wander Correction
- HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
- Power-Down and Power-Saving Modes
- LinkMD ® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
- Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
- HBM ESD Rating (6 kV)
- Loopback Modes for Diagnostics
- Single 3.3V Power Supply with V DD I/O Options for 1.8V, 2.5V, or 3.3V
- Built-In 1.2V Regulator for Core
- Available in 48-pin 7 mm x 7 mm LQFP Package
Applications
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Pin Configuration
FIGURE 2-1: 48-PIN 7 MM X 7 MM LQFP ASSIGNMENT (TOP VIEW)
TABLE 2-1: SIGNALS - KSZ8081MLX
| Pin Number | Pin Name | Type Note 2-1 | Description |
|---|---|---|---|
| 1 | GND | GND | Ground. |
| 2 | GND | GND | Ground. |
| 3 | GND | GND | Ground. |
| 4 | VDD_!.2 | P | 1.2V Core V DD (power supplied by KSZ8081MLX). Decouple with 2.2 μF and 0.1 μF capacitors to ground, and join with Pin 31 by power trace or plane. |
| 5 | NC | - | No Connect. This pin is not bonded and can be left floating. |
| 6 | NC | - | No Connect. This pin is not bonded and can be left floating. |
| 7 | VDDA_3.3 | P | 3.3V Analog V DD . |
| 8 | NC | - | No Connect. This pin is not bonded and can be left floating. |
| 9 | RXM | I/O | Physical Receive or Transmit Signal (- differential). |
| 10 | RXP | I/O | Physical Receive or Transmit Signal (+ differential). |
| 11 | TXM | I/O | Physical Transmit or Receive Signal (- differential). |
| 12 | TXP | I/O | Physical Transmit or Receive Signal (+ differential). |
| 13 | GND | GND | Ground. |
| 14 | XO | O | Crystal Feedback for 25 MHz Crystal. This pin is a no connect if an oscillator or external clock source is used. |
| 15 | XI | I | Crystal/Oscillator/External Clock Input (25 MHz ±50 ppm). |
| 16 | REXT | I | Set PHY Transmit Output Current. Connect a 6.49 k Ω resistor to ground on this pin. |
| 17 | GND | GND | Ground. |
| 18 | MDIO | Ipu/ Opu | Management Interface (MII) Data I/O. This pin has a weak pull-up, is open- drain, and requires an external 1.0 k Ω pull-up resistor. |
| 19 | MDC | Ipu | Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO data pin. |
| 20 | RXD3/ PHYAD0 | Ipu/O | MII Mode: MII Receive Data Output[3] (Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details. |
| 21 | RXD2/ PHYAD1 | Ipd/O | MII Mode: MII Receive Data Output[2] (Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details. |
| 22 | RXD1/ PHYAD2 | Ipd/O | MII Mode: MII Receive Data Output[1] (Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details. |
TABLE 2-1: SIGNALS - KSZ8081MLX (CONTINUED)
| Pin Number | Pin Name | Type Note 2-1 | Description |
|---|---|---|---|
| 23 | RXD0/ DUPLEX | Ipu/O | MII Mode: MII Receive Data Output[0] (Note 2-2) Config. Mode: The pull-up/pull-down value is latched as DUPLEX at the de- assertion of reset. See the Strap-In Options - KSZ8081MLX section for details. |
| 24 | GND | GND | Ground. |
| 25 | VDDIO | P | 3.3V, 2.5V, or 1.8V Digital V DD . |
| 26 | NC | - | No Connect. This pin is not bonded and can be left floating. |
| 27 | RXDV/ CONFIG2 | Ipd/O | MII Mode: MII Receive Data Valid Output. Config. Mode: The pull-up/pull-down value is latched as CONFIG2 at the de- assertion of reset. See the Strap-In Options - KSZ8081MLX section for details. |
| 28 | RXC/ B-CAST_OFF | Ipd/O | MII Mode: MII Receive Clock Output. Config. Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details. |
| 29 | RXER/ ISO | Ipd/O | MII Mode: MII Receive Error output Config. Mode: The pull-up/pull-down value is latched as ISOLATE at thede- assertion of reset See the Strap-In Options - KSZ8081MLX section for details. |
| 30 | GND | GND | Ground. |
| 31 | VDD_1.2 | P | 1.2V Core V DD (power supplied by KSZ8081MLX). Decouple with 0.1 μF capacitor to ground, and join with Pin 4 by power trace or plane. |
| 32 | INTRP/ NAND_Tree# | Ipu/ Opu | Interrupt Output: Programmable interrupt output. This pin has a weak pull-up, is open drain, and requires an external 1.0 k Ω pull-up resistor. Config. Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details. |
| 33 | TXC | Ipd/O | MII Mode: MII Transmit Clock Output. At the de-assertion of reset, this pin needs to latch in a pull-down value for normal operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solu- tion. It is better having an external pull-down resistor to avoid MAC side pulls this pin high. |
| 34 | TXEN | I | MII Mode: MII Transmit Enable input. |
| 35 | TXD0 | I | MII Mode: MII Transmit Data Input[0] (Note 2-3) |
| 36 | TXD1 | I | MII Mode: MII Transmit Data Input[1] (Note 2-3) |
| 37 | GND | GND | Ground. |
| 38 | TXD2 | I | MII Mode: MII Transmit Data Input[2] (Note 2-3) |
| 39 | TXD3 | I | MII Mode: MII Transmit Data Input[3] (Note 2-3) |
Electrical Characteristics
T A = 25°C. Specification is for packaged product only.
TABLE 6-1: ELECTRICAL CHARACTERISTICS
| Parameters | Symbol | Min. | Typ. | Max. | Units | Note |
|---|---|---|---|---|---|---|
| Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 |
| 10BASE-T | I DD1_3.3V | - | 41 | - | mA | Full-duplex traffic @100% utilization |
| 100BASE-TX | I DD2_3.3V | - | 47 | - | mA | Full-duplex traffic @100% utilization |
| EDPD Mode | I DD3_3.3V | - | 20 | - | mA | Ethernet cable disconnected (Reg. 18h.11 = 0) |
| Power-Down Mode | I DD4_3.3V | - | 4 | - | mA | Software power-down (Reg. 0h.11 = 1) |
| CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs |
| Input High Voltage | V IH | 2.0 | - | - | V | V DDIO = 3.3V |
| Input High Voltage | V IH | 1.8 | - | - | V | V DDIO = 2.5V |
| Input High Voltage | V IH | 1.3 | - | - | V | V DDIO = 1.8V |
| Input Low Voltage | V IL | - | - | 0.8 | V | V DDIO = 3.3V |
| Input Low Voltage | V IL | - | - | 0.7 | V | V DDIO = 2.5V |
| Input Low Voltage | V IL | - | - | 0.5 | V | V DDIO = 1.8V |
| Input Current | \ | I IN \ | - | - | 10 | |
| CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs |
| Output High Voltage | V OH | 2.4 | - | - | V DDIO = 3.3V | |
| Output High Voltage | V OH | 2.0 | - | - | V | V DDIO = 2.5V |
| Output High Voltage | V OH | 1.5 | - | - | V DDIO = 1.8V | |
| Output Low Voltage | V OL | - | - | 0.4 | V | V DDIO = 3.3V |
| Output Low Voltage | V OL | - | - | 0.4 | V | V DDIO = 2.5V |
| Output Low Voltage | V OL | - | - | 0.3 | V | V DDIO = 1.8V |
| Output Tri-State Leakage | \ | I OZ \ | - | - | 10 | |
| LED Output | LED Output | LED Output | LED Output | LED Output | LED Output | LED Output |
| Output Drive Current | I LED | - | 8 | - | mA | Each LED pin (LED0, LED1) |
| All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) |
| Internal Pull-Up Resistance | pu | 30 | 45 | 73 | k Ω | V DDIO = 3.3V |
| Internal Pull-Up Resistance | pu | 39 | 61 | 102 | k Ω | V DDIO = 2.5V |
| Internal Pull-Up Resistance | pu | 48 | 99 | 178 | k Ω | V DDIO = 1.8V |
| Internal Pull-Down Resistance | pd | 26 | 43 | 79 | k Ω | V DDIO = 3.3V |
| Internal Pull-Down Resistance | pd | 34 | 59 | 113 | k Ω | V DDIO = 2.5V |
| Internal Pull-Down Resistance | pd | 53 | 99 | 200 | k Ω | V DDIO = 1.8V |
| 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) |
| Peak Differential Output Voltage | V O | 0.95 | - | 1.05 | V | 100 Ω termination across differential output |
| Output Voltage Imbalance | V IMB | - | - | 2 | % | 100 Ω termination across differential output |
| Rise/Fall Time | t r /t f | 3 | - | 5 | ns | - |
| Rise/Fall Time Imbalance | - | 0 | - | 0.5 | ns | - |
| Duty Cycle Distortion | - | - | - | ±0.25 | ns | - |
| Overshoot | - | - | - | 5 | % | - |
| Output Jitter | - | - | 0.7 | - | ns | Peak-to-peak |
TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
| Parameters | Symbol | Min. | Typ. | Max. | Units | Note |
|---|---|---|---|---|---|---|
| 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) |
| Peak Differential Output Voltage | V P | 2.2 | - | 2.8 | V | 100 Ω termination across differential output |
| Jitter Added | - | - | - | 3.5 | ns | Peak-to-peak |
| Rise/Fall Time | t r /t f | - | 25 | - | ns | - |
| 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive |
| Squelch Threshold | V SQ | - | 400 | - | mV | 5 MHz square wave |
| Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting |
| Reference Voltage of I SET | V SET | - | 0.65 | - | V | R(I SET ) = 6.49 k Ω |
| 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters |
| Clock Phase Delay - XI Input to MII TXC Output | - | 15 | 20 | 25 | ns | XI (25 MHz clock input) to MII TXC (25 MHz clock output) delay, refer- enced to rising edges of both clocks. |
| Link Loss Reaction (Indication) Time | t llr | - | 4.4 | - | μs | Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 2. INTRP pin asserts for link-down status change. |
Note 6-1 Current consumption is for the single 3.3V supply KSZ8081MLX device only, and includes the transmit driver current and the 1.2V supply voltage (V DD_1.2 ) that are supplied by the KSZ8081MLX.
Absolute Maximum Ratings
Supply Voltage (V IN )
(V DD_1.2
).................................................................................................................................................... -0.5V to +1.8V
, V
(V DDIO
DDA_3.3 ) ...................................................................................................................................... -0.5V to +5.0V
Input Voltage (all inputs) ........................................................................................................................... -0.5V to +5.0V
Output Voltage (all outputs) ...................................................................................................................... -0.5V to +5.0V
Lead Temperature (soldering, 10s) ....................................................................................................................... +260°C
Storage Temperature (T S )...................................................................................................................... -55°C to +150°C
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| KSZ8081 | Microchip Technology | — |
| KSZ8081MLX | Microchip Technology | 48-pin 7 mm x 7 mm LQFP |
| KSZ8081MLXCA-TR | Microchip Technology | — |
| KSZ8081MLXIA | Microchip Technology | 48-pin 7 mm x 7 mm LQFP |
| KSZ8081MLXIA-TR | Microchip Technology | — |
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.
Get structured datasheet data via API
Get started free