KSZ8081MLX
KSZ8081MLX
Physical Layer TransceiverThe KSZ8081MLX is a physical layer transceiver from Microchip Technology. View the full KSZ8081MLX datasheet below including key specifications, pinout, electrical characteristics, absolute maximum ratings.
Manufacturer
Microchip Technology
Category
Physical Layer Transceiver
Package
48-pin LQFP
Key Specifications
| Parameter | Value |
|---|---|
| Data Rates | 10 Mbps, 100 Mbps |
| ESD Rating (HBM) | 6 kV |
| MDIO Clock Speed | up to 10 MHz |
| Ethernet Standard | 10BASE-T/100BASE-TX IEEE 802.3 |
| Package Dimensions | 7 mm x 7 mm (for 48-pin LQFP) |
| Core Supply Voltage | 1.2V (internal regulator) |
| Main Supply Voltage | 3.3V |
| Communication Interfaces | MII, MDC/MDIO |
| Reference Clock Frequency | 25 MHz |
| I/O Supply Voltage Options | 1.8V, 2.5V, 3.3V |
Overview
Part: KSZ8081MLX, Microchip
Type: 10BASE-T/100BASE-TX Physical Layer Transceiver
Key Specs:
- HBM ESD Rating: 6 kV
- Single Power Supply: 3.3V
- VDD I/O Options: 1.8V, 2.5V, 3.3V
- Built-In Core Regulator: 1.2V
- Crystal/Oscillator/External Clock Input: 25 MHz ±50 ppm
- REXT Resistor: 6.49 kΩ
- MDIO Pull-up Resistor: 1.0 kΩ
Features:
- Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
- MII Interface Support
- Back-to-Back Mode Support for a 100 Mbps Copper Repeater
- MDC/MDIO Management Interface for PHY Register Configuration
- Programmable Interrupt Output
- LED Outputs for Link and Activity Status Indication
- On-Chip Termination Resistors for the Differential Pairs
- Baseline Wander Correction
- HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
- Power-Down and Power-Saving Modes
- LinkMD® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
- Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
- Loopback Modes for Diagnostics
Applications:
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Package:
- LQFP: 48-pin 7 mm x 7 mm
Features
- Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
- MII Interface Support
- Back-to-Back Mode Support for a 100 Mbps Copper Repeater
- MDC/MDIO Management Interface for PHY Register Configuration
- Programmable Interrupt Output
- LED Outputs for Link and Activity Status Indication
- On-Chip Termination Resistors for the Differential Pairs
- Baseline Wander Correction
- HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
- Power-Down and Power-Saving Modes
- LinkMD® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
- Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
- HBM ESD Rating (6 kV)
- Loopback Modes for Diagnostics
- Single 3.3V Power Supply with VDD I/O Options for 1.8V, 2.5V, or 3.3V
- Built-In 1.2V Regulator for Core
- Available in 48-pin 7 mm x 7 mm LQFP Package
Applications
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Pin Configuration
KSZ8081MLX — 48-pin 7 mm × 7 mm LQFP
| Pin | Name | Type | Description |
|---|---|---|---|
| 1 | GND | GND | Ground |
| 2 | GND | GND | Ground |
| 3 | GND | GND | Ground |
| 4 | VDD_1.2 | P | 1.2V Core VDD. Decouple with 2.2 μF and 0.1 μF capacitors to ground; join with Pin 31 by power trace or plane. |
| 5 | NC | — | No Connect |
| 6 | NC | — | No Connect |
| 7 | VDDA_3.3 | P | 3.3V Analog VDD |
| 8 | NC | — | No Connect |
| 9 | RXM | I/O | Physical Receive or Transmit Signal (– differential) |
| 10 | RXP | I/O | Physical Receive or Transmit Signal (+ differential) |
| 11 | TXM | I/O | Physical Transmit or Receive Signal (– differential) |
| 12 | TXP | I/O | Physical Transmit or Receive Signal (+ differential) |
| 13 | GND | GND | Ground |
| 14 | XO | O | Crystal Feedback for 25 MHz Crystal. No connect if oscillator or external clock source is used. |
| 15 | XI | I | Crystal/Oscillator/External Clock Input (25 MHz ±50 ppm) |
| 16 | REXT | I | Set PHY Transmit Output Current. Connect 6.49 kΩ resistor to ground. |
| 17 | GND | GND | Ground |
| 18 | MDIO | Ipu/Opu | Management Interface (MII) Data I/O. Open-drain with weak pull-up; requires external 1.0 kΩ pull-up resistor. |
| 19 | MDC | Ipu | Management Interface (MII) Clock Input |
| 20 | RXD3/PHYAD0 | Ipu/O | MII Mode: MII Receive Data Output[3]. Config Mode: Pull-up/pull-down latched as PHYADDR[0] at reset de-assertion. |
| 21 | RXD2/PHYAD1 | Ipd/O | MII Mode: MII Receive Data Output[2]. Config Mode: Pull-up/pull-down latched as PHYADDR[1] at reset de-assertion. |
| 22 | RXD1/PHYAD2 | Ipd/O | MII Mode: MII Receive Data Output[1]. Config Mode: Pull-up/pull-down latched as PHYADDR[2] at reset de-assertion. |
| 23 | RXD0/DUPLEX | Ipd/O | MII Mode: MII Receive Data Output[0]. Config Mode: DUPLEX mode configuration. |
| 24 | GND | GND | Ground |
| 25 | VDDIO | P | I/O Supply Voltage |
| 26 | NC | — | No Connect |
| 27 | RXDV/CONFIG2 | Ipd/O | MII Mode: Receive Data Valid. Config Mode: Configuration pin. |
| 28 | RXC/B-CAST_OFF | Ipd/O | MII Mode: Receive Clock. Config Mode: Broadcast OFF configuration. |
| 29 | RXER/ISO | Ipd/O | MII Mode: Receive Error. Config Mode: Isolation mode configuration. |
| 30 | GND | GND | Ground |
| 31 | VDD_1.2 | P | 1.2V Core VDD. Join with Pin 4 by power trace or plane. |
| 32 | INTRP/NAND_TREE# | O/Ipd | Interrupt Output or NAND Tree configuration input |
| 33 | TXC | O | Transmit Clock |
| 34 | TXEN | O | Transmit Enable |
| 35 | TXD0 | O | MII Transmit Data Output[0] |
| 36 | TXD1 | O | MII Transmit Data Output[1] |
| 37 | GND | GND | Ground |
| 38 | TXD2 | O | MII Transmit Data Output[2] |
| 39 | TXD3 | O | MII Transmit Data Output[3] |
| 40 | COL/CONFIG0 | Ipd/O | MII Mode: Collision Detect. Config Mode: Configuration pin. |
| 41 | CRS/CONFIG1 | Ipd/O | MII Mode: Carrier Sense. Config Mode: Configuration pin. |
| 42 | LED0/NWAYEN | O/Ipd | LED0 Output or NWAY Enable configuration |
| 43 | LED1/SPEED | O/Ipd | LED1 Output or SPEED configuration |
| 44 | NC | — | No Connect |
| 45 | NC | — | No Connect |
| 46 | NC | — | No Connect |
| 47 | RST# | I | Active-Low Reset Input |
| 48 | NC | — | No Connect |
Notes
- Pin numbering: Verified against the 48-pin LQFP package diagram (top view).
- Dual-function pins: Pins 20–23, 27–29, 32, 40–43 have dual functions depending on mode (MII operation vs. configuration/strapping during reset).
- Pull-up/pull-down: Ipu = internal pull-up; Ipd = internal pull-down; Ipu/O = pull-up during power-up/reset, output otherwise; Ipd/O = pull-down during power-up/reset, output otherwise.
- Power distribution: VDD_1.2 (Pins 4 and 31) must be joined by power trace or plane and decoupled with 2.2 μF and 0.1 μF capacitors.
- MDIO: Open-drain output; requires external 1.0 kΩ pull-up resistor.
- REXT: 6.49 kΩ resistor to ground required to set transmit output current.
- No Connect pins (5, 6, 8, 26, 44, 45, 46, 48) are not bonded and can be left floating.
Electrical Characteristics
TA = 25°C. Specification is for packaged product only.
Absolute Maximum Ratings
- (VDD_1.2) –0.5V to +1.8V
- (VDDIO, VDDA_3.3) –0.5V to +5.0V
- Input Voltage (all inputs) –0.5V to +5.0V
- Output Voltage (all outputs) –0.5V to +5.0V
- Lead Temperature (soldering, 10s) +260°C
- Storage Temperature (TS) –55°C to +150°C
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Package Information
Ordering Information
| MPN | Package | Temperature Range | Packing |
|---|---|---|---|
| KSZ8081MLX | 48-pin LQFP | - | - |
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