KSZ8081MLXIA

Physical Layer Transceiver

The KSZ8081MLXIA is a physical layer transceiver from Microchip Technology. View the full KSZ8081MLXIA datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

Microchip Technology

Overview

Part: KSZ8081MLX from Microchip

Type: 10BASE-T/100BASE-TX Physical Layer Transceiver

Description: A single-chip 10BASE-T/100BASE-TX IEEE 802.3 compliant Ethernet transceiver with MII interface, supporting a single 3.3V supply, 1.8V/2.5V/3.3V I/O options, and integrated 1.2V core regulator.

Operating Conditions:

Supply voltage: 3.3V (main supply), 1.8V, 2.5V, or 3.3V (VDD I/O options)
Operating temperature: null
Clock input: 25 MHz ±50 ppm

Absolute Maximum Ratings:

Max supply voltage: null
Max continuous current: null
Max junction/storage temperature: null

Key Specs:

Ethernet Standards: 10BASE-T/100BASE-TX IEEE 802.3 Compliant
Interface: MII, MDC/MDIO
Core Voltage: 1.2V (built-in regulator)
I/O Voltage Options: 1.8V, 2.5V, 3.3V
Clock Input: 25 MHz ±50 ppm
ESD Rating: HBM 6 kV
Cable Diagnostics: LinkMD® TDR-Based
External Resistor: 6.49 kΩ for PHY Transmit Output Current

Features:

Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
MII Interface Support
Back-to-Back Mode Support for a 100 Mbps Copper Repeater
MDC/MDIO Management Interface for PHY Register Configuration
Programmable Interrupt Output
LED Outputs for Link and Activity Status Indication
On-Chip Termination Resistors for the Differential Pairs
Baseline Wander Correction
HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
Power-Down and Power-Saving Modes
LinkMD® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
HBM ESD Rating (6 kV)
Loopback Modes for Diagnostics
Single 3.3V Power Supply with VDD I/O Options for 1.8V, 2.5V, or 3.3V
Built-In 1.2V Regulator for Core

Applications:

Game Consoles
IP Phones
IP Set-Top Boxes
IP TVs
LOM
Printers

Package:

48-pin 7 mm x 7 mm LQFP

Features

Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
MII Interface Support
Back-to-Back Mode Support for a 100 Mbps Copper Repeater
MDC/MDIO Management Interface for PHY Register Configuration
Programmable Interrupt Output
LED Outputs for Link and Activity Status Indication
On-Chip Termination Resistors for the Differential Pairs
Baseline Wander Correction
HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
Power-Down and Power-Saving Modes
LinkMD® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
HBM ESD Rating (6 kV)
Loopback Modes for Diagnostics
Single 3.3V Power Supply with VDD I/O Options for 1.8V, 2.5V, or 3.3V
Built-In 1.2V Regulator for Core
Available in 48-pin 7 mm x 7 mm LQFP Package

Applications

Game Consoles
IP Phones
IP Set-Top Boxes
IP TVs
LOM
Printers

Pin Configuration

FIGURE 2-1: 48-PIN 7 MM X 7 MM LQFP ASSIGNMENT (TOP VIEW)

TABLE 2-1: SIGNALS - KSZ8081MLX

Pin Number	Pin Name	Type Note 2-1	Description
1	GND	GND	Ground.
2	GND	GND	Ground.
3	GND	GND	Ground.
4	VDD_1.2	P	1.2V Core VDD (power supplied by KSZ8081MLX). Decouple with 2.2 μF and 0.1 μF capacitors to ground, and join with Pin 31 by power trace or plane.
5	NC	—	No Connect. This pin is not bonded and can be left floating.
6	NC	—	No Connect. This pin is not bonded and can be left floating.
7	VDDA_3.3	P	3.3V Analog VDD.
8	NC	—	No Connect. This pin is not bonded and can be left floating.
9	RXM	I/O	Physical Receive or Transmit Signal (– differential).
10	RXP	I/O	Physical Receive or Transmit Signal (+ differential).
11	TXM	I/O	Physical Transmit or Receive Signal (– differential).
12	TXP	I/O	Physical Transmit or Receive Signal (+ differential).
13	GND	GND	Ground.
14	XO	O	Crystal Feedback for 25 MHz Crystal. This pin is a no connect if an oscillator or
14	XO	O	external clock source is used.
15	XI	I	Crystal/Oscillator/External Clock Input (25 MHz ±50 ppm).
16	REXT	I	Set PHY Transmit Output Current. Connect a 6.49 kΩ resistor to ground on this pin.
17	GND	GND	Ground.
18	MDIO	Ipu/ Opu	Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ pull-up resistor.
19	MDC	Ipu	Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO data pin.
20	RXD3/ PHYAD0	Ipu/O	MII Mode: MII Receive Data Output[3] (Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details.
21	RXD2/ PHYAD1	Ipd/O	MII Mode: MII Receive Data Output[2] (Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details.
22	RXD1/ PHYAD2	Ipd/O	MII Mode: MII Receive Data Output[1] (Note 2-2) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-assertion of reset. See the Strap-In Options - KSZ8081MLX section for details.

Pin Number	Pin Name
1	GND
2	GND
3	GND
4	VDD_1.2
5	NC
6	NC
7	VDDA_3.3
8	NC
9	RXM
10	RXP
11	TXM
12	TXP
13	GND
14	XO
15	XI
16	REXT
17	GND
18	MDIO
19	MDC
20	RXD3 / PHYAD0
21	RXD2 / PHYAD1
22	RXD1 / PHYAD2
23	RXD0 / DUPLEX
24	GND
25	VDDIO
26	NC
27	RXDV / CONFIG2
28	RXC / B-CAST_OFF
29	RXER / ISO
30	GND
31	VDD_1.2
32	INTRP / NAND_TREE#
33	TXC
34	TXEN
35	TXD0
36	TXD1
37	GND
38	TXD2
39	TXD3
40	COL / CONFIG0
41	CRS / CONFIG1
42	LED0 / NWAYEN
43	LED1 / SPEED
44	NC
45	NC
46	NC
47	RST#
48	NC

Pin Number	Pin Name
40	COL/CONFIG0
41	CRS/CONFIG1
42	LED0/NWAYEN
43	LED1/SPEED

Pin Number	Pin Name
44	NC
45	NC
46	NC
47	RST#
48	NC

Note 2-1 P = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Ipu = Input with internal pull-up (see Electrical Characteristics for value).

Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.

Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value).

Note 2-2 MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC.

Note 2-3 MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC.

Electrical Characteristics

T_A = 25°C. Specification is for packaged product only.

TABLE 6-1: ELECTRICAL CHARACTERISTICS

Parameters	Symbol	Min.	Typ.	Max.	Units	Note
Supply Current (V _DDIO , V _DI		). Note 6
10BASE-T	I _{DD1_3.3} V	_	41	_	mA	Full-duplex traffic @ 100% utilization
100BASE-TX	I _{DD2_3.3V}	_	47	_	mA	Full-duplex traffic @ 100% utilization
EDPD Mode	I _{DD3_3.3V}	_	20	_	mA	Ethernet cable disconnected (Reg. 18h.11 = 0)
Power-Down Mode	I _{DD4_3.3V}	ı	4	_	mA	Software power-down (Reg. 0h.11 = 1)
CMOS Level Inputs		2.0		_		V_DDIO = 3.3V
Input High Voltage	V_IH	1.8	_	_	V	V _DDIO = 2.5V
		1.3	_	_		V _DDIO = 1.8V
		_	_	0.8		V _DDIO = 3.3V
Input Low Voltage	V_IL	_	_	0.7	V	V _DDIO = 2.5V
		_	_	0.5		V _DDIO = 1.8V
Input Current	I _IN	_	_	10	μA	V _IN = GND ~ V _DDIO
CMOS Level Outputs
		2.4	_	_		V _DDIO = 3.3V
Output High Voltage	V_OH	2.0	_	_	V	V _DDIO = 2.5V
		1.5	_	_		V _DDIO = 1.8V
		_	_	0.4		V _DDIO = 3.3V
Output Low Voltage	V_OL	_	_	0.4	V	V _DDIO = 2.5V
		_	_	0.3		V _DDIO = 1.8V
Output Tri-State Leakage	I _OZ	_	_	10	μΑ	_
LED Output
Output Drive Current	I _LED	_	8	_	mA	Each LED pin (LED0, LED1)
All Pull-Up/Pull-Down Pins		Strappin	g Pins)	•	•
		30	45	73	kΩ	V _DDIO = 3.3V
Internal Pull-Up Resistance	pu	39	61	102	kΩ	V _DDIO = 2.5V
		48	99	178	kΩ	V _DDIO = 1.8V
		26	43	79	kΩ	V _DDIO = 3.3V
Internal Pull-Down Resistance	pd	34	59	113	kΩ	V _DDIO = 2.5V
Nesistance		53	99	200	kΩ	V _DDIO = 1.8V
100BASE-TX Transmit (me	asured diffe	rentially	after 1:1	transfo	rmer)
Peak Differential Output Voltage	V _O	0.95	_	1.05	V	100Ω termination across differential output
Output Voltage Imbalance	V_IMB	_	_	2	%	100Ω termination across differential output
Rise/Fall Time	t _r /t _f	3		5	ns
Rise/Fall Time Imbalance		0	_	0.5	ns	_
Duty Cycle Distortion		_	_	±0.25	ns	_
Overshoot	_	_	_	5	%	_
Output Jitter	_	_	0.7	_	ns	Peak-to-peak

TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED)

Parameters	Symbol	Min.	Typ.	Max.	Units	Note
10BASE-T Transmit (meas	ured differe	ntially af	ter 1:1 tr	ansform	er)
Peak Differential Output Voltage	V _P	2.2	_	2.8	V	100Ω termination across differential output
Jitter Added	_	_	_	3.5	ns	Peak-to-peak
Rise/Fall Time	t _r /t _f	_	25	_	ns	_
10BASE-T Receive
Squelch Threshold	V_SQ	_	400	_	mV	5 MHz square wave
Transmitter - Drive Setting
Reference Voltage of I _SET	V _SET	_	0.65	_	V	R(I_SET) = 6.49 kΩ
100 Mbps Mode - Industria	I Applicatio	ns Paran	neters
Clock Phase Delay – XI Input to MII TXC Output	_	15	20	25	ns	XI (25 MHz clock input) to MII TXC (25 MHz clock output) delay, referenced to rising edges of both clocks.
Link Loss Reaction (Indication) Time	t _llr	_	4.4	_	μs	Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 2. INTRP pin asserts for link-down status change.

Note 6-1 Current consumption is for the single 3.3V supply KSZ8081MLX device only, and includes the transmit driver current and the 1.2V supply voltage (V_DD₁.2) that are supplied by the KSZ8081MLX.

Absolute Maximum Ratings

(VDDIO, VDDA_3.3) –0.5V to +5.0V
Input Voltage (all inputs) –0.5V to +5.0V
Output Voltage (all outputs) –0.5V to +5.0V
Lead Temperature (soldering, 10s) +260°C
Storage Temperature (TS) –55°C to +150°C

^*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
KSZ8081	Microchip Technology	—
KSZ8081MLX	Microchip Technology	48-pin 7 mm x 7 mm LQFP
KSZ8081MLXCA	Microchip Technology	48-LQFP
KSZ8081MLXCA-TR	Microchip Technology	—
KSZ8081MLXIA-TR	Microchip Technology	—

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