ICE40LP1K

Part: iCE40 LP/HX Family — Lattice Semiconductor

Type: FPGA (Field-Programmable Gate Array)

Description: The iCE40 LP/HX family is a series of ultra-low power and high-performance FPGAs featuring programmable logic, embedded block RAM, PLLs, and flexible I/O, designed for various applications.

Operating Conditions:

• Core supply voltage (VCC): 1.14–1.26 V
• I/O driver supply voltage (VCCIO): 1.71–3.46 V
• Operating temperature: -40 to 100 °C (Industrial Operation)

Absolute Maximum Ratings:

• Max core supply voltage (VCC): 1.42 V
• Max I/O supply voltage (VCCIO): 3.6 V
• Max storage temperature: 150 °C
• Max junction temperature: 125 °C

Key Specs:

• Core Supply Voltage (VCC): 1.14–1.26 V
• I/O Driver Supply Voltage (VCCIO): 1.71–3.46 V
• PLL Supply Voltage (VCCPLL): 1.14–1.26 V
• NVCM Programming and Operating Supply Voltage (VPP_2V5): 1.71–3.46 V (Slave SPI Config)
• Input High Voltage (VIH) for LVCMOS33: 2.3 V (min)
• Input Low Voltage (VIL) for LVCMOS33: 0.8 V (max)
• Output High Voltage (VOH) for LVCMOS33: 2.4 V (min) at IOH = -4 mA
• Output Low Voltage (VOL) for LVCMOS33: 0.4 V (max) at IOL = 4 mA

Features:

• Programmable Logic Blocks (PLB)
• sysCLOCK Phase Locked Loops (PLLs)
• sysMEM Embedded Block RAM Memory
• sysI/O with various standards support
• Non-Volatile Configuration Memory (NVCM)
• Power On Reset (POR)
• Power Saving Options

Applications:

Package:

• Flexible Logic Architecture
• Five devices with 384 to 7,680 LUT4s and 10 to 206 I/O
• Ultra-low Power Devices
• Advanced 40 nm low power process
• As low as 21 μA standby power
• Programmable low swing differential I/O
• Embedded and Distributed Memory
• Up to 128 kb sysMEM™ Embedded Block RAM
• Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• High Current LED Drivers
• Three High Current Drivers used for three different LEDs or one RGB LED
• High Performance, Flexible I/O Buffer
• Programmable sysI/O™ buffer supports wide range of interfaces:
• LVCMOS 3.3/2.5/1.8
• LVDS25E, subLVDS
• Schmitt trigger inputs, to 200 mV typical hysteresis
• Programmable pull-up mode
• Flexible On-Chip Clocking
• Eight low skew global signal resources
• Up to two analog PLLs per device
• Flexible Device Configuration
• SRAM is configured through:
• Standard SPI Interface
• Internal Nonvolatile Configuration Memory (NVCM)
• Broad Range of Package Options
• WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options
• Small footprint package options
• As small as 1.40 mm x 1.48 mm
• Advanced halogen-free packaging

Over recommended operating conditions.

Table 4.5. DC Electrical Characteristics

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled.
2. TJ 25 o C, f = 1.0 MHz.
3. Refer to V IL and VIH in the sysI/O Single-Ended DC Electrical Characteristics table.
4. Only applies to I/O in the SPI bank following configuration.
5. Some products are clamped to a diode when VIN is larger than VCCIO.
6. High current I/O has three sysI/O buffers connected together.
7. The iCE40LP640 and iCE40LP1K SWG16 package has CDONE and a sysI/O buffer are connected together.

• Stress above those listed under the 'Absolute Maximum Ratings' may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
• Compliance with the Thermal Management (FPGA-TN-02044) document is required.
• All voltages referenced to GND.
• I/O can support a 200 mV Overshoot above the Recommended Operating Conditions VCCIO (Max) and -200 mV Undershoot below VIL (Min). Overshoot and Undershoot is permitted for 25% duty cycle but must not exceed 1.6 ns.

1. Like power supplies must be tied together. For example, if VCCIO and VCC_SPI are both the same voltage, they must also be the same supply.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. VPP_FAST, used only for fast production programming, must be left floating or unconnected in applications.
5. For CM36 and CM49 packages, if a user is not using the NVCM fast programming function, the VPP_FAST pin must be connected to the VCCIO_0_1 pin. Failing to do so will cause the I/O bank 1 from functioning properly.
6. No PLL available on the iCE40LP384 and iCE40LP640 device.
7. VCCPLL is tied to VCC internally in packages without PLL pins.