ICE40

Part: iCE40 UltraPlus Family — Lattice Semiconductor

Type: FPGA

Description: Ultra-low power FPGAs with up to 5.3K LUTs, 1 Mb SPRAM, 120 Kb EBR, 8 DSP blocks, integrated I2C/SPI IP, and high current RGB LED drivers, offering up to 125 MHz performance.

Operating Conditions:

• Supply voltage: Core VCC: 1.14–1.26 V; I/O VCCIO: 1.14–3.465 V
• Operating temperature: -40 to +100 °C (Junction)
• Max register-to-register performance:

• Flexible Logic Architecture
• Two devices with 2800 to 5280 LUTs
• Offered in WLCS and QFN packages
• Ultra-low Power Devices
• Advanced 40 nm low power process

As low as 100 μA standby current typical

• Embedded Memory
• Up to 1024 kb Single Port SRAM
• Up to 120 kb sysMEM™ Embedded Block RAM
• Two Hardened I 2 C Interfaces
• Two I/O pins to support I3C interface
• Two Hardened SPI Interfaces
• Two On-Chip Oscillators
• Low Frequency Oscillator - 10 kHz
• High Frequency Oscillator - 48 MHz
• 24 mA Current Drive RGB LED Outputs
• Three drive outputs in each device
• User selectable sink current up to 24 mA
• On-chip DSP
• Signed and unsigned 8-bit or 16-bit functions
• Functions include Multiplier, Accumulator, and Multiply-Accumulate (MAC)
• Flexible On-Chip Clocking
• Eight low skew global signal resource, six can be directly driven from external pins
• One PLL with dynamic interface per device
• Flexible Device Configuration
• SRAM is configured through:
• Standard SPI Interface
• Internal Nonvolatile Configuration Memory (NVCM)
• Ultra-Small Form Factor
• As small as 2.11 mm × 2.54 mm
• Applications
• Always-On Voice Recognition Application
• Smartphones
• Tablets and Consumer Handheld Devices
• Handheld Commercial and Industrial Devices
• Multi Sensor Management Applications
• Sensor Pre-processing and Sensor Fusion
• Always-On Sensor Applications
• USB 3.1 Type C Cable Detect / Power Delivery Applications

Over recommended operating conditions.

Table 4.5. DC Electrical Characteristics

• Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
• Compliance with the Thermal Management document is required.
• All voltages referenced to GND.

1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. See the Power-up Supply Sequence section. VCC and VCCPLL are recommended to be tied together to the same supply with an RC-based noise filter between them. Refer to iCE40 Hardware Checklist (FPGA-TN-02006).
2. See recommended voltages by I/O standard in subsequent table.
3. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
4. VPP_2V5 can, optionally, be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration modes subject to the condition that none of the HFOSC/LFOSC and RGB LED driver features are used. Otherwise, VPP_2V5 must be connected to a power supply with a minimum 2.30 V level.