ICE40UP5K

Part 1: Markdown Summary

Part: Lattice iCE40 UltraPlus Family

Type: FPGA (Field-Programmable Gate Array)

Key Specs:

• (No specific numerical values with units are provided in the excerpt)

Features:

• On-Chip Oscillator (HFOSC, LFOSC)
• User I2C IP
• User SPI IP
• RGB High Current Drive I/O Pins
• RGB PWM IP
• Non-Volatile Configuration Memory (NVCM)
• Power saving options
• Digital Signal Processor (DSP) blocks (supporting 8-bit x 8-bit and 16-bit x 16-bit multiply-accumulate)
• Embedded Block RAM (EBR)
• Phase Locked Loops (PLL)
• Programmable I/O Cells (PIC)
• Programmable Logic Blocks (PLB)

Applications:

• (Not specified in the excerpt)

Package:

• WLCSP (Wafer Level Chip Scale Packaging): dimensions not specified

• Flexible Logic Architecture
  • Two devices with 2800 to 5280 LUTs
  • Offered in WLCS and QFN packages
• Ultra-low Power Devices
  • Advanced 40 nm low power process
  • As low as 100 μA standby current typical
• Embedded Memory
  • Up to 1024 kb Single Port SRAM
  • Up to 120 kb sysMEM™ Embedded Block RAM
• Two Hardened I²C Interfaces
  • Two I/O pins to support I3C interface
• Two Hardened SPI Interfaces
• Two On-Chip Oscillators
  • Low Frequency Oscillator 10 kHz
  • High Frequency Oscillator 48 MHz
• 24 mA Current Drive RGB LED Outputs
  • Three drive outputs in each device
• User selectable sink current up to 24 mA
• On-chip DSP
  • Signed and unsigned 8-bit or 16-bit functions
  • Functions include Multiplier, Accumulator, and Multiply-Accumulate (MAC)
• Flexible On-Chip Clocking
  • Eight low skew global signal resource, six can be directly driven from external pins
  • One PLL with dynamic interface per device
• Flexible Device Configuration
  • SRAM is configured through:
  • Standard SPI Interface
  • Internal Nonvolatile Configuration Memory (NVCM)
• Ultra-Small Form Factor
  • As small as 2.11 mm × 2.54 mm
• Applications
  • Always-On Voice Recognition Application
  • Smartphones
  • Tablets and Consumer Handheld Devices
  • Handheld Commercial and Industrial Devices
  • Multi Sensor Management Applications
  • Sensor Pre-processing and Sensor Fusion
  • Always-On Sensor Applications
  • USB 3.1 Type C Cable Detect / Power Delivery Applications

Over recommended operating conditions.

Table 4.5. DC Electrical Characteristics

Notes:

• 1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Internal pull-up resistors are disabled.
• 1. T^J 25 ^oC, f = 1.0 MHz.
• 1. Refer to VIL and VIH in Table 4.13.
• 1. Input pins are clamped to VCCIO and GND by a diode. When input is higher than VCCIO or lower than GND, the Input Leakage current will be higher than the IIL and IIH.

Table 4.1. Absolute Maximum Ratings

Notes:

• Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
• Compliance with the Thermal Management document is required.
• All voltages referenced to GND.

Table 4.2. Recommended Operating Conditions

Notes:

• 1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence requirement. See the Power-up Supply Sequence section. VCC and VCCPLL are recommended to be tied together to the same supply with an RC-based noise filter between them. Refer to iCE40 Hardware Checklist (FPGA-TN-02006).
• 1. See recommended voltages by I/O standard in subsequent table.
• 1. VCCIO pins of unused I/O banks should be connected to the VCC power supply on boards.
• 1. VPP_2V5 can, optionally, be connected to a 1.8 V (+/–5%) power supply in Slave SPI Configuration modes subject to the condition that none of the HFOSC/LFOSC and RGB LED driver features are used. Otherwise, VPP_2V5 must be connected to a power supply with a minimum 2.30 V level.