EF2M45LG48

Part: SALELF ® 2 FPGA — SHANGHAI ANLOGIC INFOTECH CO.,LTD.

Type: FPGA (Field-Programmable Gate Array)

Description: Low-cost, low-power FPGA family built on 55nm technology, offering 1,500 to 4,480 LUTs, up to 206 I/Os, and featuring on-chip FLASH, distributed and embedded memory, PLLs, DSP blocks, and an embedded 8-bit SAR ADC.

Operating Conditions:

• Technology: 55nm low power consumption

Absolute Maximum Ratings:

Key Specs:

• LUTs: 1,500 to 4,480
• Max I/Os: 206
• Distributed Memory: Up to 35 Kbits
• Embedded Block Memory: Up to 700 Kbits
• PLLs: Multi-functional, with divide/multiply/phase shifting
• ADC: 8-bit SAR, 8 analog inputs, 1 MSPS sampling rate
• Global Clocks: 16
• On-chip differential resistance: 100-Ω

Features:

• Flexible Architecture with LUT4/LUT5 combination design
• On-chip FLASH for fast boot
• Distributed and Embedded Memory (9Kbits and 32Kbits RAM configurable as true dual-port)
• Programmable Logic Blocks (PLBs) with arithmetic logic and fast carry chain
• Source Synchronous I/O Interface supporting LVTTL, LVCMOS (3.3/2.5/1.8/1.5/1.2V), PCI, LVDS, LVPECL
• Hot socketing and programmable Pull-up/pull-down mode
• IOBB compatible with 5V input
• Multiple configuration modes: Master SPI, Slave Serial, Slave Parallel x8, Master Parallel x8, JTAG (IEEE-1532)
• Compatible with IEEE-1149.1 BASCAN
• Unique 64-bit DNA for enhanced safety protection
• Embedded Ring Oscillator
• Multiple Package Methods: LQFP/BGA (standard), XWFN/LGA/UBGA (small)

Applications:

• Low-cost, small applications in industrial markets
• Low-cost, small applications in communication markets

Package:

• 42 XWFN (4.2x4.2, 0.35mm pitch)
• 42 LGA (4.2x4.2, 0.35mm pitch)
• 48 LQFP (7x7, 0.5mm pitch)
• 100 LQFP (14x14, 0.5mm pitch)
• 144 LQFP (20x20, 0.5mm pitch)
• 256 LFBGA (17x17, 1.0mm pitch)
• 132 UBGA (8x8, 0.5mm pitch)

• 32 Kbits per block, can be configured as 2K x 16 or 4K x 8
• Independent A/B port clock
• Port A/B can be independently configured its data width, supporting 8-bit/ 16-bit widths
• Option to output latch (Support one-level pipeline)
• Two write operations : Normal, Write-through

Figure 2-23 ERAM32K Dual-port RAM

Table 2-12 ERAM32K Port signal

Table 2-12 ERAM32K Port signal

All parameters refer to the worst supply voltage and junction temperatures. Unless otherwise specified, the following information is available to: same commercial and industrial AC and DC characteristic. All parameters are values when the voltage is applied to the ground.