EF2L15

Part 1: Markdown Summary

Part: SALELF®2 FPGA from SHANGHAI ANLOGIC INFOTECH CO.,LTD.

Type: FPGA

Key Specs:

• LUTs: 1,500 to 4,480
• I/Os: Up to 206
• Process Technology: 55nm
• Distributed Memory: Up to 35Kbits
• Embedded Block Memory: Up to 700Kbits
• External Memory Support: 128Kbits, 256Kbits
• Global Clocks: 16
• PLL Division Factor Range: 1 to 128
• ADC Resolution: 8-bit SAR
• ADC Analog Inputs: 8
• ADC Sampling Rate: 1 MSPS
• DNA Security: 64-bit

Features:

• Flexible Architecture
• Low Power
• On-chip FLASH for fast boot
• Distributed and Embedded Memory with true dual-port configuration
• 9K RAM with dedicated FIFO control logic
• Programmable Logic Blocks with optimized LUT4/LUT5 combination
• Source Synchronous I/O Interface supporting LVTTL, LVCMOS, PCI, LVDS, LVPECL
• Hot socketing support
• Programmable Pull-up/pull-down mode
• On-chip 100-Ω differential resistance
• IOBB compatible with 5V input
• PLLs for frequency synthesis with dynamic phase selection
• Multiple configuration modes: Master SPI, Slave Serial, Slave Parallel x8, Master Parallel x8, JTAG (IEEE-1532)
• BASCAN compatible with IEEE-1149.1
• Unique 64-bit DNA for enhanced safety protection
• Embedded hard IP core including ADC and internal ring oscillator
• Multiple package methods: LQFP, BGA, XWFN, LGA, UBGA

Applications:

• null

Package:

• XWFN42: 4.2x4.2, 0.35mm pitch
• LGA42: 4.2x4.2, 0.35mm pitch
• LQFP48: 7x7, 0.5mm pitch
• LQFP100: 14x14, 0.5mm pitch
• LQFP144: 20x20, 0.5mm pitch
• LFBGA256: 17x17, 1.0mm pitch
• UBGA132: 8x8, 0.5mm pitch

Flexible Architecture

Four devices with 1, 500 to 4.480 LUTs and up to 206 I/Os

Low Power

Advanced 55nm low power consumption technology

On-chip FLASH

• Without external devices
• Fast boot

Distributed and Embedded Memory

• Up to 35Kbits distributed memory
• Up to 700Kbits Embedded Block Memory
• Both 9 Kbits and 32 Kbits RAM can be configured as true dual-port with multiple configurations. 9KRAM has dedicated FIFO control logic
• External 128Kbits, 256Kbits memory support

Programmable Logic Blocks (PLBs)

• Optimized LUT4/LUT5 combination design
• Dual-port distributed memory
• Arithmetic logic
• Fast carry chain logic

Source Synchronous I/O Interface

Following single-ended standards are

available by configuration:

• LVTTL, LVCMOS(3.3/2.5/1.8/1.5/1.2V)
• PCI
• Following differential standards are available by configuration
• LVDS, LVPECL
• Hot socketing
• Programmable Pull-up/pull-down mode
• On-chip 100-Ω differential resistance
• IOBB compatible with 5V input

Clock Resource

• 16 global clocks
• Two IOCLKs per bank for high-speed I/O interface
• Fast clock for optimized global clock
• PLLs for frequency synthesis
• Seven output clock s
• Division factor range from 1 to 128
• Five clocks output cascading
• Dynamic Phase selection

Configuration

• Master SPI (MSPI)
• Slave Serial (SS)

• Slave Parallel x8 (SP)
• Master Parallel x8 (MP)
• JTAG Mode (IEEE-1532)

BASCAN

• Compatible with IEEE-1149.1

• Enhanced Safety Protection design

  • Unique 64-bit DNA for each FPGA

• Embedded hard IP core

• ADC

• 8-bit SAR

• Eight analog input

• 1MHz Sampling rate (MSPS)

• Internal ring oscillator

Multiple Package Methods

Standard size: LQFP/BGA

Small size: XWFN/LGA/UBGA

Table 1-1 ELF2 FPGA Device Selection Guide

				Dis			ERAM		Total					MAX
Series	Device	LUTs	DFFs	RAM (Kbs)	9K	32K	128K	256K	(KBits)	DSP	PLL	Flash	MCU	user IO
	EF2L15	1520	1520	12	6	3	1	1	534	8	1	4Mb	-	206
L	EF2L25	2520	2520	20	9	4	1	1	593	12	1	4Mb	-	206
	EF2L45	4480	4480	35	12	6	1	1	684	15	1	4Mb	-	206
M	EF2M45	4480	4480	35	12	6	1	1	684	15	1	4Mb	M3	113

Table 1-2 ELF2 FPGA Package

Packages	EF2L15	EF2L25	EF2L45	EF2M45
42 XWFN(4.2x4.2, 0.35mm pitch)		29 (10+1)
42 LGA(4.2x4.2, 0.35mm pitch)		29 (10+1)
48 LQFP (7x7, 0.5mm pitch)				35 (5+9)
100 LQFP (14x14, 0.5mm pitch )	80 (15+17)			80 (15+17)
144 LQFP (20x20, 0.5mm pitch )	113 (24+25)		113 (24+25)	113 (24+25)
256 LFBGA (17x17, 1.0mm pitch)	206 (31+65)	206 (31+65)	206 (31+65)
132 UBGA(8x8,0.5mm pitch)			104(23+25)

Note:

1. 206 (31+65) indicate: user available IO number (user available True LVDS pair+ user

available Emulated LVDS pair).

1. JTAGEN conflicts with TCK, TMS, TDI, TDO, when JTAGEN pin used as user IO, TCK, TMS, TDI, TDO cannot be used as user IO, the above total IO number exclude JTAGEN pin.

All parameters refer to the worst supply voltage and junction temperatures. Unless otherwise specified, the following information is available to: same commercial and industrial AC and DC characteristic. All parameters are values when the voltage is applied to the ground.

DC Characteristics

Maximum Absolute Rating Value

Symbol Parameters Min Max Unit VCCAUX Auxiliary Supply Voltage -0.5 3.75 V VCCIO I/O Fed supply voltage -0.5 3.75 V VI DC input voltage Enhanced IOBE -0.5 3.75 V Basic IOBB -0.5 6.00 V VESDHBM Human body model discharge voltage ±1500 V VESDCDM Machine model discharge voltage ±500 V TSTG Storage temperature -65 150 °C TJ Operating junction temperature -40 125 °C

Table 3-1 Maximum Absolute Rating

Conditions outside the range listed in the absolute maximum ratings tables may cause permanent damage to the device. Conditions listed in the above table only indicates that working at these conditions will not cause damage to the device but it does not mean devices having normal function in these conditions. The functionality of device based on any maximum absolute rating may cause permanent damage to the device. Additionally, devices operation at the absolute maximum ratings for extended periods may undermine device reliability.

During transition, input signals may overshoot or undershoot as shown in the figure 3-1, and table 3-2 list the overshoot and undershoot duration as percentage of high time over 10-year life time.

Figure 3-1 Input signal overshoot/undershoot

Table 3-2 Overshoot and Undershoot Duration As Percentage of High Time over 10-Year Life Time

Parameter	Condition(V)	Under/Overshoot Duration as % of High Time	Unit
	-0.3	100	%
	-0.4	100	%
	-0.5	86	%
	-0.6	49	%
	-0.7	28	%
	-0.8	16	%
	-0.9	9.23	%
	-1	5.27	%
VI AC Input	-1.1	3	%
Voltage	3.7	100	%
	3.8	86	%
	3.9	49	%
	4	28	%
	4.1	16	%
	4.2	9.23	%
	4.3	5.27	%
	4.4	3	%

Recommended Operation Condition

Table 3-3 Recommended operation condition

Symbol		Parameter	Min	Typical	Max	Unit
VCCAUX		Auxiliary Supply Voltage	2.375	2.5/3.3	3.63	V
		Supply Voltage for I/O @ 3.3V	3.135	3.3	3.465	V
	Supply Voltage for I/O	@ 2.5V	2.375	2.5	2.625	V
VCCIO		Supply Voltage for I/O @ 1.8V	1.71	1.8	1.89	V
		Supply Voltage for I/O @ 1.5V	1.425	1.5	1.575	V
		Supply Voltage for I/O @ 1.2V	1.14	1.2	1.26	V
	DC input	EnhancedIOBE4	-0.5	-	3.6	V
VI	voltage	Basic IOBB	-0.3	-	5.5	V
VO	Output Voltage		0	-	VCCIO	V
	Operating	Commercial	0	-	85	°C
TJ	junction		-40	-	100	°C
	temperature	Industrial
TRAMP	Power supply ramp time		0.05	-	100	V/ms
IDiode		DC current across PCI-clamp diode	-	-	10	mA

Note:

• 1. VCCIO for all I/O banks must be powered up during device operation
• 1. All input buffer must be powered up by VCCIO
• 1. IO interface cannot directly connect to ground or VCCIO, if required to be connected to application, connecting with resistor is necessary.
• 1. If true differential pair pin is used as single-ended IO, the minimum input voltage should not lower than -0.3V or another true differential pair pin remains unused.

Basic Power Supply Requirements

Table 3-4 Minimum power supply for EF2L15/25/45BG256

Symbol	Basic power supply3	Note
VCCAUX	>=2.5V	Ripple peak-to-peak value should lower than 100mV, must supply power
VCCIO01	>=1.5V	JTAG used for download. Voltage should same as for downloader
VCCIO11	>=2.5V	Chip configuration device (internal FLASH)

		voltage connect to VCCIO1
VCCIO2	>=1.2V	Supply power when VCCIO unused
VCCIO3	>=1.2V	Supply power when VCCIO unused
VCCIO4	>=1.2V	Supply power when VCCIO unused
VCCIO5	>=1.2V	Supply power when VCCIO unused

• 1. Must supply power for POR.
• 1. When using LVDS, the supply voltage for the corresponding bank should be greater than or equal to 2.5V.
• 1. ADC used or not, voltage for ADC_VDDD/ADC_VDDA should be same, and voltage for ADC_VREF should not be greater than that of ADC_VREF. voltage for ADC_VREF should not greater than VCCAUX (ADC_VDDA/ADC_VDDD). ADC_VDDA and ADC_VDDD should connect to device maximum voltage by recommendation.

Table 3-5 Minimum voltage supply for EF2L15/45LG144 & EF2M45LG144

Symbols	Basic Voltage Supply3	Note
VCCAUX	>=2.5V	Ripple peak-to-peak value should lower than 100mV, must supply power
VCCIO0	>=1.2V	Supply power when VCCIO unused
VCCIO1	>=1.2V	Supply power when VCCIO unused
VCCIO21	>=2.5V	Chip configuration device (internal FLASH) voltage power connects to VCCIO2
VCCIO31	>=1.5V	JTAG used for download. Voltage should same as for downloader

Note:

• 1. Must supply power for POR.
• 1. When using LVDS, supply voltage for corresponding bank should be greater than or equal to 2.5V.
• 3. ADC used or not, voltage for ADC_VREF should not greater than VCCAUX (ADC_VDDA/ADC_VDDD)

Table 3-6 Minimum Power Supply for EF2L15LG100 & EF2M45LG100

Symbols	Basic Voltage Supply3	Note
VCCAUX	>=2.5V	Ripple peak-to-peak value should lower than 100mV, must supply power
VCCIO0	>=1.2V	Supply power when VCCIO unused

Symbols	Basic Voltage Supply3	Note
VCCIO1	>=1.2V	Supply power when VCCIO unused
VCCIO21	>=2.5V	Chip configuration device (internal FLASH) voltage power connects to VCCIO2
VCCIO31	>=1.5V	JTAG used for download. Voltage should same as for downloader

• 1. Must supply power for POR.
• 1. When using LVDS, supply voltage for corresponding BANK should be greater than or equal to 2.5V.
• 1. ADC used or not, ADC_VREF should not greater than VCCIO2(ADC_VDDA/ADC_VDDD).

Table 3-7 Minimum Power Supply for EF2M45LG48

Symbols	Basic Voltage Supply	Note
VCCAUX	>=2.5V	Ripple peak-to=peak value should lower than 100Mv,
		must supply power
VCCIO01	>=1.5V	JTAG used for download. Voltage should same as for
		downloader
VCCIO1	>=1.2V	Supply power when VCCIO unused
VCCIO2	>=1.2V	Supply power when VCCIO unused
1 VCCIO3	>=2.5V	Chip configuration device (internal FLASH) voltage
		power connects to VCCIO3

Note:

• 1. Must supply power for POR.
• 1. When using LVDS, supply voltage for corresponding bank should be greater than or equal to 2.5V.
• 1. ADC used or not, power supplied for ADC_VDDA/VCCAUX(ADC_VDDD) should be same, ADC_VREF should not greater than ADC_VDDA, also recommended to supply the highest voltage for ADC_VDDA/VCCAUX (ADC_VDDD).

Table 3-8 Minimum power supply for EF2L25XG42 & EF2L25AG42

Symbol	Basic Power Supply	Note
	VCCAUX >=2.5V	Ripple peak-to-peak value should lower than
		100mV, must supply power
VCCIO01	=VCCAUX	Fixed connection within package
VCCIO1	>=1.2V	Supply power when VCCIO unused
VCCIO2	>=1.2V	Supply power when VCCIO unused
VCCIO31	=VCCAUX	Fixed connection within package

• 1. Must supply power to POR power-on test
• 1. When using LVDS, supply voltage for corresponding bank should be greater than or equal to 2.5V.

Table 3-9 Minimum power supply for EF2L45UG132

Symbol	Basic Power Supply3	Note
		Ripple peak-to-peak value should lower than
VCCAUX	>=2.5V	100mV, must supply power
VCCIO01		JTAG used for download. Voltage should same as
	>=1.5V	for downloader
VCCIO11	>=2.5V	Chip configuration device (internal FLASH)
		voltage power connects to VCCIO1
VCCIO22	>=1.2V	Supply power when VCCIO unused2
2 VCCIO3	>=1.2V	Supply power when VCCIO unused2
2 VCCIO4	>=1.2V	Supply power when VCCIO unused2
2 VCCIO5	>=1.2V	Supply power when VCCIO unused2

Note:

• 1. Must supply power to POR power-on test
• 1. When using LVDS, supply voltage for corresponding bank should ≥ 2.5V.