EF2L25

FPGA

The EF2L25 is a fpga from SHANGHAI ANLOGIC INFOTECH CO.,LTD.. View the full EF2L25 datasheet below including electrical characteristics.

Manufacturer

SHANGHAI ANLOGIC INFOTECH CO.,LTD.

Overview

Part: SALELF ® 2 FPGA — SHANGHAI ANLOGIC INFOTECH CO.,LTD.

Type: FPGA (Field-Programmable Gate Array)

Description: Low-cost, low-power FPGA family built on 55nm technology, offering 1,500 to 4,480 LUTs, up to 206 I/Os, and featuring on-chip FLASH, distributed and embedded memory, PLLs, DSP blocks, and an embedded 8-bit SAR ADC.

Operating Conditions:

Technology: 55nm low power consumption

Absolute Maximum Ratings:

Key Specs:

LUTs: 1,500 to 4,480
Max I/Os: 206
Distributed Memory: Up to 35 Kbits
Embedded Block Memory: Up to 700 Kbits
PLLs: Multi-functional, with divide/multiply/phase shifting
ADC: 8-bit SAR, 8 analog inputs, 1 MSPS sampling rate
Global Clocks: 16
On-chip differential resistance: 100-Ω

Features:

Flexible Architecture with LUT4/LUT5 combination design
On-chip FLASH for fast boot
Distributed and Embedded Memory (9Kbits and 32Kbits RAM configurable as true dual-port)
Programmable Logic Blocks (PLBs) with arithmetic logic and fast carry chain
Source Synchronous I/O Interface supporting LVTTL, LVCMOS (3.3/2.5/1.8/1.5/1.2V), PCI, LVDS, LVPECL
Hot socketing and programmable Pull-up/pull-down mode
IOBB compatible with 5V input
Multiple configuration modes: Master SPI, Slave Serial, Slave Parallel x8, Master Parallel x8, JTAG (IEEE-1532)
Compatible with IEEE-1149.1 BASCAN
Unique 64-bit DNA for enhanced safety protection
Embedded Ring Oscillator
Multiple Package Methods: LQFP/BGA (standard), XWFN/LGA/UBGA (small)

Applications:

Low-cost, small applications in industrial markets
Low-cost, small applications in communication markets

Package:

42 XWFN (4.2x4.2, 0.35mm pitch)
42 LGA (4.2x4.2, 0.35mm pitch)
48 LQFP (7x7, 0.5mm pitch)
100 LQFP (14x14, 0.5mm pitch)
144 LQFP (20x20, 0.5mm pitch)
256 LFBGA (17x17, 1.0mm pitch)
132 UBGA (8x8, 0.5mm pitch)

Features

32 Kbits per block, can be configured as 2K x 16 or 4K x 8
Independent A/B port clock
Port A/B can be independently configured its data width, supporting 8-bit/ 16-bit widths
Option to output latch (Support one-level pipeline)
Two write operations : Normal, Write-through

Figure 2-23 ERAM32K Dual-port RAM

Table 2-12 ERAM32K Port signal

Port A	Direction	Description
dia[15:0]	Input	Data input to port A, dia [7:0]is valid in 8-bit input mode.
addra[10:0]	Input	Address input to port A, 2K depth
wbyte_ena	Input	Port A 16-bit mode, enable 8-bit write mode high active. In 8- bit mode connect 0
bytea	Input	As low bit address input in 8-bit input mode; In 16-bit mode and wbyte_ena=1, when bytea=1, high 8-bit write, when bytea=0, low 8-bit write.
doa[15:0]	Output	Data output to port A, only doa[7:0]is valid in 8-bit output mode.
clka	Input	Clock input to Port A, by default rising edge is valid (reversible)
rsta	Input	Data output to Port A register synchronous reset signal. By default high active (reversible).
csa	Input	Port A chipselect, by default high active (reversible)

Table 2-12 ERAM32K Port signal

wea	Input	Port A write/ read control, 1 refers to write, 0 refers to read.
ocea	Input	Port A data register clock enable, by default high active (reversible). It is valid when (REGMODE_A= 'OUTREG') is used.
Port B	Direction	Description
dib[15:0]	Input	Data input to port B, dib[7:0] is valid in 8-bit input mode.
addrb[10:0]	Input	Address input to port B, 2K depth
wbyte_enb	Input	Port B enable 8-bit write high active in 16-bit mode in 8-bit connect 0.
byteb	Input	As lowest address input in 8-bit mode; When wbyte_enb=1 in 16- bit mode, byteb=1 selects high 8-bit weite, when byteb=0 selects low 8-bit write.
dob[15:0]	Output	Data output to Port B, dob [7:0]is valid in 8-bit output mode.
clkb	Output	Clock input to Port B, by default rising edge is valid (reversible).
rstb	Input	Data output to Port B register synchronous reset signal. By default high active (reversible).
csb	Input	Port B chipselect, by default high active (reversible)
web	Input	Port B write/read operation control, 0 refers to write, 1 refers to read
oceb	Input	Port B data register clock enable, by default high active (reversible). It is valid when (REGMODE_B= 'OUTREG') is used.

Electrical Characteristics

All parameters refer to the worst supply voltage and junction temperatures. Unless otherwise specified, the following information is available to: same commercial and industrial AC and DC characteristic. All parameters are values when the voltage is applied to the ground.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
EF2L15	SHANGHAI ANLOGIC INFOTECH CO.,LTD.	—
EF2L45	SHANGHAI ANLOGIC INFOTECH CO.,LTD.	—
EF2M45	SHANGHAI ANLOGIC INFOTECH CO.,LTD.	—
EF2M45LG48	SHANGHAI ANLOGIC INFOTECH CO.,LTD.	—
EF2M45LG48B	SHANGHAI ANLOGIC INFOTECH CO.,LTD.	LQFP-48-EP(7x7)
ELF2	SHANGHAI ANLOGIC INFOTECH CO.,LTD.	—

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