DA14580-01AT1

Part: DA14580-01AT2 — Dialog Semiconductor (QFN40, 5 x 5 mm, reel)

Type: Bluetooth low energy SoC (ARM Cortex-M0 with integrated 2.4 GHz radio transceiver)

Description: Bluetooth 4.2 compliant low energy SoC with a 16 MHz ARM Cortex-M0, integrated radio (0 dBm TX, -93 dBm RX sensitivity), 42 kB SRAM, 32 kB OTP and an integrated buck/boost DC-DC converter.

Operating Conditions:

• Supply: supports coin cell (typ. 3.0 V) on VBAT3V and alkaline/NiMH (typ. 1.5 V) on VBAT1V
• Supply current at VBAT3V: TX 3.4 mA, RX 3.7 mA (with ideal DC-DC)
• CPU clock: 16 MHz
• GPIO tolerance: 3.3 V on ports P0–P3

Absolute Maximum Ratings:

• VPP during OTP programming: 6.7 V ± 0.1 V (programming condition, not an abs-max rating)

Key Specs:

• Receiver sensitivity: -93 dBm
• Transmit output power: 0 dBm; -20 dBm in 'Near Field Mode'
• Memory: 32 kB OTP, 42 kB system SRAM, 8 kB retention SRAM, 84 kB ROM
• 16 MHz crystal (±20 ppm max); 32 kHz crystal (±50 ppm, ±500 ppm max)
• ADC: 10-bit, 4 channels
• GPIO: 24 in QFN40 package, drive 4.8 mA per pin
• UART: 2 UARTs with hardware flow control up to 1 MBd
• I2C: 100 kHz and 400 kHz

Features:

• Fully integrated 2.4 GHz CMOS transceiver with single-wire antenna connection (no RF matching or RX/TX switching required)
• Compliant with Bluetooth V4.2, ETSI EN 300 328 / EN 300 440 Class 2, FCC CFR47 Part 15 and ARIB STD-T66
• ARM Cortex-M0 with SWD interface, dedicated Link Layer processor, AES-128 encryption
• Integrated buck/boost DC-DC converter; only 4 supply pins need decoupling
• Qualified BLE stack in ROM; OTA-updatable application code
• SPI+, 2 UARTs, I2C, 3-axis quadrature decoder
• General purpose, capture and sleep timers; watchdog; keyboard controller
• 16 MHz crystal and RC oscillators; 32 kHz crystal and RCX oscillators

Applications:

• Standalone application processor for Bluetooth low energy
• Data pump in hosted systems

Package:

• QFN40, 5 mm x 5 mm (DA14580-01AT2, reel of 5000)
• Other family packages: WLCSP34 (2.436 x 2.436 mm), QFN48 (6 x 6 mm), KGD (wafer/dice)

The Programmable Pin Assignment (PPA) provides a multiplexing function to the I/Os of on-chip peripherals. Any peripheral input or output signal can be freely mapped to any I/O port bit by setting:

Pxy_MODE_REG[4-0]:

0x00 to 0x16: Peripheral IO ID (PID)

Refer to the Px_MODE_REGs for an overview of the available PIDs. Analog ADC has fixed pin assignment in order to limit interference with the digital domain. The SWD interface (JTAG) is mapped on P1_4 and P1_5.

Figure 1: QFN48 Package Outline Drawing

Figure 2: QFN40 Package Outline Drawing

Figure 3: WLCSP34 Package Outline Drawing

FINAL