CC1101

Low-Power Sub-1 GHz RF Transceiver

Manufacturer

Overview

Part: CC1101

Type: Low-Power Sub-1 GHz RF Transceiver

Key Specs:

Sensitivity: -116 dBm at 0.6 kBaud, 433 MHz, 1% packet error rate
RX Current Consumption: 14.7 mA at 1.2 kBaud, 868 MHz
Programmable Output Power: up to +12 dBm
Programmable Data Rate: 0.6 to 600 kbps
Frequency Bands: 300-348 MHz, 387-464 MHz, 779-928 MHz
Sleep Mode Current Consumption: 200 nA
Fast Startup Time: 240 μs from sleep to RX or TX mode
Transmit/Receive FIFOs: 64 byte
Frequency Synthesizer Settling Time: 75 μs

Features:

Supports 2-FSK, 4-FSK, GFSK, MSK, OOK, and flexible ASK shaping
Extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio
Controlled via SPI interface
Integrated analog temperature sensor
On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling
Digital RSSI output
Programmable channel filter bandwidth, Carrier Sense (CS) indicator, Preamble Quality Indicator (PQI)
Support for automatic Clear Channel Assessment (CCA)
Support for per-package Link Quality Indication (LQI)
Optional automatic whitening and dewhitening of data
Wake-on-radio functionality for automatic low-power RX polling
Completely onchip frequency synthesizer, no external filters or RF switch needed
RoHS compliant
Suited for systems targeting compliance with EN 300 220, FCC CFR Part 15, and Wireless MBUS standard EN 13757-4:2005
Support for asynchronous and synchronous serial receive/transmit mode

Applications:

Ultra low-power wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands
Wireless alarm and security systems
Industrial monitoring and control
Wireless sensor networks
AMR – Automatic Meter Reading
Home and building automation
Wireless MBUS

Package:

QLP 4x4 mm package, 20 pins

Features

2-FSK, 4-FSK, GFSK, and MSK supported as well as OOK and flexible ASK shaping
Suitable for frequency hopping systems due to a fast settling frequency synthesizer; 75 μs settling time
Automatic Frequency Compensation (AFC) can be used to align the frequency synthesizer to the received signal centre frequency
Integrated analog temperature sensor

Applications

Ultra low-power wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands
Wireless alarm and security systems
Industrial monitoring and control
Wireless sensor networks
AMR – Automatic Meter Reading
Home and building automation
Wireless MBUS

Pin Configuration

The CC1101 pin-out is shown in Figure 8 and Table 19. See Section 26 for details on the I/O configuration.

Figure 8: Pinout Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip

| Pin # | Pin Name | Pin type |-------|-----------|--------- | 1 | SCLK | Digital Input | 2 | SO (GDO1) | Digital Output | | | | 3 | GDO2 | Digital Output | | | | | | | | | | | | | | | | 4 | DVDD | Power (Digital) | 5 | DCOUPL | Power (Digital) | | | | 6 | GDO0 | Digital I/O | | (ATEST) | | | | | | | | | | | | | | | | | | | | 7 | CSn | Digital Input | 8 | XOSC_Q1 | Analog I/O | 9 | AVDD | Power (Analog) | 10 | XOSC_Q2 | Analog I/O | 11 | AVDD | Power (Analog) | 12 | RF_P | RF I/O | | | | 13 | RF_N | RF I/O | | | | 14 | AVDD | Power (Analog) | 15 | AVDD | Power (Analog) | 16 | GND | Ground (Analog) | 17 | RBIAS | Analog I/O | 18 | DGUARD | Power (Digital) | 19 | GND | | 20 | SI | Digital Input Table | Description | ---------|---------------------------------------------------------------------------------------------------------------------------|--| | Serial configuration interface, clock input | | Serial configuration interface, data output | | Optional general output pin when CSn is high | | Digital output pin for general use: | | 
Test signals | | 
FIFO status signals | | 
Clear channel indicator | | 
Clock output, down-divided from XOSC | | 
Serial output RX data | | 1.8 - 3.6 V digital power supply for digital I/O's and for the digital core
voltage regulator | | 1.6 - 2.0 V digital power supply output for decoupling | | NOTE: This pin is intended for use with the CC1101 only. It can not be used
to provide supply voltage to other devices | | Digital output pin for general use: | | 
Test signals | | 
FIFO status signals | | 
Clear channel indicator | | 
Clock output, down-divided from XOSC | | 
Serial output RX data | | 
Serial input TX data | | Also used as analog test I/O for prototype/production testing | | Serial configuration interface, chip select | | Crystal oscillator pin 1, or external clock input | | 1.8 - 3.6 V analog power supply connection | | Crystal oscillator pin 2 | | 1.8 - 3.6 V analog power supply connection | | Positive RF input signal to LNA in receive mode | | Positive RF output signal from PA in transmit mode | | Negative RF input signal to LNA in receive mode | | Negative RF output signal from PA in transmit mode | | 1.8 - 3.6 V analog power supply connection | | 1.8 - 3.6 V analog power supply connection | | Analog ground connection | | External bias resistor for reference current | | Power supply connection for digital noise isolation | Ground (Digital) | Ground connection for digital noise isolation | | Serial configuration interface, data input | 19: Pinout Overview

Electrical Characteristics

4.1 Current Consumption

T^A = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]). Reduced current settings (MDMCFG2.DEM\_DCFILT\_OFF=1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Table 7 for additional details on current consumption and sensitivity.

Parameter	Typ	Max	Unit	Condition
Current consumption in power down modes	0.2	1	A	Voltage regulator to digital part off, register values retained (SLEEP state). All GDO pins programmed to 0x2F (HW to 0)
	0.5		A	Voltage regulator to digital part off, register values retained, low power RC oscillator running (SLEEP state with WOR enabled)
	100		A	Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)
	165		A	Voltage regulator to digital part on, all other modules in power down (XOFF state)
Current consumption	8.8		A	Automatic RX polling once each second, using low-power RC oscillator, with 542 kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1)
	35.3		A	Same as above, but with signal in channel above carrier sense level, 1.96 ms RX timeout, and no preamble/sync word found
	1.4		A	Automatic RX polling every 15th second, using low-power RC oscillator, with 542 kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1)
	39.3		A	Same as above, but with signal in channel above carrier sense level, 36.6 ms RX timeout, and no preamble/sync word found
	1.7		mA	Only voltage regulator to digital part and crystal oscillator running (IDLE state)
	8.4		mA	Only the frequency synthesizer is running (FSTXON state). This currents consumption is also representative for the other intermediate states when going from IDLE to RX or TX, including the calibration state
Current consumption, 315 MHz	15.4		mA	Receive mode, 1.2 kBaud, reduced current, input at sensitivity limit
	14.4		mA	Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit
	15.2		mA	Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit
	14.3		mA	Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit
	16.5		mA	Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit
	15.1		mA	Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit
	27.4		mA	Transmit mode, +10 dBm output power
	15.0		mA	Transmit mode, 0 dBm output power
	12.3		mA	Transmit mode, –6 dBm output power

Parameter	Typ	Unit	Condition
Current consumption, 433 MHz	16.0	mA	Receive mode, 1.2 kBaud, register settings optimized for reduced current, input at sensitivity limit
	15.0	mA	Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit
	15.7	mA	Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit
	15.0	mA	Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit
	17.1	mA	Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit
	15.7	mA	Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit
	29.2	mA	Transmit mode, +10 dBm output power
	16.0	mA	Transmit mode, 0 dBm output power
	13.1	mA	Transmit mode, –6 dBm output power
Current consumption, 868/915 MHz	15.7	mA	Receive mode, 1.2 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 3 for current consumption with register settings optimized for sensitivity.
	14.7	mA	Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 3 for current consumption with register settings optimized for sensitivity.
	15.6	mA	Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 3 for current consumption with register settings optimized for sensitivity.
	14.6	mA	Receive mode, 38.4 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 3 for current consumption with register settings optimized for sensitivity.
	16.9	mA	Receive mode, 250 kBaud, register settings optimized for reduced current, input at sensitivity limit. See Figure 3 for current consumption with register settings optimized for sensitivity.
	15.6	mA	Receive mode, 250 kBaud, register settings optimized for reduced current, input well above sensitivity limit. See Figure 3 for current consumption with register settings optimized for sensitivity.
	34.2	mA	Transmit mode, +12 dBm output power, 868 MHz
	30.0	mA	Transmit mode, +10 dBm output power, 868 MHz
	16.8	mA	Transmit mode, 0 dBm output power, 868 MHz
	16.4	mA	Transmit mode, –6 dBm output power, 868 MHz.
	33.4	mA	Transmit mode, +11 dBm output power, 915 MHz
	30.7	mA	Transmit mode, +10 dBm output power, 915 MHz
	17.2	mA	Transmit mode, 0 dBm output power, 915 MHz
	17.0	mA	Transmit mode, –6 dBm output power, 915 MHz

Table 4: Current Consumption

| | | Supply Voltage
VDD = 1.8 V | | | Supply Voltage
VDD = 3.0 V | | Supply Voltage
VDD = 3.6 V | |----------------------------------------|------|-------------------------------|------|------|-------------------------------|------|-------------------------------|------|------| | Temperature [°C] | -40 | 25 | 85 | -40 | 25 | 85 | -40 | 25 | 85 | | Current [mA], PATABLE=0xC0,
+12 dBm | 32.7 | 31.5 | 30.5 | 35.3 | 34.2 | 33.3 | 35.5 | 34.4 | 33.5 | | Current [mA], PATABLE=0xC5,
+10 dBm | 30.1 | 29.2 | 28.3 | 30.9 | 30.0 | 29.4 | 31.1 | 30.3 | 29.6 | | Current [mA], PATABLE=0x50,
0 dBm | 16.4 | 16.0 | 15.6 | 17.3 | 16.8 | 16.4 | 17.6 | 17.1 | 16.7 |

Table 5: Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz

| | | Supply Voltage
VDD = 1.8 V | | | Supply Voltage
VDD = 3.0 V | | Supply Voltage
VDD = 3.6 V | |----------------------------------------|------|-------------------------------|------|------|-------------------------------|------|-------------------------------|------|------| | Temperature [°C] | -40 | 25 | 85 | -40 | 25 | 85 | -40 | 25 | 85 | | Current [mA], PATABLE=0xC0,
+11 dBm | 31.9 | 30.7 | 29.8 | 34.6 | 33.4 | 32.5 | 34.8 | 33.6 | 32.7 | | Current [mA], PATABLE=0xC3,
+10 dBm | 30.9 | 29.8 | 28.9 | 31.7 | 30.7 | 30.0 | 31.9 | 31.0 | 30.2 | | Current [mA], PATABLE=0x8E,
0 dBm | 17.2 | 16.8 | 16.4 | 17.6 | 17.2 | 16.9 | 17.8 | 17.4 | 17.1 |

Table 6: Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz

Figure 3: Typical RX Current Consumption over Temperature and Input Power Level, 868/915 MHz, Sensitivity Optimized Setting

4.2 RF Receive Section

T^A = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]).

Parameter	Min	Typ	Max	Unit	Condition/Note
Digital channel filter bandwidth	58		812	kHz	User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal)
Spurious emissions		-68	–57	dBm	25 MHz – 1 GHz (Maximum figure is the ETSI EN 300 220 limit)
		-66	–47	dBm	Above 1 GHz (Maximum figure is the ETSI EN 300 220 limit)
					Typical radiated spurious emission is -49 dBm measured at the VCO frequency
RX latency		9		bit	Serial operation. Time from start of reception until data is available on the receiver data output pin is equal to 9 bit

315 MHz

| 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) | |-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|-----|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----|-----------------------------------------------------------------------|--|--|--| | Receiver sensitivity
-111
dBm | | | Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 17.2 mA to 15.4 mA at the
sensitivity limit. The sensitivity is typically reduced to -109 dBm | | 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) | | Receiver sensitivity | | -88 | | dBm | MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates >
250 kBaud |

433 MHz

| 0.6 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 14.3 kHz deviation, 58 kHz digital channel filter bandwidth) | |-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|------|--|-----|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--|--| | Receiver sensitivity | | -116 | | dBm | | 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) | | Receiver sensitivity | | -112 | | dBm | Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 18.0 mA to 16.0 mA at the
sensitivity limit. The sensitivity is typically reduced to -110 dBm | | 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 | | | | | (GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) | | Receiver sensitivity | | –104 | | dBm | | 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth) | | Receiver sensitivity | | -95 | | dBm |

868/915 MHz

| 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0
(GFSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) | |------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|------|--|-----|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|--|--|--| | Receiver sensitivity | | –112 | | dBm | Sensitivity can be traded for current consumption by setting
MDMCFG2.DEM_DCFILT_OFF=1. The typical current
consumption is then reduced from 17.7 mA to 15.7 mA at
sensitivity limit. The sensitivity is typically reduced to -109 dBm | | Saturation | | –14 | | dBm | FIFOTHR.CLOSE_IN_RX=0. See more in DN010 [8] | | Adjacent channel
rejection
±100 kHz offset | | 37 | | dB | Desired channel 3 dB above the sensitivity limit.
100 kHz channel spacing
See Figure 4 for selectivity performance at other offset
frequencies | | Image channel
rejection | | 31 | | dB | IF frequency 152 kHz
Desired channel 3 dB above the sensitivity limit |

Parameter	Typ	Unit	Condition/Note
Blocking ±2 MHz offset ±10 MHz offset	-50 -40	dBm dBm	Desired channel 3 dB above the sensitivity limit See Figure 4 for blocking performance at other offset frequencies
38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0			(GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)
Receiver sensitivity	–104	dBm	Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.6 mA at the sensitivity limit. The sensitivity is typically reduced to -102 dBm
Saturation	–16	dBm	FIFOTHR.CLOSE_IN_RX=0. See more in DN010 [8]
Adjacent channel rejection -200 kHz offset +200 kHz offset	12 25	dB dB	Desired channel 3 dB above the sensitivity limit. 200 kHz channel spacing See Figure 5 for blocking performance at other offset frequencies
Image channel rejection	23	dB	IF frequency 152 kHz Desired channel 3 dB above the sensitivity limit
Blocking ±2 MHz offset ±10 MHz offset	-50 -40	dBm dBm	Desired channel 3 dB above the sensitivity limit See Figure 5 for blocking performance at other offset frequencies
250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0			(GFSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth)
Receiver sensitivity	–95	dBm	Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.9 mA to 16.9 mA at the sensitivity limit. The sensitivity is typically reduced to -91 dBm
Saturation	–17	dBm	FIFOTHR.CLOSE_IN_RX=0. See more in DN010 [8]
Adjacent channel rejection	25	dB	Desired channel 3 dB above the sensitivity limit. 750 kHz channel spacing See Figure 6 for blocking performance at other offset frequencies
Image channel rejection	14	dB	IF frequency 304 kHz Desired channel 3 dB above the sensitivity limit
Blocking ±2 MHz offset ±10 MHz offset	-50 -40	dBm dBm	Desired channel 3 dB above the sensitivity limit See Figure 6 for blocking performance at other offset frequencies
500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0			(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver sensitivity	–90	dBm	MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud
Image channel rejection	1	dB	IF frequency 355 kHz Desired channel 3 dB above the sensitivity limit
Blocking ±2 MHz offset ±10 MHz offset	-50 -40	dBm dBm	Desired channel 3 dB above the sensitivity limit See Figure 7 for blocking performance at other offset frequencies
			4-FSK, 125 kBaud data rate (250 kbps), sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (1% packet error rate, 20 bytes packet length, 127 kHz deviation, 406 kHz digital channel filter bandwidth)
Receiver sensitivity	-96	dBm
			4-FSK, 250 kBaud data rate (500 kbps), sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (1% packet error rate, 20 bytes packet length, 254 kHz deviation, 812 kHz digital channel filter bandwidth)
Receiver sensitivity	-91	dBm
			4-FSK, 300 kBaud data rate (600 kbps), sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (1% packet error rate, 20 bytes packet length, 228 kHz deviation, 812 kHz digital channel filter bandwidth)
Receiver sensitivity	-89	dBm
Table 7: RF Receive Section

| | Supply Voltage
VDD = 1.8 V | | | | Supply Voltage
VDD = 3.0 V | | Supply Voltage
VDD = 3.6 V | |---------------------------------|-------------------------------|------|------|------|-------------------------------|------|-------------------------------|------|------|--| | Temperature [°C] | -40 | 25 | 85 | -40 | 25 | 85 | -40 | 25 | 85 | | Sensitivity [dBm]
1.2 kBaud | -113 | -112 | -110 | -113 | -112 | -110 | -113 | -112 | -110 | | Sensitivity [dBm]
38.4 kBaud | -105 | -104 | -102 | -105 | -104 | -102 | -105 | -104 | -102 | | Sensitivity [dBm]
250 kBaud | -97 | -96 | -92 | -97 | -95 | -92 | -97 | -94 | -92 | | Sensitivity [dBm]
500 kBaud | -91 | -90 | -86 | -91 | -90 | -86 | -91 | -90 | -86 | Table 8: Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized Setting

| | Supply Voltage
VDD = 1.8 V | | | | Supply Voltage
VDD = 3.0 V | | Supply Voltage
VDD = 3.6 V | |---------------------------------|-------------------------------|------|------|------|-------------------------------|------|-------------------------------|------|------|--| | Temperature [°C] | -40 | 25 | 85 | -40 | 25 | 85 | -40 | 25 | 85 | | Sensitivity [dBm]
1.2 kBaud | -113 | -112 | -110 | -113 | -112 | -110 | -113 | -112 | -110 | | Sensitivity [dBm]
38.4 kBaud | -105 | -104 | -102 | -104 | -104 | -102 | -105 | -104 | -102 | | Sensitivity [dBm]
250 kBaud | -97 | -94 | -92 | -97 | -95 | -92 | -97 | -95 | -92 | | Sensitivity [dBm]
500 kBaud | -91 | -89 | -86 | -91 | -90 | -86 | -91 | -89 | -86 | Table 9: Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized Setting

Figure 4: Typical Selectivity at 1.2 kBaud Data Rate, 868.3 MHz, GFSK, 5.2 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 58 kHz

Figure 5: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, GFSK, 20 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 100 kHz

Figure 6: Typical Selectivity at 250 kBaud Data Rate, 868 MHz, GFSK, IF Frequency is 304 kHz and the Digital Channel Filter Bandwidth is 540 kHz

Figure 7: Typical Selectivity at 500 kBaud Data Rate, 868 MHz, GFSK, IF Frequency is 355 kHz and the Digital Channel Filter Bandwidth is 812 kHz

4.3 RF Transmit Section

$T_A = 25$ °C, VDD = 3.0 V, +10 dBm if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]).

Parameter	Typ	Unit	Condition/Note
Differential load impedance			Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1101EM reference
315 MHz	122 + j31	Ω	designs ([1] and [2]) available from the TI website
433 MHz	116 + j41	Ω
868/915 MHz	86.5 + j43	Ω
Output power, highest setting			Output power is programmable, and full range is available in all frequency bands. Output power may be restricted by
315 MHz	+10	dBm	regulatory limits.
433 MHz	+10	dBm	See Design Note DN013 [15] for output power and harmonics figures when using multi-layer inductors. The output power is
868 MHz	+12	dBm	then typically +10 dBm when operating at 868/915 MHz.
915 MHz	+11	dBm	Delivered to a 50 $\Omega$ single-ended load via CC1101EM reference designs ([1] and [2]) RF matching network
Output power, lowest setting	-30	dBm	Output power is programmable, and full range is available in all frequency bands
			Delivered to a $50\Omega$ single-ended load via CC1101EM reference designs ([1] and [2]) RF matching network
Harmonics, radiated			Measured on CC1101EM reference designs ([1] and [2]) with CW, maximum output power
2 ^nd Harm, 433 MHz 3 ^rd Harm, 433 MHz	-49 -40	dBm dBm	The antennas used during the radiated measurements (SMAFF-433 from R.W. Badland and Nearson S331 868/915) play a part in attenuating the harmonics
2 ^nd Harm, 868 MHz 3 ^rd Harm, 868 MHz	-47 -55	dBm dBm	projection and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the second and the se
2 ^nd Harm, 915 MHz 3 ^rd Harm, 915 MHz	-50 -54	dBm dBm	Note: All harmonics are below -41.2 dBm when operating in the 902 – 928 MHz band
Harmonics, conducted			Manager durith and all pur OW at 045 MHz and 400 MHz
315 MHz	< -35 < -53	dBm dBm	Measured with +10 dBm CW at 315 MHz and 433 MHz Frequencies below 960 MHz Frequencies above 960 MHz
433 MHz	-43 < -45	dBm dBm	Frequencies below 1 GHz Frequencies above 1 GHz
868 MHz 2 ^nd Harm other harmonics	-36 < -46	dBm dBm	Measured with +12 dBm CW at 868 MHz
915 MHz 2 ^nd Harm	-34	dBm	Measured with +11 dBm CW at 915 MHz (requirement is -20 dBc under FCC 15.247)
other harmonics	< -50	dBm	,

Parameter	Typ	Unit	Condition/Note
Spurious emissions conducted, harmonics not included
315 MHz	< -58 < -53	dBm dBm	Measured with +10 dBm CW at 315 MHz and 433 MHz Frequencies below 960 MHz Frequencies above 960 MHz
433 MHz	< -50 < -54 < -56	dBm dBm dBm	Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz
868 MHz	< -50 < -52 < -53	dBm dBm dBm	Measured with +12 dBm CW at 868 MHz Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz
			All radiated spurious emissions are within the limits of ETSI. The peak conducted spurious emission is -53 dBm at 699 MHz (868 MHz – 169 MHz), which is in a frequency band limited to -54 dBm by EN 300 220. An alternative filter can be used to reduce the emission at 699 MHz below -54 dBm, for conducted measurements, and is shown in Figure 11. See more information in DN017 [9].
			For compliance with modulation bandwidth requirements under EN 300 220 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.
915 MHz	< -51 < -54	dBm dBm	Measured with +11 dBm CW at 915 MHz Frequencies below 960 MHz Frequencies above 960 MHz
TX latency	8	bit	Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports

Table 10: RF Transmit Section

| | | Supply Voltage
VDD = 1.8 V | | | Supply Voltage
VDD = 3.0 V | | Supply Voltage
VDD = 3.6 V | |----------------------------------------------|-----|-------------------------------|----|-----|-------------------------------|----|-------------------------------|----|----| | Temperature [°C] | -40 | 25 | 85 | -40 | 25 | 85 | -40 | 25 | 85 | | Output Power [dBm],
PATABLE=0xC0, +12 dBm | 12 | 11 | 10 | 12 | 12 | 11 | 12 | 12 | 11 | | Output Power [dBm],
PATABLE=0xC5, +10 dBm | 11 | 10 | 9 | 11 | 10 | 10 | 11 | 10 | 10 | | Output Power [dBm],
PATABLE=0x50, 0 dBm | 1 | 0 | -1 | 2 | 1 | 0 | 2 | 1 | 0 |

Table 11: Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz

| | | Supply Voltage
VDD = 1.8 V | | | Supply Voltage
VDD = 3.0 V | | Supply Voltage
VDD = 3.6 V | |----------------------------------------------|-----|-------------------------------|----|-----|-------------------------------|----|-------------------------------|----|----| | Temperature [°C] | -40 | 25 | 85 | -40 | 25 | 85 | -40 | 25 | 85 | | Output Power [dBm],
PATABLE=0xC0, +11 dBm | 11 | 10 | 10 | 12 | 11 | 11 | 12 | 11 | 11 | | Output Power [dBm],
PATABLE=0x8E, +0 dBm | 2 | 1 | 0 | 2 | 1 | 0 | 2 | 1 | 0 |

Table 12: Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz

4.4 Crystal Oscillator

T^A = 25C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([1] and [2]).

Parameter	Min	Typ	Max	Unit	Condition/Note
Crystal frequency	26	26	27	MHz	For compliance with modulation bandwidth requirements under EN 300 220 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.
Tolerance		±40		ppm	This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.
Load capacitance	10	13	20	pF	Simulated over operating conditions
ESR			100	
Start-up time		150		µs	This parameter is to a large degree crystal dependent. Measured on the CC1101EM reference designs ([1] and [2]) using crystal AT-41CD2 from NDK

Table 13: Crystal Oscillator Parameters

4.5 Low Power RC Oscillator

T^A = 25C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([1] and [2]).

Parameter	Min	Typ	Max	Unit	Condition/Note
Calibrated frequency	34.7	34.7	36	kHz	Calibrated RC Oscillator frequency is XTAL frequency divided by 750
Frequency accuracy after calibration			±1	%
Temperature coefficient		+0.5		% / C	Frequency drift when temperature changes after calibration
Supply voltage coefficient		+3		% / V	Frequency drift when supply voltage changes after calibration
Initial calibration time		2		ms	When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running

Table 14: RC Oscillator Parameters

4.6 Frequency Synthesizer Characteristics

$T_A = 25^{\circ}$ C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal.

Parameter	Min	Typ	Max	Unit	Condition/Note
Programmed frequency resolution	397	F _XOSC / 2 ¹⁶	412	Hz	26-27 MHz crystal. The resolution (in Hz) is equal for all frequency bands
Synthesizer frequency tolerance		±40		ppm	Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing
RF carrier phase noise		-92		dBc/Hz	@ 50 kHz offset from carrier
RF carrier phase noise		-92		dBc/Hz	@ 100 kHz offset from carrier
RF carrier phase noise		-92		dBc/Hz	@ 200 kHz offset from carrier
RF carrier phase noise		-98		dBc/Hz	@ 500 kHz offset from carrier
RF carrier phase noise		-107		dBc/Hz	@ 1 MHz offset from carrier
RF carrier phase noise		-113		dBc/Hz	@ 2 MHz offset from carrier
RF carrier phase noise		-119		dBc/Hz	@ 5 MHz offset from carrier
RF carrier phase noise		-129		dBc/Hz	@ 10 MHz offset from carrier
PLL turn-on / hop time ( See Table 34)	72	75	75	μS	Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running.
PLL RX/TX settling time ( See Table 34)	29	30	30	μs	Settling time for the 1-IF frequency step from RX to TX
PLL TX/RX settling time ( See Table 34)	30	31	31	μS	Settling time for the 1-IF frequency step from TX to RX. 250 kbps data rate.
PLL calibration time (See Table 35)	685	712	724	μS	Calibration can be initiated manually or automatically before entering or after leaving RX/TX

Table 15: Frequency Synthesizer Parameters

4.7 Analog Temperature Sensor

$T_A = 25^{\circ}C$ , VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([1] and [2]). Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

Parameter	Min	Typ	Max	Unit	Condition/Note
Output voltage at –40°C		0.651		V
Output voltage at 0°C		0.747		V
Output voltage at +40°C		0.847		V
Output voltage at +80°C		0.945		V
Temperature coefficient		2.47		mV/°C	Fitted from -20 °C to +80 °C
Error in calculated temperature, calibrated	-2 *	0	2 *	°C	From –20 °C to +80 °C when using 2.47 mV / °C, after 1-point calibration at room temperature
					*The indicated minimum and maximum error with 1- point calibration is based on simulated values for typical process parameters
Current consumption increase when enabled		0.3		mA
Table 16: Analog Temperature Sensor Parameters

4.8 DC Characteristics

$T_A = 25^{\circ}C$ if nothing else stated.

Digital Inputs/Outputs	Min	Max	Unit	Condition
Logic "0" input voltage	0	0.7	V
Logic "1" input voltage	VDD-0.7	VDD	V
Logic "0" output voltage	0	0.5	V	For up to 4 mA output current
Logic "1" output voltage	VDD-0.3	VDD	V	For up to 4 mA output current
Logic "0" input current	N/A	-50	nA	Input equals 0V
Logic "1" input current	N/A	50	nA	Input equals VDD

Table 17: DC Characteristics

4.9 Power-On Reset

For proper Power-On-Reset functionality the power supply should comply with the requirements in Table 18 below. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 19.1 on page 50 for further details.

Parameter	Min	Typ	Max	Unit	Condition/Note
Power-up ramp-up time			5	ms	From 0V until reaching 1.8V
Power off time	1			ms	Minimum time between power-on and power-off

Table 18: Power-On Reset Requirements

5 Pin Configuration

The CC1101 pin-out is shown in Figure 8 and Table 19. See Section 26 for details on the I/O configuration.

Figure 8: Pinout Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip

| Pin # | Pin Name | Pin type | Description | |-------|-----------|------------------|---------------------------------------------------------------------------------------------------------------------------|--| | 1 | SCLK | Digital Input | Serial configuration interface, clock input | | 2 | SO (GDO1) | Digital Output | Serial configuration interface, data output | | | | | Optional general output pin when CSn is high | | 3 | GDO2 | Digital Output | Digital output pin for general use: | | | | | 
Test signals | | | | | 
FIFO status signals | | | | | 
Clear channel indicator | | | | | 
Clock output, down-divided from XOSC | | | | | 
Serial output RX data | | 4 | DVDD | Power (Digital) | 1.8 - 3.6 V digital power supply for digital I/O's and for the digital core
voltage regulator | | 5 | DCOUPL | Power (Digital) | 1.6 - 2.0 V digital power supply output for decoupling | | | | | NOTE: This pin is intended for use with the CC1101 only. It can not be used
to provide supply voltage to other devices | | 6 | GDO0 | Digital I/O | Digital output pin for general use: | | | (ATEST) | | 
Test signals | | | | | 
FIFO status signals | | | | | 
Clear channel indicator | | | | | 
Clock output, down-divided from XOSC | | | | | 
Serial output RX data | | | | | 
Serial input TX data | | | | | Also used as analog test I/O for prototype/production testing | | 7 | CSn | Digital Input | Serial configuration interface, chip select | | 8 | XOSC_Q1 | Analog I/O | Crystal oscillator pin 1, or external clock input | | 9 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection | | 10 | XOSC_Q2 | Analog I/O | Crystal oscillator pin 2 | | 11 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection | | 12 | RF_P | RF I/O | Positive RF input signal to LNA in receive mode | | | | | Positive RF output signal from PA in transmit mode | | 13 | RF_N | RF I/O | Negative RF input signal to LNA in receive mode | | | | | Negative RF output signal from PA in transmit mode | | 14 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection | | 15 | AVDD | Power (Analog) | 1.8 - 3.6 V analog power supply connection | | 16 | GND | Ground (Analog) | Analog ground connection | | 17 | RBIAS | Analog I/O | External bias resistor for reference current | | 18 | DGUARD | Power (Digital) | Power supply connection for digital noise isolation | | 19 | GND | Ground (Digital) | Ground connection for digital noise isolation | | 20 | SI | Digital Input | Serial configuration interface, data input | Table 19: Pinout Overview

Circuit Description

Figure 9: CC1101 Simplified Block Diagram

A simplified block diagram of CC1101 is shown in Figure 9.

CC1101 features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation, and bit/packet synchronization are performed digitally.

The transmitter part of CC1101 is based on direct synthesis of the RF frequency. The

Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Parameter	Min	Max	Units	Condition
Supply voltage	–0.3	3.9	V	All supply pins must have the same voltage
Voltage on any digital pin	–0.3	VDD + 0.3, max 3.9	V
Voltage on the pins RF_P, RF_N, DCOUPL, RBIAS	–0.3	2.0	V
Voltage ramp-up rate		120	kV/µs
Input RF level		+10	dBm
Storage temperature range	–50	150	C
Solder reflow temperature		260	C	According to IPC/JEDEC J-STD-020
ESD		750	V	According to JEDEC STD 22, method A114, Human Body Model (HBM)
ESD		400	V	According to JEDEC STD 22, C101C, Charged Device Model (CDM)

Table 1: Absolute Maximum Ratings

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

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