DA14580-01AT2
Bluetooth Low Energy System-on-Chip (SoC)The DA14580-01AT2 is a bluetooth low energy system-on-chip (soc) from Dialog Semiconductor. View the full DA14580-01AT2 datasheet below including pinout.
Manufacturer
Dialog Semiconductor
Category
Bluetooth Low Energy System-on-Chip (SoC)
Overview
Part: DA14580-01AT2 — Dialog Semiconductor Type: Bluetooth Low Energy System-on-Chip (SoC) Description: A fully integrated Bluetooth V4.2 low energy SoC featuring an ARM Cortex-M0 processor, 32 kB OTP, 42 kB System SRAM, 84 kB ROM, and a 2.4 GHz CMOS transceiver with -93 dBm receiver sensitivity and 0 dBm transmit output power.
Operating Conditions:
- Supply voltage: Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V) battery cells
- Max CPU clock: 16 MHz
Absolute Maximum Ratings:
Key Specs:
- CPU: 16 MHz 32-bit ARM Cortex-M0
- OTP Memory: 32 kB
- System SRAM: 42 kB
- ROM: 84 kB
- Retention SRAM: 8 kB
- Transmit Output Power: 0 dBm
- Receiver Sensitivity: -93 dBm
- I2C Bus Speed: 100 kHz, 400 kHz
- UART Baud Rate: up to 1 MBd
Features:
- Complies with Bluetooth V4.2
- Dedicated Link Layer Processor
- AES-128 bit encryption Processor
- Integrated Buck/Boost DC-DC converter
- 10-bit ADC for battery voltage measurement
- Digital controlled oscillators (16 MHz crystal/RC, 32 kHz crystal/RCX)
- General purpose, Capture and Sleep timers
- P0, P1, P2 and P3 ports with 3.3 V tolerance
- Single wire antenna interface
Applications:
- Standalone application processor
- Data pump in hosted systems
Package:
- WLCSP 34 pins, 2.436 mm x 2.436 mm
- QFN 40 pins, 5 mm x 5 mm
- QFN 48 pins, 6 mm x 6 mm
- KGD (wafer, dice)
Pin Configuration
DA14580-01AT2 Pinout
Package: QFN48
| Pin Number | Pin Name | Type | Drive (mA) | Reset State | Description |
|---|---|---|---|---|---|
| Port 0 | |||||
| 1 | P0_0 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 2 | P0_1 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 3 | P0_2 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 4 | P0_3 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 5 | P0_4 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 6 | P0_5 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 7 | P0_6 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 8 | P0_7 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| Port 1 | |||||
| 9 | P1_0 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 10 | P1_1 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 11 | P1_2 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 12 | P1_3 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 13 | P1_4/SW_CLK | DIO | 4.8 | I-PD | INPUT JTAG clock signal. Can also be used as a GPIO. INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 14 | P1_5/SWDIO | DIO | 4.8 | I-PU | INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and control communication. Can also be used as a GPIO. INPUT/OUTPUT with selectable pull up/down resistor. Pull-up enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| Port 2 | |||||
| 15 | P2_0 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 16 | P2_1 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 17 | P2_2 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 18 | P2_3 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 19 | P2_4 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 20 | P2_5 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 21 | P2_6 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 22 | P2_7 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 23 | P2_8 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 24 | P2_9 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| Port 3 | |||||
| 25 | P3_0 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 26 | P3_1 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 27 | P3_2 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 28 | P3_3 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 29 | P3_4 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 30 | P3_5 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 31 | P3_6 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| 32 | P3_7 | DIO | 4.8 | I-PD | INPUT/OUTPUT with selectable pull up/down resistor. Pull-down enabled during and after reset. General purpose I/O port bit or alternate function nodes. Contains state retention mechanism during power down. |
| Clock Inputs | |||||
| 33 | XTAL16Mp | AI | — | — | INPUT. Crystal input for the 16 MHz XTAL |
| 34 | XTAL16Mm | AO | — | — | OUTPUT. Crystal output for the 16 MHz XTAL |
| 35 | XTAL32kp | AI | — | — | INPUT. Crystal input for the 32.768 kHz XTAL |
| 36 | XTAL32km | AO | — | — | OUTPUT. Crystal output for the 32.768 kHz XTAL |
| RF Interface | |||||
| 37 | RFIOp | AIO | — | — | RF input/output. Impedance 50 Ω |
| 38 | RFIOm | AIO | — | — | RF ground |
| Power Supply | |||||
| 39 | VBAT3V | AIO | — | — | INPUT/OUTPUT. Battery connection. Used for a single coin battery (3 V). If an alkaline or a NiMH battery (1.5 V) is attached to pin VBAT1V, this is the second output of the DC-DC converter. |
| 40 | VBAT1V | AI | — | — | INPUT. Battery connection. Used for an alkaline or a NiMh battery (1.5 V). If a single coin battery (3 V) is attached to pin VBAT3V, this pin must be connected to GND. |
| 41 | SWITCH | AIO | — | — | INPUT/OUTPUT. Connection for the external DC-DC converter inductor. |
| 42 | VDCDC | AO | — | — | Output of the DC-DC converter |
| 43 | GND | AIO | — | — | Ground |
| 44 | GND | AIO | — | — | Ground |
| 45 | GND | AIO | — | — | Ground |
| 46 | GND | AIO | — | — | Ground |
| Miscellaneous | |||||
| 47 | RST | DI | — | — | INPUT. Reset signal (active high). Must be connected to GND if not used. |
| 48 | VPP | AI | — | — | INPUT. This pin is used while OTP programming and testing. OTP programming: VPP = 6.7 V ± 0.1 V. OTP Normal operation: leave VPP floating. |
Notes
- Port 3 (P3_0–P3_7) is only available on the QFN48 package (DA14580-01AT2).
- Port 2.8–2.9 (P2_8–P2_9) are only available on QFN40/QFN48 packages.
- Pin numbering extracted from the QFN48 pin assignment diagram (Figure 2).
- P1_4 and P1_5 have dual functions: GPIO and JTAG debug interface (SW_CLK and SWDIO respectively).
- All GPIO pins (P0–P3) support state retention during power down and have selectable pull-up/pull-down resistors.
- Multiple GND pins (43–46) provide ground connections; all are electrically equivalent.
Package Information
Figure 1: QFN48 Package Outline Drawing
Figure 1: QFN48 Package Outline Drawing
Figure 2: QFN40 Package Outline Drawing
Figure 2: QFN40 Package Outline Drawing
Figure 3: WLCSP34 Package Outline Drawing
Figure 3: WLCSP34 Package Outline Drawing
Ordering Information
| Part Number | Package | Size (mm) | Shipment Form | Pack Quantity | Category |
|---|---|---|---|---|---|
| DA14580-01UNA | WLCSP34 | 2.436 x 2.436 | Mini-reel | 50/100/1000 | Samples |
| DA14580-01A31 | QFN48 | 6 x 6 | Tray | 50 | Samples |
| DA14580-01AT1 | QFN40 |
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| DA14580 | Dialog Semiconductor | — |
| DA14580-01A31 | Dialog Semiconductor | — |
| DA14580-01A32 | Dialog Semiconductor | — |
| DA14580-01AT1 | Dialog Semiconductor | — |
| DA14580-01PXA31 | Dialog Semiconductor | — |
| DA14580-01PXA32 | Dialog Semiconductor | — |
| DA14580-01PXAT1 | Dialog Semiconductor | — |
| DA14580-01PXAT2 | Dialog Semiconductor | — |
| DA14580-01PXUNA | Dialog Semiconductor | — |
| DA14580-01UNA | Dialog Semiconductor | — |
| DA14580-01WC4 | Dialog Semiconductor | — |
| DA14580-01WO4 | Dialog Semiconductor | — |
| DA14580-NN | Dialog Semiconductor | — |
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