DA14580-01PXA32

Part: DA14580-01AT2 — Dialog Semiconductor Type: Bluetooth Low Energy System-on-Chip (SoC) Description: A fully integrated Bluetooth V4.2 low energy SoC featuring an ARM Cortex-M0 processor, 32 kB OTP, 42 kB System SRAM, 84 kB ROM, and a 2.4 GHz CMOS transceiver with -93 dBm receiver sensitivity and 0 dBm transmit output power.

Operating Conditions:

• Supply voltage: Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V) battery cells
• Max CPU clock: 16 MHz

Absolute Maximum Ratings:

Key Specs:

• CPU: 16 MHz 32-bit ARM Cortex-M0
• OTP Memory: 32 kB
• System SRAM: 42 kB
• ROM: 84 kB
• Retention SRAM: 8 kB
• Transmit Output Power: 0 dBm
• Receiver Sensitivity: -93 dBm
• I2C Bus Speed: 100 kHz, 400 kHz
• UART Baud Rate: up to 1 MBd

Features:

• Complies with Bluetooth V4.2
• Dedicated Link Layer Processor
• AES-128 bit encryption Processor
• Integrated Buck/Boost DC-DC converter
• 10-bit ADC for battery voltage measurement
• Digital controlled oscillators (16 MHz crystal/RC, 32 kHz crystal/RCX)
• General purpose, Capture and Sleep timers
• P0, P1, P2 and P3 ports with 3.3 V tolerance
• Single wire antenna interface

Applications:

• Standalone application processor
• Data pump in hosted systems

Package:

• WLCSP 34 pins, 2.436 mm x 2.436 mm
• QFN 40 pins, 5 mm x 5 mm
• QFN 48 pins, 6 mm x 6 mm
• KGD (wafer, dice)

The Programmable Pin Assignment (PPA) provides a multiplexing function to the I/Os of on-chip peripherals. Any peripheral input or output signal can be freely mapped to any I/O port bit by setting:

Pxy_MODE_REG[4-0]:

0x00 to 0x16: Peripheral IO ID (PID)

Refer to the Px_MODE_REGs for an overview of the available PIDs. Analog ADC has fixed pin assignment in order to limit interference with the digital domain. The SWD interface (JTAG) is mapped on P1_4 and P1_5.

Figure 1: QFN48 Package Outline Drawing

Figure 1: QFN48 Package Outline Drawing

Figure 2: QFN40 Package Outline Drawing

Figure 2: QFN40 Package Outline Drawing

Figure 3: WLCSP34 Package Outline Drawing

Figure 3: WLCSP34 Package Outline Drawing