CH32V003F4U6
CH32V003 Datasheet
The CH32V003F4U6 is an electronic component from WCH. CH32V003 Datasheet. View the full CH32V003F4U6 datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
WCH
Overview
Part: CH32V003 series
Type: Industrial-grade General-purpose Microcontroller
Key Specs:
- System Main Frequency: 48MHz
- Rated Operating Voltage: 3.3V or 5V
- Operating Voltage Range: 2.7V to 5.5V
- Operating Temperature Range: -40°C to 85°C
- SRAM: 2KB
- CodeFlash: 16KB
- DMA Channels: 7
- ADC Resolution: 10-bit
- External ADC Channels: 8
- Internal ADC Channels: 2
- GPIO Pins: Up to 18
Features:
- Qingke 32-bit RISC-V core, RV32EC instruction set
- Fast Programmable Interrupt Controller (PFIC)
- Supports 2 levels of interrupt nesting
- Single-wire debugging interface
- Low Power Modes: Sleep, Standby
- Built-in 24MHz RC oscillator
- Built-in 128KHz RC oscillator
- External support for 4MHz to 25MHz high-speed oscillator
- Power-on/Power-off Reset (POR/PDR)
- Programmable Voltage Monitor (PVD)
- 1 set of operational amplifier, comparator
- 1 16-bit advanced timer with dead-time control and emergency brake
- 1 16-bit general-purpose timer
- 2 watchdog timers (independent and window type)
- 1 32-bit system time-base timer
- 1 USART interface
- 1 I2C interface
- 1 SPI interface
- 96-bit unique chip ID
Applications:
- null
Package:
- SOP
- TSSOP
- QFN
Features
- Core
- Qingke 32-bit RISC-V core, RV32EC instruction set
- Fast Programmable Interrupt Controller + hardware interrupt stack
- Supports 2 levels of interrupt nesting
- Supports system main frequency 48MHz
Memory
- 2KB Volatile Data Storage Area SRAM
- 16KB Program Storage Area CodeFlash
- 1920B System Boot Program Storage Area BootLoader
- 64B System Non-Volatile Configuration Information Storage Area
- 64B User-Defined Information Storage Area
Power Management and Low Power Consumption
- System Power Supply VDD Rated: 3.3V or 5V
- Low Power Modes: Sleep, Standby
System Clock, Reset
- Built-in factory-calibrated 24MHz RC oscillator
- Built-in 128KHz RC oscillator
- External support for 4~25MHz high-speed oscillator
- Power-on/Power-off Reset, Programmable Voltage Monitor
- 7-channel General-purpose DMA Controller
- 7 channels, supports circular buffer management
- Supports TIMx/ADC/USART/I2C/SPI
- 1 set of operational amplifier, comparator: connected to ADC and TIM2
- 1 set of 10-bit analog-to-digital conversion ADC
- Analog input range: 0~VDD
- 8 external signal channels + 2 internal signal channels
- Supports external delayed trigger
- Multiple Timers
- 1 16-bit advanced timer, providing dead-time control and emergency brake, providing complementary PWM output for motor control
- 1 16-bit general-purpose timer, providing input capture/output compare/PWM/pulse counting and incremental encoder input
- 2 watchdog timers (independent and window type)
- System time-base timer: 32-bit counter
- Standard Communication Interfaces
- 1 USART interface
- 1 I2C interface
- 1 SPI interface
- GPIO Ports
- 3 sets of GPIO ports, 18 I/O pins
- Maps one external interrupt
- Security Features: 96-bit unique chip ID
- Debug Mode: Serial Single-Wire Debug Interface
- Package Type: SOP, TSSOP, QFN
| Model | Flash | SRAM | Pin Count | General-purpose I/O | Advanced Timer | General-purpose Timer | Watchdog | System Clock Source | ADC Channels | SPI | I2C | USART | Package Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CH32V003F4P6 | 16K | 2K | 20 | 18 | 1 | 1 | 2 | 3 | 8 | 1 | 1 | 1 | TSSOP20 |
| CH32V003F4U6 | 16K | 2K | 20 | 18 | 1 | 1 | 2 | 3 | 8 | 1 | 1 | 1 | QFN20 |
| CH32V003A4M6 | 16K | 2K | 16 | 14 | 1 | 1 | 2 | 3 | 6 | - | 1 | 1 | SOP16 |
| CH32V003J4M6 | 16K | 2K | 8 | 6 | 1 | 1 | 2 | 3 | 6 | - | 1 | 1 | SOP8 |
Pin Configuration
Table 2-1 Pin Definition
Note: The pin function descriptions in the table below apply to all functions and do not involve specific product models. Peripheral resources vary between different models. Please confirm whether this function is available based on the product model resource table before viewing.
| Pin Number | Main Function | |||||
|---|---|---|---|---|---|---|
| SOP16 | TSSOP20 | QFN20 | SOP8 | Pin Name | Pin Type | (After Reset) |
| - | - | 0 | - | VSS | P | VSS |
| 8 | 1 | 18 | 8 | PD4 | I/O/A | PD4 |
| 9 | 2 | 19 | 8 | PD5 | I/O/A | PD5 |
| 10 | 3 | 20 | 1 | PD6 | I/O/A | PD6 |
| 11 | 4 | 1 | - | PD7 | I/O/A | PD7 |
| 12 | 5 | 2 | 1 | PA1 | I/O/A | PA1 |
| 13 | 6 | 3 | 3 | PA2 | I/O/A | PA2 |
| 14 | 7 | 4 | 2 | VSS | P | VSS |
| - | 8 | 5 | - | PD0 | I/O/A | PD0 |
| 15 | 9 | 6 | 4 | VDD | P | VDD |
| 16 | 10 | 7 | - | PC0 | I/O | PC0 |
| 1 | 11 | 8 | 5 | PC1 | I/O/FT | PC1 |
| 2 | 12 | 9 | 6 | PC2 | I/O/FT | PC2 |
| 3 | 13 | 10 | - | PC3 | I/O | PC3 |
| 4 | 14 | 11 | 7 | PC4 | I/O/A | PC4 |
| - | 15 | 12 | - | PC5 | I/O/FT | PC5 |
| 5 | 16 | 13 | - | PC6 | I/O/FT | PC6 |
| 6 | 17 | 14 | - | PC7 | I/O | PC7 |
| 7 | 18 | 15 | 8 | PD1 | I/O/A | PD1 |
| - | 19 | 16 | - | PD2 | I/O/A | PD2 |
| - | 20 | 17 | - | PD3 | I/O/A | PD3 |
| --- | ---- | ---- | --- | ----- | ------- | ----- |
| --- | ---- | ---- | --- | ----- | ------- | ----- |
- Note: 1.TIM2_CH1, TIM2_ETR;
- 2. For remapping functions, the value after the underscore indicates the corresponding bit configuration value in the AFIO register. For example: T1CH4_3 means the corresponding bit in the AFIO register is configured as 11b;
- 3. Table abbreviation explanation:
- I = TTL/CMOS level Schmitt input;
- O = CMOS level tri-state output;
- P = Power;
- FT = 5V tolerant;
- A = Analog signal input or output.
Electrical Characteristics
3.1 Test Conditions
Unless otherwise specified and noted, all voltages are referenced to VSS.
All minimum and maximum values are guaranteed under the worst environmental temperature, supply voltage, and clock frequency conditions. Typical values are based on normal temperature 25°C and VDD = 3.3V or 5V environment for design guidance.
Data obtained through comprehensive evaluation, design simulation, or process characterization will not be tested on the production line. Based on comprehensive evaluation, minimum and maximum values are statistically obtained after sample testing. Unless specifically stated as measured values, characteristic parameters are guaranteed by comprehensive evaluation or design.
Power supply scheme:
Figure 3-1 Typical circuit for conventional power supply
3.2 Absolute Maximum Ratings
Operating at or exceeding absolute maximum ratings may cause the chip to malfunction or even be damaged.
Table 3-1 Absolute Maximum Ratings Parameters
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Table 3-7-2 Typical Current Consumption in Sleep Mode, with Data Processing Code Running from Internal Flash or SRAM (VDD = 5V)
| Symbol Parameter | Condition | Typical Value | ||
|---|---|---|---|---|
| All Peripherals Enabled | ||||
| Supply Current in Sleep Mode (Peripherals Powered and Clocks Maintained) | External Clock | FHCLK = 48MHz | 4.7 | |
| (1) IDD | FHCLK = 24MHz FHCLK = 16MHz FHCLK = 8MHz FHCLK = 750KHz | 2.8 2.5 1.7 1.2 | ||
| Running on High-Speed Internal RC Oscillator (HSI), using AHB Prescaler to Reduce Frequency | FHCLK = 48MHz FHCLK = 24MHz FHCLK = 16MHz FHCLK = 8MHz FHCLK = 750KHz | 4.1 2.1 1.8 1.0 0.5 |
Table 3-8 Typical Current Consumption in Standby Mode
| Symbol | Parameter | Condition | Typical Value | Unit | |
|---|---|---|---|---|---|
| IDD Supply Current in Standby Mode | VDD = 3.3V | 9.1 | |||
| LSI On | VDD = 5V VDD = 3.3V | 9.4 7.6 | uA | ||
| LSI Off | VDD = 5V | 8.0 |
2. Test conditions: At normal temperature with VDD = 3.3V or 5V, initial main frequency HSI=24M, all IO ports configured as pull-down inputs.
3.3.5 External Clock Source Characteristics
Table 3-9 External High-Speed Clock
| Symbol | Parameter | Condition | Min | Typical | Max | Unit |
|---|---|---|---|---|---|---|
| FHSE_ext | External Clock Frequency | 4 | 24 | 25 | MHz | |
| (1) VHSEH | OSC_IN Input Pin High-Level Voltage | 0.8VDD | VDD | V | ||
| (1) VHSEL | OSC_IN Input Pin Low-Level Voltage | 0 | 0.2VDD | V | ||
| Cin(HSE) | OSC_IN Input Capacitance | 5 | pF | |||
| DuTy(HSE) | Duty Cycle | 40 | 50 | 60 | % | |
| IL | OSC_IN Input Leakage Current | ±1 | uA |
Note: 1. Failure to meet this condition may cause level recognition errors.
Figure 3-3 External High-Frequency Clock Source Circuit
Table 3-10 High-Speed External Clock Generated Using a Crystal/Ceramic Resonator
| Symbol | Parameter | Condition | Min | Typical | Max | Unit |
|---|---|---|---|---|---|---|
| FOSC_IN | Resonator Frequency | 4 | 24 | 25 | MHz | |
| RF | Feedback Resistor (No External Required) | 250 | kΩ | |||
| C | Recommended Load Capacitance and Corresponding Crystal Series Resistance RS | (1) RS = 60Ω | 20 | pF | ||
| I2 | HSE Drive Current | VDD = 3.3V,20p Load | 0.32 | mA | ||
| gm | Oscillator Transconductance | Startup | 6.8 | mA/V | ||
| tSU(HSE) | Startup Time | VDD = 3.3V, 24M Crystal | 2 | ms |
Note: 1. For 25M crystals, ESR is recommended not to exceed 60 ohms; for frequencies below 25M, this can be relaxed appropriately.
Circuit Reference Design and Requirements:
The crystal's load capacitance should follow the crystal manufacturer's recommendations; typically CL1=CL2.
Figure 3-4 Typical Circuit for External 24M Crystal
3.3.6 Internal Clock Source Characteristics
Table 3-11 Internal High-Speed (HSI) RC Oscillator Characteristics
| Symbol | Parameter | Condition | Min | Typical | Max | Unit |
|---|---|---|---|---|---|---|
| FHSI | Frequency (Calibrated) | 24 | MHz | |||
| DuCyHSI | Duty Cycle | 45 | 50 | 55 | % | |
| ACCHSI | HSI Oscillator Accuracy (Calibrated) | TA = 0°C~70°C | -1.2 | 1.6 | % | |
| TA = -40°C~85°C | -2.2 | 2.2 | % | |||
| tSU(HSI) | HSI Oscillator Startup Time | 10 | us | |||
| IDD |
3.3.11 TIM Timer Characteristics
Table 3-20 TIMx Characteristics
| Symbol | Parameter | Condition | Min | Max | Unit |
|---|---|---|---|---|---|
| tres(TIM) | 1 | tTIMxCLK | |||
| Timer reference clock | fTIMxCLK = 48MHz | 20.8 | ns | ||
| FEXT | 0 | fTIMxCLK/2 | MHz | ||
| Timer external clock frequency for CH1 to CH4 | fTIMxCLK = 48MHz | 0 | 24 | MHz | |
| ResTIM | Timer resolution | 16 | bit | ||
| tCOUNTER | 16 bit counter clock period when internal clock is selected | 1 | 65536 | tTIMxCLK | |
| fTIMxCLK = 48MHz | 0.0208 | 1363 | us | ||
| tMAX_COUNT | 65535 | tTIMxCLK | |||
| Maximum possible count | fTIMxCLK = 48MHz | 1363 | us |
3.3.12 I2C Interface Characteristics
Figure 3-6 I2C Bus Timing Diagram
Table 3-21 I2C Interface Characteristics
| Symbol | Parameter | Standard I2C | Fast I2C | |
|---|---|---|---|---|
| Min | Max | Min | ||
| tw(SCKL) | SCL clock low time | 4.7 | 1.2 | |
| tw(SCKH) | SCL clock high time | 4.0 | 0.6 | |
| tSU(SDA) | SDA data setup time | 250 | 100 | |
| th(SDA) | SDA data hold time | 0 | 0 | |
| tr(SDA)/tr(SCL) | SDA and SCL rise time | 1000 | 20 | |
| tf(SDA)/tf(SCL) | SDA and SCL fall time | 300 | ||
| th(STA) | Start condition hold time | 4.0 | 0.6 | |
| tSU(STA) | Repeated start condition setup time | 4.7 | 0.6 | |
| tSU(STO) | Stop condition setup time | 4.0 | 0.6 | |
| tw(STO:STA) | Time from stop condition to start condition (bus free) | 4.7 | 1.2 | |
| Cb | Capacitive load per bus | 400 |
Absolute Maximum Ratings
Operating at or exceeding absolute maximum ratings may cause the chip to malfunction or even be damaged.
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