CH32F203C8U6

Part: CH32F203C8T6

Type: 32-bit ARM Cortex-M3 Microcontroller

Description: 32-bit ARM Cortex-M3 core microcontroller operating at up to 144 MHz, featuring dual USB (Host/Device), 1 CAN, 2 operational amplifier comparators, 4 USARTs, 2 I2Cs, 12-bit ADC, 20KB SRAM, and 224KB Flash.

Operating Conditions:

• Supply voltage: 2.4–3.6 V (3–3.6 V when using USB)
• Operating temperature: -40 to 85 °C
• Max system frequency: 144 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max total supply current: 150 mA
• Max storage temperature: 125 °C

Key Specs:

• Core: 32-bit ARM Cortex-M3
• Max CPU Frequency: 144 MHz
• SRAM: Up to 20 KB
• CodeFlash: Up to 224 KB
• USB: 2 (Host/Device, Full-Speed)
• CAN: 1 (2.0B active)
• I2C: 2 interfaces
• USART: 4 interfaces
• ADC: 12-bit
• OPA/Comparator: 2

Features:

• Single-cycle multiplication and hardware division
• Interrupt technology, Fault handling mechanism
• Dual USB interfaces (Host and Device)
• 1 CAN interface (2.0B active)
• 2 operational amplifier comparators
• 4 USARTs, 2 I2Cs
• 12-bit ADC, 10 Touchkey channels
• Multiple timers
• Power-On Reset (POR) / Power-Down Reset (PDR)
• Programmable Voltage Detector (PVD)
• Sleep, Stop, Standby low-power modes
• Serial 2-Wire Debug Interface (SWD)

Package:

• LQFP32
• LQFP48
• QFN48

• l Core:
• 32-bit ARM Cortex-M3 core
• • Single-cycle multiplication and hardware division
• • Interrupt technology, Fault handling mechanism
• • System main frequency 144MHz

Table 3-1 CH32F203x6/x8 Pin Definition

Note: The pin function descriptions in the table below cover all functions and do not refer to specific product models. Peripheral resources vary between different models. Before viewing, please confirm whether a function is available based on the product model resource table.

13

15

Note 1: Table Abbreviation Explanation

O = CMOS level tri-state output;

A = Analog signal input or output;

P = Power supply;

FT = 5V tolerant;

ANT = RF signal input/output (antenna);

Note 2: PC13, PC14 and PC15 pins are powered through a power switch, which can only sink a limited current (3mA). Therefore, when these three pins are used as output pins, they have the following restrictions: only one pin can act as an output at the same time, when acting as an output pin, it can only operate in 2MHz mode, the maximum drive load is 30pF, and it cannot be used as a current source (e.g., driving an LED).

Note 3: These pins are in their main function state during the first power-up in the backup domain. Afterwards, even if reset, the state of these pins is controlled by the backup domain registers (these registers are not reset by the main reset system). For specific information on how to control these I/O ports, please refer to the relevant chapters on the battery backup domain and BKP registers in the CH32xRM manual.

Note 4: The BOOT0 and PB8 pins are co-packaged on the chip. It is recommended to connect an external 500K pull-down resistor to ensure the chip stably enters program flash memory boot mode upon power-up. Additionally, this PB8 pin and its multiplexed functions only retain output drive capability; all input functions have been disabled.

Note 5: For chips where the BOOT0 pin is not brought out, it will be internally pulled down to GND. For chips where the BOOT1/PB2 pin is not brought out, it will be internally pulled down to GND. In this case, if configuring the I/O port state when entering low-power mode, it is recommended to use the input pull-down mode for the BOOT1/PB2 pins to prevent additional current generation.

16

Critical or exceeding absolute maximum ratings may lead to abnormal chip operation or even damage.