ATSAML21J18B-MUT-SLL

Part: ATSAML21J18B-AUT — Atmel

Type: 32-bit ARM Cortex-M0+ Microcontroller

Description: Ultra low-power 32-bit ARM Cortex-M0+ microcontroller running at up to 48 MHz, with up to 256 KB Flash and 40 KB SRAM, featuring sophisticated power management and highly configurable peripherals.

Operating Conditions:

• Supply voltage: 1.62–3.63V
• Operating temperature: -40 to 85 °C
• Max CPU frequency: 48 MHz

Key Specs:

• CPU: Arm Cortex-M0+
• Max CPU frequency: 48 MHz
• Flash memory: Up to 256 KB
• SRAM main memory: Up to 32 KB
• SRAM low-power memory: Up to 8 KB
• ADC: 12-bit, 1 MSPS, up to 20 channels
• DAC: Two 12-bit, 1 MSPS dual output
• SERCOM: Up to six, configurable as USART, I2C (up to 3.4 MHz), SPI, LIN slave

Features:

• Arm Cortex-M0+ CPU running at up to 48 MHz
• Up to 256 KB in-system self-programmable Flash
• Idle, Stand-by, Backup, and Off Sleep modes
• Embedded Buck/LDO regulator
• 16-channel Direct Memory Access Controller (DMAC)
• Full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
• Peripheral Touch Controller (PTC) with 169-channel capacitive touch and proximity sensing
• Two-pin Serial Wire Debug (SWD) interface

Package:

• 64-pin TQFP, QFN, WLCSP
• 48-pin TQFP, QFN
• 32-pin TQFP, QFN

• Processor
• -Arm Cortex-M0+ CPU running at up to 48 MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer
• Memories
• -32/64/128/256-KB in-system self-programmable Flash
• -1/2/4/8-KB Flash Read-While-Write section
• -4/8/16/32-KB SRAM main memory
• -2/4/8/8-KB SRAM low-power memory
• System
• -Power-on Reset (POR) and Brown-out Detection (BOD)
• -Internal and external clock options
• -External Interrupt Controller (EIC)
• -16 external interrupts
• -One non-maskable interrupt
• -Two-pin Serial Wire Debug (SWD) programming, testing, and debugging interface
• Low Power
• -Idle, Stand-by, Backup, and Off Sleep modes
• -SleepWalking peripherals
• -Static and Dynamic Power Gating Architecture
• -Battery backup support
• -Two performance levels
• -Embedded Buck/LDO regulator supporting on-the-fly selection
• Peripherals
• -16-channel Direct Memory Access Controller (DMAC)
• -12-channel Event System
• -Up to five 16-bit Timer/Counters (TC) including one low-power TC, each configurable as:
• 16-bit TC with two compare/capture channels
• 8-bit TC with two compare/capture channels
• 32-bit TC with two compare/capture channels, by using two TCs

The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totempole, or pull configuration.

As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided.

The I/O pin configurations are described further in this chapter, and summarized in Table 29-2.

Stresses beyond those listed in Table 46-1 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 46-1. Absolute Maximum Ratings

1. Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of GPIOs.

Also note that each VDD/GND pair is connected to two clusters, so current consumption through the pair will be a sum of the clusters' source/sink currents.

This device is sensitive to electrostatic discharges (ESD). Improper handling may lead to permanent performance degradation or malfunctioning. Handle the device following best practice ESD protection rules:

Be aware that the human body can accumulate charges large enough to impair functionality or destroy the device.

The following table summarizes the thermal resistance data depending on the package.

Table 50-1. Thermal Resistance Data